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arunbasilpaul/README.md

ABOUT ME

I'm a Mechatronics Graduate from Universität Siegen who is passionate about creating safety-critical embedded systems, saving and bettering lives accessible to everyone. After completing my Bachelor in Mechanical Engineering from NMAMIT (India), I developed an interest in FPGAs during my Master's at the University of Siegen (Deutschland) and have focused on developing solutions for medical devices such as a hardware OS for the TE0802 Zynq Ultrascale+, custom IPs for Hardware acceleration using VHDL and Verilog, memory allocation pattern recognition to replicate faster memory retrieval; encouraging efficient memory usage, reducing the load on small-medium sized FPGAs and pre-fetching for speedier memory access for the past ✌️ years and counting.....

INTERESTED TOPICS

  • RTL Programming with custom IP creation
  • Prefetching
  • Time-Triggreed systems
  • Pynq-Linux OS creation
  • Machine Learning

PROGRAMMING LANGUAGES

  • VHDL, Verilog, Python, C, C++, Embedded C

SOFTWARES

  • Vivado, Vitis, Vitis HLS, SDK, ModelSim, Pynq, PetaLinux, Jupyter Notebook, Visual Studio

PROJECTS

  • Optimizing deep learning model performance through the integartion of a Time-triggered memory cache with Versatile Tensor Accelerator
  • Development of custom Linux OS for custom boards (Case: TE0802 Ultrascale+ with TVM/VTA interface)
  • DRAM Pattern analysis for VTA Load module schedule simplification
  • Wireless Aerial Painter - Funded by the Govt. of India
  • FPGA-based Neural Network implementation on TE0802 board using HLS and RTL programming

MY HOBBIES:

  • Nature photography 🌲📷
  • Hiking 🥾⛺🚵🧗🏞️
  • Reading productivity and philosophical books 📚

Popular repositories Loading

  1. arunbasilpaul arunbasilpaul Public

  2. Alarm_Clock Alarm_Clock Public

    A HDL twist to the traditional Alarm Clock with opportunity to set an alarm and a 7-segment display

    VHDL

  3. Traffic_Lights Traffic_Lights Public

    This is a simple project of a normal Traffic signal that can change during emergencies to accommodate situations such as an ambulance passing through

    VHDL

  4. Custom_PYNQ_OS_for_TE0802_with_PetaLinux Custom_PYNQ_OS_for_TE0802_with_PetaLinux Public

    Jupyter Notebook

  5. FIFO-Synchronous-vs-Asynchronous FIFO-Synchronous-vs-Asynchronous Public

    This project explores the simplicity / complexity of a synchronous and asynchronous FIFO. FIFO is a valuable component during data transmission, in particular during clock-domain crossing for multi…

    VHDL