diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5ca9764693988..08d4cd475722a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -328,6 +328,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-rpi-cm4-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-nx5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts index d461ba2e3de84..2ca1e3293eab2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -312,6 +312,10 @@ &i2s0_sdo0>; }; +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; &pwm4 { status = "okay"; @@ -329,6 +333,7 @@ &hdmi0 { status = "okay"; + enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; }; &hdmi0_in_vp0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts new file mode 100644 index 0000000000000..69587ce849678 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-rpi-cm4-io.dts @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Radxa Limited + * + */ + +/dts-v1/; + +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa CM5 RPI CM4 IO"; + compatible = "radxa,cm5-rpi-cm4-io", "rockchip,rk3588"; + + /delete-node/ chosen; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + usb20_reset: usb-up-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_reset_pin>; + regulator-name = "usb20_reset"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi0_sound: hdmi0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gpio_leds { + activity-led-green { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + pwr-led-red { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; +}; + +&sdhci { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; + cursor-win-id = ; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>; + clock-names = "hdmi0_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + + emc2301: emc2301@2f { + status = "okay"; + compatible = "microchip,emc2301"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + microchip,pwm-separate; + microchip,cooling-levels = <10>; + channel@0 { + reg = <0>; + pwm-min = <0>; + }; + }; + + pcf85063: pcf85063@51 { + compatible = "nxp,pcf85063"; + status = "okay"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; +}; + +&threshold { + temperature = <60000>; +}; + +&soc_thermal { + cooling-maps { + sustainable-power = <5000>; /* milliwatts */ + map3 { + trip = <&target>; + cooling-device = + <&emc2301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + map4 { + trip = <&threshold>; + cooling-device = + <&emc2301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <8192>; + }; + }; +}; + +&pinctrl { + + usb { + usb20_reset_pin: usb20-reset { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd>; + status = "okay"; +}; + +/* Fix the issue of board howling */ +&vdd_cpu_big0_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_big1_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_npu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_gpu_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_cpu_lit_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_log_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_vdenc_s0 { + regulator-initial-mode = <1>; +}; + +&vdd_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vdd2_ddr_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_2v0_pldo_s3 { + regulator-initial-mode = <1>; +}; + +&vcc_3v3_s3 { + regulator-initial-mode = <1>; +}; + +&vddq_ddr_s0 { + regulator-initial-mode = <1>; +}; + +&vcc_1v8_s3 { + regulator-initial-mode = <1>; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0-A3 */ + "", "", "", "", + /* GPIO0_A4-A7 */ + "", "", "", "", + + /* GPIO0_B0-B3 */ + "", "", "", "", + /* GPIO0_B4-B7 */ + "", "PIN_8", "PIN_10", "", + + /* GPIO0_C0-C3 */ + "", "", "", "", + /* GPIO0_C4-C7 */ + "", "", "", "PIN_5", + + /* GPIO0_D0-D3 */ + "PIN_3", "", "", "", + /* GPIO0_D4-D7 */ + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0-A3 */ + "", "PIN_38", "PIN_40", "PIN_12", + /* GPIO1_A4-A7 */ + "PIN_36", "", "PIN_18", "PIN_16", + + /* GPIO1_B0-B3 */ + "PIN_22", "PIN_21", "PIN_19", "PIN_23", + /* GPIO1_B4-B7 */ + "PIN_24", "PIN_26", "", "", + + /* GPIO1_C0-C3 */ + "", "", "PIN_11", "PIN_15", + /* GPIO1_C4-C7 */ + "", "PIN_13", "", "PIN_29", + + /* GPIO1_D0-D3 */ + "", "", "", "", + /* GPIO1_D4-D7 */ + "PIN_7", "", "PIN_28", "PIN_27"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0-A3 */ + "", "", "", "", + /* GPIO2_A4-A7 */ + "", "", "", "", + + /* GPIO2_B0-B3 */ + "", "", "", "", + /* GPIO2_B4-B7 */ + "", "", "", "", + + /* GPIO2_C0-C3 */ + "", "", "", "", + /* GPIO2_C4-C7 */ + "", "", "", "", + + /* GPIO2_D0-D3 */ + "", "", "", "", + /* GPIO2_D4-D7 */ + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0-A3 */ + "", "", "", "", + /* GPIO3_A4-A7 */ + "", "", "", "", + + /* GPIO3_B0-B3 */ + "", "", "", "", + /* GPIO3_B4-B7 */ + "", "", "", "", + + /* GPIO3_C0-C3 */ + "", "", "", "", + /* GPIO3_C4-C7 */ + "", "", "", "", + + /* GPIO3_D0-D3 */ + "PIN_37", "", "", "", + /* GPIO3_D4-D7 */ + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0-A3 */ + "", "PIN_33", "PIN_31", "", + /* GPIO4_A4-A7 */ + "", "", "", "", + + /* GPIO4_B0-B3 */ + "", "", "PIN_32", "", + /* GPIO4_B4-B7 */ + "", "", "", "", + + /* GPIO4_C0-C3 */ + "", "", "", "", + /* GPIO4_C4-C7 */ + "", "", "", "", + + /* GPIO4_D0-D3 */ + "", "", "", "", + /* GPIO4_D4-D7 */ + "", "", "", ""; +}; diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index a4da4b474ea9d..494bcb9ae33f6 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -175,13 +175,9 @@ static void __dwc3_set_mode(struct work_struct *work) break; } - /* - * When current_dr_role is not set, there's no role switching. - * Only perform GCTL.CoreSoftReset when there's DRD role switching. - */ - if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || - DWC3_VER_IS_PRIOR(DWC31, 190A)) && - desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { + /* For DRD host or device mode only */ + if ((DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC31, 190A)) && + dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg |= DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg);