Firefly Map

The bit(s) column refers to the entry in the internal MCU masks. In the case of two bits for one entry, it is split into separate Tx and Rx modules.

Rev2

Firefly Number	Type	Quad(s)	Bit(s)
F1_1	12 ch	121, 122, 123	0, 1
F1_2	12 ch	125, 126, 127	2, 3
F1_3	12 ch	132, 133, 134	4, 5
F1_4	4 ch	124	6
F1_5	4 ch	128	7
F1_6	4 ch	129	8
F1_7	4 ch	130	9
F2_1	12 ch	121, 122, 123	10, 11
F2_2	12 ch	125, 126, 127	12, 13
F2_3	12 ch	132, 133, 134	14, 15
F2_4	4 ch	124	16
F2_5	4 ch	128	17
F2_6	4 ch	129	18
F2_7	4 ch	130	19

This does not describe the quads that run between the FPGAs. F1 and F2 are identical for Firefly maps.

Rev3

In this version three 4-channel parts are replaced by a 12-channel part, for a total of four 12-channel parts and 2 four-channel parts for each FPGA.

Firefly Number	Type	Quad(s)	Bit(s)
F1_1	12 ch	121, 122, 123	0, 1
F1_2	12 ch	125, 126, 127	2, 3
F1_3	12 ch	128, 128, 130
F1_4	12 ch	132, 133, 134
F1_5	4 ch	124
F1_6	4 ch	131
F2_1	12 ch	121, 122, 123	0, 1
F2_2	12 ch	125, 126, 127	2, 3
F2_3	12 ch	128, 128, 130
F2_4	12 ch	132, 133, 134
F2_5	4 ch	124
F2_6	4 ch	131