NVME_device_PCI_config

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Section 1: PCI Space Config File Info
The Configuration file contains the NVME PCI Express registers which the QEMU
uses to initialize its PCI space. The CFG_NAME tag defines a unique value
that is constant across a set of registers which fall under the same category.

Following are the CFG_NAME's supported by the parser :
PCIHEADER : PCI Header Space
PMCAP     : PCI Power Management Capabilities
MSICAP    : Message Signaled Interrupt Capability
MSIXCAP   : MSI-X Capability (Defaulted in code)
MSIXCAP functionality is not supported for NVME because of the default code
inside the msix.c (msix_add_config), which assumes MSIX should not point to any other
capability.Thus values inside MSIXCAP are ignored!

PXACP     : PCI Express Capability
AERCAP    : Advanced Error Reporting Capability (Not Supported)

It should be noted that PCIHEADER should be the first section followed by
any order of other sections in the file.

The NAME tag indicates the name specific to each register. It should be
noted that, NAME tag can be any general name and does not have to be unique
like CFG_NAME.

The OFFSET tag gives a relative offset of this register in its corresponding
section defined by CFG_NAME. The parser code uses the above offset for
storing the values in the PCI space.

The LENGTH indicates the length in bytes of the resgister defined in
PCI space.

The VALUE tag of the registers is where you set the required values
that the NVME card needs to get initialized with.in some cases, it gives the
offset to next set of capabilities for this NVME.

The reamaining tags indicate a MASK for the registers if it is Read Only, Read
Write, Read Write Clear or Read write Set.If the mask is set to 1 indicates it
has the corresponding capability. For example if RO_MASK = 0x1 then it
indicates that the last bit in that register has a capability of read only.

Each line in the file needs to be no more than 255 charachters and the CFG_NAME
has a limit of 50 charachters.

The order in which the registers are organized in this file is important as it
gives the QEMU parser program the next set of register's identification/
category.

For example consider a VALUE = 0x45 in CAP register under CFG_NAME = PCIHEADER
section.The various register sections are listed as follows in the file from
top to bottom.
PMCAP
MSICAP
MSIXCAP
PXCAP
AERCAP

Since PMCAP just follows the PCIHEADER section in the file, PMCAP will be stored
in PCI space starting at an offset of 0x45 from the start of PCI space.
Note that, offset of 0x45 was extracted from VALUE =0x45 of CAP present in
PCIHEADER section. Likewise all the next pointer fields in capabilities will
point to the next available capabilities in the file in the top to
down order. Thus following is the linkage for the above example

PCIHEADER (CAP) --> PMCAP
PMCAP (NEXT) --> MSICAP
MSICAP (NEXT) --> MSIXCAP
MSIXCAP (NEXT) --> PXCAP
PXCAP (NEXT) --> AERCAP

Thus there is no need of explicilty writing down the order and the specific
offsets. Just maintain the order according to your needs in the memory and
write down the relative offsets (OFFSET) for each section (CFG_NAME), rest
is handled by the Qemu parser.

Values (VALUES) to be written can be either 8 bits, 16 bits or 32 bits with
the appropriate lengths. If you want to write 64 bit values , divide it
into two 32 bit values and enter in the config file.

Section 2: Parsing Syntax
    The Qemu parser, would only look for values under the <REG> and </REG>.
Thus anything written outside the <REG> and </REG> would be considered as
invalid values. Thus this is a good place for writing down comments.
    There are 10 fields inside the <REG> and </REG> header. If some of the
fields are not applicable to a particular register, then just default it
to 0x00. If by mistake you forget to list down some of the entries
between the headers, the parser would take care of it and default it to
0x00.
    <COMMENT> and </COMMENT> is used if you want the parser to neglect the values.
Moreover anything written outside <REG> and </REG> block is also ignored by
the parser

<REG>
	CFG_NAME =PCIHEADER
	NAME = "ID"
	OFFSET = 0x00
	LENGTH = 0x04
	VALUE = 0x01118086
	RO_MASK = 0xFFFFFFFF
	RW_MASK = 0x00000000
	RWC_MASK = 0x00000000
	RWS_MASK = 0x00000000
	DESC = "Identifier"

</REG>

Bits CMD.IOSE and CMD.MSE are defaulted to 1 by Qemu PCI Host
module. You can configure them once the system boots using
the respective driver
<REG>
	CFG_NAME = PCIHEADER
	NAME = "CMD"
	OFFSET = 0x04
	LENGTH = 0x02
	VALUE = 0x03
	RO_MASK = 0xFBF8
	RW_MASK = 0x0447
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Command Register"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "STS"
	OFFSET = 0x06
	LENGTH = 0x02
	VALUE = 0x10
	RO_MASK = 0x4EFF
	RW_MASK = 0x0
	RWC_MASK = 0xB100
	RWS_MASK = 0x0000
	DESC = "Device Status"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "RID"
	OFFSET = 0x08
	LENGTH = 0x01
	VALUE = 0x1A
	RO_MASK = 0xFF
	RW_MASK = 0x00
	RWC_MASK = 0x00
	RWS_MASK = 0x00
	DESC = "Revision ID"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "CC"
	OFFSET = 0x09
	LENGTH = 0x04
	VALUE = 0x010802
	RO_MASK = 0xFFFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Class Code"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "CLS"
	OFFSET = 0x0C
	LENGTH = 0x01
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x00
	RWC_MASK = 0x00
	RWS_MASK = 0x00
    DESC = "Cache Line Size"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "MLT"
	OFFSET = 0x0D
	LENGTH = 0x01
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x00
	RWC_MASK = 0x00
	RWS_MASK = 0x00
	DESC = "Master Latecy Timer"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "HTYPE"
	OFFSET = 0x0E
	LENGTH = 0x01
	VALUE = 0x00
	RO_MASK = 0xFF
	RW_MASK = 0x00
	RWC_MASK = 0x00
	RWS_MASK = 0x00
	DESC = "Header Type"
</REG>

BIST Reg is defaulted to 0x00 when BIST.BC is 0
<REG>
	CFG_NAME = PCIHEADER
	NAME = "BIST"
	OFFSET = 0x0F
	LENGTH = 0x1
	VALUE = 0x00
	RO_MASK = 0xBF
	RW_MASK = 0x40
	RWC_MASK = 0x00
	RWS_MASK = 0x00
	DESC = "Built in self test"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "MLBAR(BAR0)"
	OFFSET = 0x10
	LENGTH = 0x04
	VALUE = 0x04
	RO_MASK = 0x0
	RW_MASK = 0xFFFF7FFF
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Memory Register Base address lower 32 bits 0xF2060004"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "MUBAR(BAR1)"
	OFFSET = 0x14
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Memory Register Base address upper 32 bits"
</REG>

IDBAR Reg will be read as 0h when CMD.IOSE in PCI space is not set
(Refer: section 2.1.12 and 3.2 of NVM Express 1.0a)
<REG>
	CFG_NAME = PCIHEADER
	NAME = "IDBAR(BAR2)"
	OFFSET = 0x18
	LENGTH = 0x04
	VALUE = 0x01
	RO_MASK = 0x7
	RW_MASK = 0xFFFFFFF8
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Index Data pair registers Base address"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "BAR3"
	OFFSET = 0x1C
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Reserved"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "BAR4"
	OFFSET = 0x20
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Vendor Specific"
</REG>

<REG>
	CFG_NAME = PCIHEADER
	NAME = "BAR5"
	OFFSET = 0x24
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Vendor Specific"
</REG>

 <REG>
	CFG_NAME = PCIHEADER
	NAME = "CCPTR"
	OFFSET = 0x28
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Card Bus CIS Pointer"
</REG>
<REG>
	CFG_NAME = PCIHEADER
	NAME = "SS"
	OFFSET = 0x2C
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Sub System Identfiers"
</REG>

If we remove EROM Register from this list it means "EROM" is not supported and thus is ignored
and is defaulted to 0 as mentioned in the NVME specs
<REG>
	CFG_NAME = PCIHEADER
	NAME = "EROM"
	OFFSET = 0x30
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Expansion Rom"
</REG>
<REG>
	CFG_NAME = PCIHEADER
	NAME = "CAP"
	OFFSET = 0x34
	LENGTH = 0x01
	VALUE = 0x46
	RO_MASK = 0xF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PMCAP Capabilities Pointer"
</REG>
<REG>
	CFG_NAME = PCIHEADER
	NAME = "INTR"
	OFFSET = 0x3C
	LENGTH = 0x02
	VALUE = 0x0100
	RO_MASK = 0xFF00
	RW_MASK = 0x00FF
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Interrupt Information"
</REG>
<REG>
	CFG_NAME = PCIHEADER
	NAME = "MGNT"
	OFFSET = 0x3E
	LENGTH = 0x01
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Minimum Grant"
</REG>
<REG>
	CFG_NAME = PCIHEADER
	NAME = "MLAT"
	OFFSET = 0x3F
	LENGTH = 0x01
	VALUE = 0x0
	RO_MASK = 0xFF
	RW_MASK = 0x00
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Maximum Latency"
</REG>

<REG>
	CFG_NAME = PMCAP
	NAME = "PID"
	OFFSET = 0x00
	LENGTH = 0x02
	VALUE = 0x6601
	RO_MASK = 0xFFFF
	RW_MASK = 0x0000
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "PCI Power Management Capability ID"
</REG>

<REG>
	CFG_NAME = PMCAP
	NAME = "PC"
	OFFSET = 0x02
	LENGTH = 0x02
	VALUE = 0x0
	RO_MASK = 0xFFFF
	RW_MASK = 0x0000
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "PCI Power Management Capabilities"
</REG>
<REG>
	CFG_NAME = PMCAP
	NAME = "PMCS"
	OFFSET = 0x04
	LENGTH = 0x02
	VALUE = 0x8
	RO_MASK = 0xFFFC
	RW_MASK = 0x3
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "PCI Power Management Control and Status"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MID"
	OFFSET = 0x00
	LENGTH = 0x02
	VALUE = 0x9005
	RO_MASK = 0xFFFF
	RW_MASK = 0x0000
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Message Signaled Interrupt Identifiers"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MC"
	OFFSET = 0x02
	LENGTH = 0x02
	VALUE = 0x80
	RO_MASK = 0xFF8E
	RW_MASK = 0x0071
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Message Signaled Interrupt Message Control"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MA"
	OFFSET = 0x04
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x3
	RW_MASK = 0xFFFFFFFC
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Message Signaled Interrupt Message Address"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MUA"
	OFFSET = 0x08
	LENGTH = 0x04
	VALUE = 0x00
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Message Signaled Interrupt Upper Address"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MD"
	OFFSET = 0x0C
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Message Signaled Interrupt Message Data"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MMASK"
	OFFSET = 0x10
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "Message Signaled Interrupt Mask Bits"
</REG>
<REG>
	CFG_NAME = MSICAP
	NAME = "MPEND"
	OFFSET = 0x14
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0x0
	RW_MASK = 0xFFFFFFFF
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "Message Signaled Interrupt Pending Bits"
</REG>

<REG>
	CFG_NAME = PXCAP
	NAME = "PXID"
	OFFSET = 0x00
	LENGTH = 0x02
	VALUE = 0x0010
	RO_MASK = 0xFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Capability ID"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXCAP"
	OFFSET = 0x02
	LENGTH = 0x02
	VALUE = 0x2
	RO_MASK = 0xFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Capabilities"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXDCAP"
	OFFSET = 0x04
	LENGTH = 0x04
	VALUE = 0x10008000
	RO_MASK = 0xFFFFFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Device Capabilities"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXDC"
	OFFSET = 0x08
	LENGTH = 0x02
	VALUE = 0x0
	RO_MASK = 0x7FE0
	RW_MASK = 0xFFFF
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "PCI Express Device Control"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXDS"
	OFFSET = 0x0A
	LENGTH = 0x02
	VALUE = 0x0
	RO_MASK = 0xFFF0
	RW_MASK = 0x0
	RWC_MASK = 0xF
	RWS_MASK = 0x0
	DESC = "PCI Express Device Status"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXLCAP"
	OFFSET = 0x0C
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0xFFFFFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Link Capabilities"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXLC"
	OFFSET = 0x10
	LENGTH = 0x02
	VALUE = 0x0
	RO_MASK = 0xFE34
	RW_MASK = 0x3CB
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Link Control"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXLS"
	OFFSET = 0x12
	LENGTH = 0x02
	VALUE = 0x0001
	RO_MASK = 0xFFFF
	RW_MASK = 0x0
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Link Status"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXDCAP2"
	OFFSET = 0x24
	LENGTH = 0x04
	VALUE = 0x10
	RO_MASK = 0xFFFFFFFF
	RW_MASK = 0x0000
	RWC_MASK = 0x0000
	RWS_MASK = 0x0000
	DESC = "PCI Express Device Capabilities 2"
</REG>
<REG>
	CFG_NAME = PXCAP
	NAME = "PXDC2"
	OFFSET = 0x28
	LENGTH = 0x04
	VALUE = 0x0
	RO_MASK = 0xFFFF9BEF
	RW_MASK = 0x6410
	RWC_MASK = 0x0
	RWS_MASK = 0x0
	DESC = "PCI Express Device Control 2"
</REG>