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Returning the signal name map when generating Verilog code #1057

Answered by whitequark
xThaid asked this question in Q&A

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Backwards compatibility (the interface of verilog.convert originally did not include any provision for mapping signal names). For the time being, use verilog.convert_fragment function, which requires the inconvenience of you having to run Fragment.get yourself first.

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Converted from issue

This discussion was converted from issue #1056 on January 29, 2024 21:31.