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MIPS processor designed in Verilog.

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Name		Name	Last commit message	Last commit date
Latest commit History 14 Commits
MIPS [Multi-Cycle]		MIPS [Multi-Cycle]
MIPS [Single-Cycle]		MIPS [Single-Cycle]
LICENSE		LICENSE
README.md		README.md

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MIPS Processor

An implementation of a MIPS CPU written in Verilog.

MIPS architecture is described in this link.

Ali Ghanbari & Mohammad Mashreghi

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MIPS processor designed in Verilog.

c mips mips-assembly verilog mips-architecture single-cycle multi-cycle single-cycle-processor multi-cycle-processor

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Verilog 98.2%
C 1.8%