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DESIGN
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*******************************************************************************
***
*** WARNING: This file is largely out of date.
***
*******************************************************************************
* 16-bit address
* 16-bit data
* 16-bit word
* Memory-mapped registers
* MIPS-like structure
* Dual-ported 8-reg file
* Instruction: op operand
==Registers==
===Directly Accessible Registers===
* A: 16 bits. The accumulator, where everything happens.
* L: 1 bit. The link register. Carry out, Rotate/shift out and overflow
register in one. Same as on the PDP-8.
* I: 1 bit. The interrupt register. Set to allow IRQs, clear to
ignore.
===Indirectly Accessible Registers===
* PC: 16 bits. The program counter.
* PR: 6 bits. The page register. Very unlike the PDP-8. Holds the upper 6 bits
of addresses for LOAD and STORE operations. May not be read. It's set:
** Using the OP1 instruction with bit IR2 set: the PR gets the value from the
6 most significant bits of the PC. (current page, CPG).
** Using the OP1 instruction with bit IR3 set: the PR gets the value from the
6 most significant bits of the Accumulator. (set page, SPG).
** The PR is reset to the 6 most significant bits of the PC whenever the PC
crosses a page boundary (10 lower bits go from ffff -> 0000).
** The PR is reset to the 6 most significant bits of the PC when the PC
changes as a result of a JMP, JSR or TRAP operation (whenever a value is
latched to the PC)
===Internal Registers and Buffers, not Accessible===
* IR: 16 bits. Instruction register. Buffer for instructions read from
memory. Used by the control unit for instruction decoding. The IR is directly
accessible via the program, of course.
* DR: 16 bits. Used to fetch data from memory and for indirection. Also used as
the ALU B port (right hand operand).
* MAR: 16 bits. Memory address register. Stores addresses for the address
bus. 16 bits address 16-bit wide memory for 64 kWords (128 kBytes). By
convention, only the lower 10 bits should be used for memory-mapped I/O-space
devices.
* B: 16 bits. The ALU result buffer. Latched back to the Accumulator when the
ALU's result settles (usually one clock cycle later).
==Instruction format==
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
| OPCODE | I | R | OPERAND/ADDRESS |
+---------------+---+---+---------------------------------------+
==Addressing modes==
===Literal===
The L instruction loads A with the literal value of the address
field. This is the only instruction that uses this addressing mode.
===Immediate Mode===
Register PR (6 bits) holds most significant 6 bits of address.
Address field supplies the least significant 10 bits.
PR can be modified using the OP1 instruction. The JSR instruction
executes an implicit CPG instruction, setting the PR to the current
page (most significant bits of the PC).
===Register Mode===
If 'R' (register) field is set in instruction, The upper 6 bits of the
address are forced to 000000, so the instruction address field
accesses absolute memory locations 0x0000-0x03ff (0-1023).
===Indirect Mode===
If 'I' (indirect) is set, the address is dereferenced.
===Autoincrement Mode===
If 'I' (indirect) is set, and address & 0xff10 == 0x10, (absolute
memory addresses 0x0010-0x001f) then, after access, mem[address] is
incremented a la PDP-8.
==Basic instructions==
INSTRUCTION SEMANTICS
-------------------------------------------------------------------------------
0000 TRAP addr mem[1] <- PC; flags.I = 0; PC <- addr
0001 **RESERVED
0010 LOAD address A <- mem[address]
0011 STORE address mem[address] <- A
0100 IN A <- io[address]
0101 OUT io[address] <- A
0110 JMP addr PC <- addr
0111 JSR addr mem[0] <- PC; PC <- addr
1000 ADD address <C,A> <- <C,A> + mem[address]
1001 AND address A <- A & mem[address]
1010 OR address A <- A | mem[address]
1011 XOR address A <- A ^ mem[address]
1100 OP1
1101 OP2
1110 **RESERVED
1111 LI literal A <- #literal
-------------------------------------------------------------------------------
OP1: 10 bits of special features
9876543210
1--------- CLA A <- 0
-1-------- CLL L <- 0
--1------- NOT A <- NOT A
---1------ INC <L,A> <- <L,A> + 1
----1----- NTL L <- NOT L
-----010-- RBL <L,A> <- <L,A> >> 1
-----001-- RBR <L,A> <- <L,A> << 1
-----110-- RNL <L,A> <- <L,A> >> 4
-----101-- RNR <L,A> <- <L,A> << 4
--------1- **RESERVED
---------1 HALT
OP2: 10 bits of special features
9876543210
-----1---- LPG A <= PR
------1--- SPG PR <= A
-------1-- CPG PR <= PC
-0000----- NOP (no semantics)
-01------- SNA A & 0x8000 == 1 ==> PC := PC + 1 }
-0-1------ SZA A == 0 ==> PC := PC + 1 } ORred together
-0--1----- SSL L == 1 ==> PC := PC + 1 }
-1000----- SKIP PC := PC + 1
-11------- SNN A & 0x80 == 1 ==> PC := PC + 1 }
-1-1------ SNZ A != 0 ==> PC := PC + 1 } ANDed together
-1--1----- SCL L == 0 ==> PC := PC + 1 }
1--------- CLA A <- 0
--------1- CLI INT <= 0
---------1 TLI INT <= !INT
===SKIP MECHANISM===
* bit 15 sets skip flag (0 = clear, 1 = skip)
* bits 14, 13, 12 set the skip flag when the appropriate condition is true.
====SKIP LOGIC PROOF====
A = bit 12
B = bit 13
C = bit 14
D = bit 15
S1 = (from ALU) AND A
S2 = (from ALU) AND B
S3 = (from ALU) AND C
T = S1 or S2 or S3
SKIP = T XOR bit 15
PROOF
D S1 S2 S3 S1·S2·S3 S1+S2+S3 (S1+S2+S3) ^ D COMMENT
-------------------------------------------------------------
0 0 0 0 0 0 0 NEVER SKIP (NOP)
0 0 0 1 0 1 1 SSL (skip if L set)
0 0 1 0 0 1 1 SZA (skip if A == 0)
0 0 1 1 0 1 1
0 1 0 0 0 1 1 SNA (skip if A < 0)
0 1 0 1 0 1 1
0 1 1 0 0 1 1 **1
0 1 1 1 1 1 1
1 0 0 0 0 0 1 ALWAYS SKIP (SKIP)
1 0 0 1 0 1 0 DON'T SKIP IF L set <==> SNN skip if L clear
1 0 1 0 0 1 0 DON'T SKIP IF A == 0 <==> SKIP IF A non-zero
1 0 1 1 0 1 0
1 1 0 0 0 1 0 DON'T SKIP IF A < 0 <==> SKIP IF A >= 0
1 1 0 1 0 1 0
1 1 1 0 0 1 0 **2
1 1 1 1 0 1 0
**1 = SKIP if (A == 0) OR (A < 0)
== SKIP IF A <= 0
**2 = SKIP if NOT ((A == 0) OR (A < 0))
DeMorgan: SKIP IF (NOT (A == 0) AND NOT (A < 0))
== SKIP IF ((A != 0) AND (A >= 0))
== SKIP IF A > 0
==ARCHITECTURE==
===Data Paths===
MAR <- PC
IR <- RAM
MAR <- <PR,A>
DR <- MEM[MAR]
A <- IR (for LI instruction)
A <- PC
A <- PR
BLOCK DIAGRAM
Data bus
<---------------------------------------------------------------------------->
| |
| | | Data bus
v v ----|
+-----+ +-----+ | Latch --+ +-- AEN
| A | | B | | | | | Address bus[0:15]
+-----+ +-----+ ------| +-v-----+ |
| | |-------->| MAR |-------->|
___V__ __V___ | +-------+ |
\ \ / / | |
\ \/ / MR --+ +-- MW |
\ / | | |
\ / | +--v-v---+ |
\______/ ARL -+ |<------->| RAM | |
| | | +--------+
| +---v--------+ |
+-------| Y Register |--->|
+------------+ |
| +---------------+
+--------------+ |<------->| Register file |
| |----+ | | |
| Control Unit | IR |<--------->| - -->| Reg window |
| |----+ | +---------------+
+--------------+ | 8 regs * 18 bits * 32
|
+----------------+ |
| Constant Store |---------->|
+----------------+ |
==MICROCODE==
Microcoding makes the design of a 74xxx CPU much easier compared to
the complexities of a more traditional state machine. It also makes it
easier to debug and improve.
Microcode fields needed (some can be decoded straight from the IR):
Name Bits Description/Semantics
------------------------------------------------------------------------------
pc_step 1 Increase PC
go_execute 1 IR loaded; go to execute cycle.
go_fetch 1 uPC <- 0
mem_read 1 External signal
mem_write 1 External signal
io 1 External signal
alu_op 2 ** 00:ADD, 01:AND, 10:OR, 11:XOR (driven by IR12-13)
==DATA PATHS==
Generated by:
./emu.py a.obj |grep LATCH | sort | uniq -c | sort nr
771 *** LATCH MAR <- <PR,IR>
551 *** LATCH MAR <- PC
551 *** LATCH IR <- [DATA BUS]
387 *** LATCH DR <- [DATA BUS]
138 *** LATCH A <- [DATA BUS]
56 *** LATCH PR_UPDATE (PR <- PC(15:10)
56 *** LATCH PC <- MAR
56 *** LATCH A <- IR[9:0]
52 *** LATCH A <- ALU_Y
27 *** LATCH [DATA BUS] <- A
1 *** LATCH MAR <- DR
==ALU USING 74x181==
ALU OP M S
++ -- -+ +-
---------------------------
00 11 10 01 ADD 0 1010
01 10 11 00 AND 1 1110
10 01 00 11 OR 1 1010
11 00 01 10 XOR 1 1001
Simplfication:
M = OP0 + OP1
S3 = 1
S2 = OP0 * -OP1
S1 = -OP0 + -OP1
S0 = OP0 * OP1
==ALU ON A ROM==
Inputs:
* L: 1 bit.
* A: 16 bits.
* B: 16 bits.
* OP: 2 bits.
Total: 35 bits. Two 18-bit (256k) RAM chips?
Outputs:
* L: 1 bit.
* X: 16 bits.
Split:
* A: x bits
* B: x bits
* C_in: 1 bit
* OP: 2 bits
Split output:
* C_out: 1 bit
* X: x bits
* Z: (X == 0): 1 bit
x = 4 => Input = 4 + 4 + 1 + 2 = 11 bits. (4096).
Output = 6 bits (2 spare)
==ROMs==
* ALU ROM
* Microcode
Use Atmels for ROM emulation and easy upgrade.
Also use an Atmel (microcode-setting one) for reset control and clock generation/control.
==MICROCODE==
===ADDRESSES===
These listed in order of decreasing significance.
* 1 bit: resetting CPU.
* 1 bit: IRQ.
* 1 bit: Fetching.
* 4 bits: the opcode.
* 1 bit: indirection.
* 1 bit: skip set.
* 4 bits: the phase counter. This allows for 16 step microprograms.
Total: 13 bits (8192k).
===CONTROL LINES===
Some of these can be decoded from the IR without the microcode being involved. These are marked ***
* 1 bit: DAB: Drive address bus.
* 1 bit: /R: Read from memory.
* 1 bit: /W: Write to memory.
* 1 bit: /IO: Selects I/O space for reading/writing.
* 1 bit: /MEM: Selects memory for reading/writing.
* 1 bit: /ALUEN (ALU enable)
* 1 bit: PC++, step PC.
* 2 bits: address source: 00 = IR, 10 = constant(Z 0000), 11 = constant(0001)
* 1 bit: Drive Address bus with 0001.
* 4 bits: ALU operation ***
* 1 bit: step <L,A> ***
* 1 bit: halt clock. ***
===MICROCODE===
Fetch instruction:
begin(RST=0, IRQ=X, F=1, OP=X, I=X, SKIP=X):
MAR <- PC, DAB, /MEM, /MR ; Drive address bus with PC
DAB, /MEM, /MR ; Wait state (optional?)
IR <- DBUS, hold ; Latch data, keep driving.
-DAB, -/MEM, -/MR, PC++ ; Stop driving bus. Data is now in IR.
end
Fetch argument (indirection 0):
MAR <- OPERAND, DAB, /MEM, /MR ; Drive address bus with OPERAND
DAB, /MEM, /MR ; Wait state
DR <- DBUS, hold ; Latch data, keep driving.
-DAB, -/MEM, -/MR ; Stop driving bus. Data is now in DR.
Fetch argument (indirection 1):
MAR <- OPERAND, DAB, /MEM, /MR ; Drive address bus with OPERAND
DAB, /MEM, /MR ; Wait state
DR <- DBUS, hold ; Latch data, keep driving.
-DAB, -/MEM, -/MR ; Stop driving. DR = mem[OPERAND].
;
MAR <- DR, DAB, /MEM, /MR ; Drive address bus with DR
DAB, /MEM, /MR ; Wait state
DR <- DBUS, hold ; Latch data, keep driving.
-DAB, -/MEM, -/MR ; Stop driving. DR = mem[mem[OPERAND]].
TRAP instruction:
STORE instruction:
MAR <- DR, DAB, /MEM, /MW ; Drive address bus with DR
DAB, /MEM, /MW ; Wait state
DBUS <- A, hold ; Latch data, keep driving.
-DAB, -/MEM, -/MW ; Stop driving. mem[DR] = A
OUT instruction:
MAR <- DR, DAB, /IO, /MW ; Drive I/O bus with DR
DAB, /MEM, /MW ; Wait state
DBUS <- A, hold ; Latch data, keep driving.
-DAB, -/IO, -/MW ; Stop driving. io[DR] = A
OR instruction:
ALU_X <- A ; Latch ALU X register from A (Y reg is DR)
/ALUEN, hold ; Wait for ALU to settle
A <- ALU_Y, -/ALUEN
DAB, /MEM, /MW ; Wait state
DBUS <- A, hold ; Latch data, keep driving.
-DAB, -/IO, -/MW ; Stop driving. io[DR] = A