This repository contains some verilog modules which are the elementary and fundamental building blocks of a digital circuit. It is best suited for those who are just getting started with Verilog.
Table of Contents
- Clock (customisable tick rate)
- Clock Divider (customisable factor)
- D Latch
- Memory
- 32 Bit LFSR - Pseudo Random Number Generator
- Switch Debouncer
- Pattern Detector
- Two's Complementer
- N Bit Shift Register (universal shift register)
- Typical Example of circuit with datapath and control unit
- N-Bit Barrel Shifter
- FIFO
- Clone this repository to local machine -
git clone https://github.com/aklsh/getting-started-with-verilog.git. - cd into the repository -
cd getting-started-with-verilog/ - Edit the testbench in the file
testbench.vby instantiating the module you want to check, and providing the stimulus in the initial block. - Run with
make.
Feel free to submit pull requests with more such modules. Do take a look at the format of an accepted file before contributing.
