IO

Link Port

Link port lines are defined in the top of core_top:

inout  wire port_tran_si,
output wire port_tran_si_dir,
inout  wire port_tran_so,
output wire port_tran_so_dir,
inout  wire port_tran_sck,
output wire port_tran_sck_dir,
inout  wire port_tran_sd,
output wire port_tran_sd_dir,

Direction lines are such that a 0 (low) indicates input, and 1 (high) indicates output. The default core_top contains comments about X is output/input only, but this is specific to how the GBA lines are configured, NOT how the actual hardware works. All lines can be used bidirectionally.

NOTE: In order to address the link port your core must enable both link_port: true AND cartridge_adapter: 0 in core.json. This means that the cart port is powered at the same time.

Performance

I experimented with starting at the 8kHz clock/switching speed of the GBA link port and doubled it until the signal degraded significantly. I should have hooked up a logic analyzer, but I simply eyeballed the signal quality with my scope. The scope calculated a rough real world frequency.

I observed reasonable signal integrity up to ~6MHz, but after that the switching time and noise became unreasonable, and the output started to look like a sine wave. The above image displays a 1.2MHz signal, and you can see how there's already a large amount of variation in the signal.