From 703039497f4d003e58bbe89c54a070b28b416778 Mon Sep 17 00:00:00 2001 From: FaragElsayed2 Date: Wed, 8 May 2024 11:57:23 +0300 Subject: [PATCH] Fixing some linting issues for run_lvs script Signed-off-by: FaragElsayed2 --- .flake8 | 2 +- ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.flake8 b/.flake8 index e4757ebb..e3b27d50 100644 --- a/.flake8 +++ b/.flake8 @@ -16,7 +16,7 @@ ; ========================================================================== [flake8] -max-line-length = 100 +max-line-length = 120 max-complexity = 18 exclude = diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py index 0e6d870a..45ffa091 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py @@ -29,16 +29,16 @@ --help -h Displays this help message. --layout= Specifies the file path of the input GDS file. --netlist= Specifies the file path of the input netlist file. - --run_dir= Run directory to save all the generated results [default: pwd] + --run_dir= Run directory to save all generated results [default: pwd] --topcell= Specifies the name of the top cell to be used. - --run_mode= Selects the allowed KLayout mode. (flat, deep). [default: flat] + --run_mode= Selects allowed KLayout mode. (flat, deep). [default: flat] --lvs_sub= Sets the substrate name used in your design. --no_net_names Omits net names in the extracted netlist. --spice_comments Includes netlist comments in the extracted netlist. --net_only Generates netlist objects only in the extracted netlist. - --no_simplify Disables simplification for both layout and schematic netlists. - --no_series_res Prevents the simplification of series resistors for both layout and schematic netlists. - --no_parallel_res Prevents the simplification of parallel resistors for both layout and schematic netlists. + --no_simplify Disables simplification for both layout and schematic. + --no_series_res Prevents simplification of series resistors for both layout and schematic. + --no_parallel_res Prevents simplification of parallel resistors for both layout and schematic. --combine_devices Enables device combination for both layout and schematic netlists. --top_lvl_pins Creates pins for top-level circuits in both layout and schematic netlists. --purge Removes unused nets from both layout and schematic netlists. @@ -216,7 +216,7 @@ def generate_klayout_switches(arguments, layout_path, netlist_path): } return switches - + def build_switches_string(sws: dict): """