diff --git a/.flake8 b/.flake8 index 637aa626..e4757ebb 100644 --- a/.flake8 +++ b/.flake8 @@ -1,33 +1,29 @@ ; ========================================================================== -; Copyright 2024 IHP PDK Authors -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; https://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. -; SPDX-License-Identifier: Apache-2.0 +; Copyright 2024 IHP PDK Authors +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; https://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; SPDX-License-Identifier: Apache-2.0 ; ========================================================================== [flake8] max-line-length = 100 max-complexity = 18 -; select = B,C,E,F,W,T4,B9 -; ignore = E203, E266, E501, W503, F403, F401 exclude = # No need to traverse our git directory .git, # There's no value in checking cache directories __pycache__, - # Ignore python init files - __init__.py, # The conf file is mostly autogenerated, ignore it docs/source/conf.py, # The old directory contains Flake8 2.0 @@ -42,4 +38,4 @@ exclude = deprecated, env, *_env, - *.egg-info + *_venv, diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md new file mode 100644 index 00000000..a9d7ea35 --- /dev/null +++ b/.github/ISSUE_TEMPLATE.md @@ -0,0 +1,16 @@ +## Environment + +- Klayout Version: +- OS/Platform: + +## Expected Behavior + + +## Actual Behavior + + +## Steps to Reproduce the Problem + +1. +2. +3. diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 00000000..f90b0dd3 --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,4 @@ +Fixes # + +- [ ] Tests pass +- [ ] Appropriate changes to README are included in PR diff --git a/.github/workflows/linting.yml b/.github/workflows/linting.yml new file mode 100644 index 00000000..ff8a5a54 --- /dev/null +++ b/.github/workflows/linting.yml @@ -0,0 +1,33 @@ +#========================================================================== +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +#========================================================================== + +name: code linting +on: + pull_request: + # push: + workflow_dispatch: + +jobs: + lint_python: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + with: + submodules: 'recursive' + - name: Lint with flake8 + run: | + make lint_python diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml new file mode 100644 index 00000000..c7dc5f89 --- /dev/null +++ b/.github/workflows/lvs_regression.yml @@ -0,0 +1,82 @@ +#========================================================================== +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +#========================================================================== + +name: LVS regression testing + +# Prevent keeping resources busy when a branch/PR is updated +# https://docs.github.com/en/actions/using-jobs/using-concurrency +concurrency: + group: ${{ github.repository }}-${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +on: + # push: + pull_request: + workflow_dispatch: + +jobs: + lvs_switch: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + include: + - { tool: klayout, part: lvs, test: switch } + + name: ${{ matrix.part }} | ${{ matrix.test }} + + steps: + - uses: actions/checkout@v3 + with: + submodules: 'recursive' + - name: Testing ${{ matrix.part }} for ${{ matrix.test }} + run: | + make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }} + + build_lvs-matrix: + runs-on: ubuntu-latest + outputs: + lvs_table: ${{ steps.set-matrix.outputs.lvs_table }} + steps: + - uses: actions/checkout@v3 + - id: set-matrix + run: | + cd ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ + lvs_table=`echo '[' ; find -iname '*_extraction.lvs' | awk -F_ '{print $1}' | awk -F/ '{print $2}' | tr '[:lower:]' '[:upper:]' | tr '\n' ','|sed -e 's/^/\"/'| sed -e 's/,$/\"]/'|sed -e 's/,/\", \"/g'`; + lvs_table=`echo $lvs_table | jq -c .` + echo $lvs_table + echo "lvs_table=$lvs_table" >>$GITHUB_OUTPUT + + lvs_regression: + needs: build_lvs-matrix + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + part: [lvs] + test: ${{ fromJson(needs.build_lvs-matrix.outputs.lvs_table) }} + + name: ${{ matrix.part }} | ${{ matrix.test }} + + steps: + - uses: actions/checkout@v3 + with: + submodules: 'recursive' + - name: Testing ${{ matrix.part }} for ${{ matrix.test }} + run: | + make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }} + diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..6cdef419 --- /dev/null +++ b/Makefile @@ -0,0 +1,69 @@ +#========================================================================== +# Copyright 2024 IHP PDK Authors +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +#========================================================================== + +# The top directory where environment will be created. +TOP_DIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST)))) +VENV_RUN_COMMAND = $(TOP_DIR)/actions_venv/bin/activate + +# Path to regression +KLAYOUT_LVS_TESTS := ihp-sg13g2/libs.tech/klayout/tech/lvs/testing + +# A pip `requirements.txt` file. +# https://pip.pypa.io/en/stable/reference/pip_install/#requirements-file-format +REQUIREMENTS_FILE := requirements.txt + +# ======================= +# ------ ENV SETUP ------ +# ======================= + +$(TOP_DIR)/actions_venv: + @python3 -m venv $(TOP_DIR)/actions_venv + +# Install requirements +env: $(TOP_DIR)/actions_venv + @. $(VENV_RUN_COMMAND); pip install -r $(REQUIREMENTS_FILE) + +# ======================== +# ----- LINTING TEST ----- +# ======================== + +# Lint python code +lint_python: env + @echo "Running python linting for Klayout-tech directory" + @. $(VENV_RUN_COMMAND); flake8 ihp-sg13g2/libs.tech/klayout/tech/ + +#================================= +# ----- test-LVS_regression ------ +#================================= + +.ONESHELL: +test-LVS-main: env + @. $(VENV_RUN_COMMAND); echo "Running Klayout-LVS regression for all devices" + @. $(VENV_RUN_COMMAND); cd $(KLAYOUT_LVS_TESTS) && make test-LVS-main + +.ONESHELL: +test-LVS-% : env + @. $(VENV_RUN_COMMAND); echo "Running Klayout-LVS regression for $* device" + @. $(VENV_RUN_COMMAND); cd $(KLAYOUT_LVS_TESTS) && make test-LVS-$* + +#================================= +# -------- test-LVS-switch ------- +#================================= + +test-LVS-switch: env + @. $(VENV_RUN_COMMAND); echo "Running Klayout-LVS switch test" + @. $(VENV_RUN_COMMAND); cd $(KLAYOUT_LVS_TESTS) && make test-LVS-switch diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md b/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md index 1666b3da..dbe6b012 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md @@ -199,9 +199,12 @@ The SG13G2 also facilitates LVS execution via Klayout menus as depicted below: First, you need to add the LVS menus to your `KLAYOUT_PATH`, you could do that by executing the following command: ```bash -KLAYOUT_PATH=$PWD/../:$PWD/../.. klayout -e +KLAYOUT_PATH=$PDKPATH/libs.tech/klayout:$PDKPATH/libs.tech/klayout/tech/ klayout -e ``` +> **_NOTE:_** In this context, `PDKPATH` refers to the path leading to the IHP-Open-PDK/ihp-sg13g2 directory within the current repository. + + Then, you will get the LVS menus for SG13G2, you could set your desired options as shown below: > **_NOTE:_** You need to select the path of the netlist will be used in the LVS run. If no path is specified, the tool will automatically search for the netlist file in the same directory as the layout file, considering files with the extensions .cdl, .spice, or .cir and has same name of the layout file. diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_connections.lvs index fd829141..a1cc5611 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_connections.lvs @@ -28,7 +28,7 @@ logger.info('Starting LVS BJT CONNECTIONS') # ============= # General -connect(npn_sub, pwell_con) +connect(npn_sub, pwell) # npn13G2 nodes connections connect(npn13G2_te, npn13G2_e_pin) @@ -37,7 +37,7 @@ connect(npn13G2_tb, npn13G2_b_pin) connect(npn13G2_e_pin, cont_drw) connect(npn13G2_c_pin, cont_drw) connect(npn13G2_b_pin, cont_drw) -connect(npn_sub, pwell_con) +connect(npn_sub, pwell) connect(npn13G2_e_pin, emwind_drw) connect(emwind_drw, metal1_con) @@ -48,7 +48,7 @@ connect(npn13G2l_tb, npn13G2l_b_pin) connect(npn13G2l_e_pin, cont_drw) connect(npn13G2l_c_pin, cont_drw) connect(npn13G2l_b_pin, cont_drw) -connect(npn_sub, pwell_con) +connect(npn_sub, pwell) # npn13G2V nodes connections connect(npn13G2v_te, npn13G2v_e_pin) @@ -57,7 +57,7 @@ connect(npn13G2v_tb, npn13G2v_b_pin) connect(npn13G2v_e_pin, cont_drw) connect(npn13G2v_c_pin, cont_drw) connect(npn13G2v_b_pin, cont_drw) -connect(npn_sub, pwell_con) +connect(npn_sub, pwell) # ============= # ---- PNP ---- diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_derivations.lvs index ca700c42..e51fbe6e 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/bjt_derivations.lvs @@ -29,18 +29,21 @@ logger.info('Starting BJT DERIVATIONS') logger.info('Starting NPN-BJT DERIVATIONS') -bjt_exclude = gatpoly_drw.join(salblock_drw).join(polyres_drw) - .join(extblock_drw).join(nsd_drw).join(recog_diode) - .join(recog_esd).join(substrate_drw).join(ind_drw) +bjt_exclude = gatpoly_drw.join(pwell_block).join(nsd_drw) + .join(heatres_drw).join(salblock_drw).join(polyres_drw) + .join(mim_drw).join(extblock_drw).join(res_drw) + .join(pwell_blk_holes).join(recog_diode).join(recog_esd) + .join(ind_drw).join(ind_pin).join(substrate_drw) -npn_exclude = nwell_drw.join(nbulay_drw).join(pwell_block).join(bjt_exclude) +npn_exclude = nwell_drw.join(psd_drw).join(nbulay_drw).join(bjt_exclude) # ---------- General NPN ---------- +npn_mk = trans_drw.and(pwell).and(ptap_holes) npn_c_exc = emwind_drw.join(emwihv_drw).join(activ_mask) .join(nsd_block).join(heattrans_drw).join(npn_exclude) npn_b_exc = emwind_drw.join(emwihv_drw).join(heattrans_drw).join(npn_exclude) - -npn_sub = trans_drw.and(pwell).not(npn_exclude) +npn_sub = npn_mk.not(npn_exclude) +npn_dev = activ_drw.join(activ_mask).and(npn_mk) # ---------- npn13G2 ---------- # npn13G2 exclusion layers @@ -48,15 +51,16 @@ npn13G2_e_exc = activ_drw.join(emwihv_drw).join(npn_exclude) npn13G2_b_exc = npn_b_exc.join(activ_mask) # npn13G2 nodes -npn13G2_e_ = emwind_drw.and(activ_mask).and(heattrans_drw).and(nsd_block).and(trans_drw).not(npn13G2_e_exc) +npn13G2_e_ = emwind_drw.and(activ_mask).and(heattrans_drw).and(nsd_block).and(npn_mk).not(npn13G2_e_exc) +# npn13G2 is a fixed device (0.07um X 0.9um) npn13G2_e_pin = npn13G2_e_.with_bbox_min(0.07.um).with_bbox_max(0.9.um).with_area(0.063.um) -npn13G2_b_pin = nsd_block.and(pwell).and(trans_drw).not(npn13G2_b_exc) -npn13G2_c_pin = activ_drw.and(pwell).and(trans_drw).not_overlapping(npn_c_exc) +npn13G2_b_pin = nsd_block.and(npn_mk).not(npn13G2_b_exc) +npn13G2_c_pin = activ_drw.and(npn_mk).not_overlapping(npn_c_exc) -npn13G2_dev = activ_drw.join(activ_mask).join(nsd_block).and(trans_drw).extents.covering(npn13G2_e_pin).covering(npn13G2_b_pin).covering(npn13G2_c_pin) -npn13G2_c = npn13G2_dev.sized(-1.nm).and(trans_drw) +npn13G2_dev = npn_dev.join(nsd_block).extents.covering(npn13G2_e_pin).covering(npn13G2_b_pin).covering(npn13G2_c_pin) +npn13G2_c = npn13G2_dev.sized(-1.nm) npn13G2_tc = npn13G2_dev.not(npn13G2_c).interacting(npn13G2_c_pin) -npn13G2_b = npn13G2_dev.not(npn13G2_c_pin).and(trans_drw) +npn13G2_b = npn13G2_dev.not(npn13G2_c_pin) npn13G2_tb = npn13G2_b.not(npn13G2_e_pin).merged npn13G2_e = npn13G2_e_pin npn13G2_te = npn13G2_e @@ -67,15 +71,16 @@ npn13G2l_e_exc = activ_mask.join(nsd_block).join(emwihv_drw).join(npn_exclude) npn13G2l_b_exc = npn_b_exc.join(activ_drw).join(nsd_block) # npn13G2L nodes -npn13G2l_e_ = emwind_drw.and(activ_drw).and(heattrans_drw).and(trans_drw).not(npn13G2l_e_exc) +npn13G2l_e_ = emwind_drw.and(activ_drw).and(heattrans_drw).and(npn_mk).not(npn13G2l_e_exc) +# npn13G2L has fixed width (0.07um), Length could vary from 1:2.5 um npn13G2l_e_pin = npn13G2l_e_.with_bbox_min(0.07.um).with_bbox_max(1.um, 2.5.um).with_area(0.07.um, 0.175.um) -npn13G2l_b_pin = activ_mask.and(trans_drw).and(pwell).not(npn13G2l_b_exc) +npn13G2l_b_pin = activ_mask.and(npn_mk).not(npn13G2l_b_exc) npn13G2l_c_pin = npn13G2_c_pin -npn13G2l_dev = activ_drw.join(activ_mask).covering(npn13G2l_e_pin).covering(npn13G2l_b_pin).covering(npn13G2l_c_pin).and(trans_drw) -npn13G2l_c = npn13G2l_dev.sized(1.nm).and(trans_drw) +npn13G2l_dev = npn_dev.covering(npn13G2l_e_pin).covering(npn13G2l_b_pin).covering(npn13G2l_c_pin) +npn13G2l_c = npn13G2l_dev.sized(1.nm) npn13G2l_tc = npn13G2l_c.not(npn13G2l_dev).interacting(npn13G2l_c_pin) -npn13G2l_b = npn13G2l_dev.not(npn13G2l_c_pin).and(trans_drw) +npn13G2l_b = npn13G2l_dev.not(npn13G2l_c_pin) npn13G2l_tb = npn13G2l_b.not(npn13G2l_e_pin).merged npn13G2l_e = npn13G2l_e_pin npn13G2l_te = npn13G2l_e @@ -85,15 +90,16 @@ npn13G2l_te = npn13G2l_e npn13G2v_e_exc = activ_mask.join(nsd_block).join(emwind_drw).join(npn_exclude) # npn13G2V nodes -npn13G2v_e_ = emwihv_drw.and(activ_drw).and(heattrans_drw).and(trans_drw).not(npn13G2v_e_exc) +npn13G2v_e_ = emwihv_drw.and(activ_drw).and(heattrans_drw).and(npn_mk).not(npn13G2v_e_exc) +# npn13G2L has fixed width (0.12um), Length could vary from 1:5 um npn13G2v_e_pin = npn13G2v_e_.with_bbox_min(0.12.um).with_bbox_max(1.um, 5.um).with_area(0.12.um, 0.6.um) npn13G2v_b_pin = npn13G2l_b_pin npn13G2v_c_pin = npn13G2l_c_pin -npn13G2v_dev = activ_drw.join(activ_mask).covering(npn13G2v_e_pin).covering(npn13G2v_b_pin).covering(npn13G2v_c_pin).and(trans_drw) -npn13G2v_c = npn13G2v_dev.sized(1.nm).and(trans_drw) +npn13G2v_dev = npn_dev.covering(npn13G2v_e_pin).covering(npn13G2v_b_pin).covering(npn13G2v_c_pin) +npn13G2v_c = npn13G2v_dev.sized(1.nm) npn13G2v_tc = npn13G2v_c.not(npn13G2v_dev).interacting(npn13G2v_c_pin) -npn13G2v_b = npn13G2v_dev.not(npn13G2v_c_pin).and(trans_drw) +npn13G2v_b = npn13G2v_dev.not(npn13G2v_c_pin) npn13G2v_tb = npn13G2v_b.not(npn13G2v_e_pin).merged npn13G2v_e = npn13G2v_e_pin npn13G2v_te = npn13G2v_e @@ -107,10 +113,12 @@ logger.info('Starting PNP-BJT DERIVATIONS') pnp_exclude = heattrans_drw.join(trans_drw).join(emwind_drw) .join(emwihv_drw).join(nsd_block).join(bjt_exclude) +pnp_mk = ptap_holes.not(pnp_exclude) + # pnp general nodes DERIVATIONS -pnp_e = pactiv.and(nwell_iso).not(pnp_exclude) -pnp_b = nactiv.and(nwell_iso).not(pnp_exclude) -pnp_c = ptap.not(pnp_exclude) +pnp_e = pactiv.and(pnp_mk).and(nwell_iso) +pnp_b = nactiv.and(pnp_mk).and(nwell_iso) +pnp_c = ptap.interacting(pnp_mk).not(pnp_exclude) # pnp_mpa nodes DERIVATIONS pnp_mpa_e = pnp_e.and(pnp_b.extents).and(pnp_c.extents) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/cap_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/cap_derivations.lvs index cd6ba0e7..f8f2c190 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/cap_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/cap_derivations.lvs @@ -23,9 +23,16 @@ logger.info('Starting CAP DERIVATIONS') +rfmimcap_exc = gatpoly_drw.join(nsd_drw).join(nsd_block) + .join(psd).join(nbulay_drw).join(thickgateox_drw) + .join(heattrans_drw).join(trans_drw).join(emwind_drw) + .join(emwihv_drw).join(heatres_drw).join(salblock_drw) + .join(polyres_drw).join(extblock_drw).join(res_drw) + .join(activ_mask).join(pwell_blk_holes).join(recog_diode) + .join(recog_esd).join(ind_drw).join(ind_pin).join(substrate_drw) + # === MIMCAP === -rfmim_exclude = nbulay_drw.join(recog_drw).join(recog_esd) -mimcap_exclude = rfmim_exclude.join(pwell_block) +mimcap_exclude = rfmimcap_exc.join(pwell_block).join(ptap_holes) mim_top = mim_drw.overlapping(topmetal1_drw).and(metal5_drw) mim_btm = metal5_drw.and(mim_drw).sized(0.6.um) @@ -38,8 +45,8 @@ cmim_btm = mim_btm.covering(cmim_top) cmim_dev = mim_drw.covering(cmim_top).and(cmim_btm) # === rfcmim === -rfmim_area = ptap.extents.and(pwell_block).interacting(mim_drw) -rfmim_top = mim_top.and(rfmim_area).not(rfmim_exclude) +rfmim_area = pwell_block.and(ptap.extents).interacting(mim_drw) +rfmim_top = mim_top.and(rfmim_area).not(rfmimcap_exc) rfmim_btm = mim_btm.and(rfmim_area).covering(rfmim_top) rfmim_dev = mim_drw.covering(rfmim_top).and(rfmim_btm) rfmim_sub = ptap.extents.interacting(rfmim_area) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs index e811d0bf..830bcb12 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs @@ -163,6 +163,17 @@ class EnDiode < RBA::DeviceClassDiode end end +# schottky device class +class CustomSchottky < RBA::DeviceClassBJT3Transistor + def initialize + super + clear_parameters + add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true)) + + self.combiner = SchottckyDeviceCombiner.new + end +end + # Taps device class class CustomTap < RBA::DeviceClassDiode def initialize diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs index 9f2533cc..186f0aec 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/devices_connections.lvs @@ -81,4 +81,4 @@ logger.info('Starting GF180 LVS connectivity setup') # ------- Taps CONNECTIONS ------ #================================ -# %include taps_connections.lvs +# %include tap_connections.lvs diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_connections.lvs index 60f3f72c..1950cecf 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_connections.lvs @@ -25,11 +25,11 @@ logger.info('Starting LVS DIODE CONNECTIONS') # dantenna diode connect(dantenna_n, cont_drw) -connect(dantenna_p, pwell_con) +connect(dantenna_p, pwell) # dantenna diode connect(dpantenna_n, cont_drw) -connect(dpantenna_p, pwell_con) +connect(dpantenna_p, pwell) # dantenna diode connect(schottcky_p_1x1, schottcky_p) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs index 1d7a5b98..a8de7e74 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs @@ -23,31 +23,41 @@ logger.info('Starting DIODE DERIVATIONS') -diode_exclude = gatpoly_drw.join(trans_drw).join(polyres_drw) - .join(extblock_drw).join(nsd_drw).join(recog_esd) - .join(substrate_drw).join(ind_drw) +diode_exclude = gatpoly_drw.join(nsd_drw).join(heattrans_drw) + .join(trans_drw).join(emwind_drw).join(emwihv_drw) + .join(heatres_drw).join(polyres_drw).join(mim_drw) + .join(extblock_drw).join(res_drw).join(activ_mask) + .join(recog_esd).join(ind_drw).join(ind_pin) + .join(substrate_drw) -antenna_d_exc = nwell_drw.join(salblock_drw).join(nbulay_drw) - .join(pwell_block).join(diode_exclude) +antenna_d_exc = nwell_drw.join(pwell_block).join(nbulay_drw).join(salblock_drw) + .join(nsd_block).join(pwell_blk_holes).join(diode_exclude) + +antenna_d_mk = recog_diode.not(antenna_d_exc) # dantenna diode -dantenna_exc = psd_drw.join(nsd_block).join(antenna_d_exc) -dantenna_n = activ_drw.and(recog_diode).not(dantenna_exc) -dantenna_p = pwell_con.and(recog_diode).not(dantenna_exc) +dantenna_n = activ_drw.and(antenna_d_mk).not(psd_drw) +dantenna_p = pwell.and(antenna_d_mk).covering(dantenna_n) # dpantenna diode -dpantenna_n = activ_drw.and(psd_drw).and(recog_diode).not(antenna_d_exc) -dpantenna_p = pwell_con.and(recog_diode).and(psd_drw) +dpantenna_n = pactiv.and(antenna_d_mk) +dpantenna_p = pwell.and(antenna_d_mk).covering(dpantenna_n) # schottky_nbl1 diode -schottcky_p_ = activ_drw.and(cont_drw).and(metal1_drw).and(thickgateox_drw) - .and(recog_diode).and(nsd_block).and(salblock_drw) - .and(nbulay_drw).not(nwell_drw).not(diode_exclude) +schottky_mk = recog_diode.and(thickgateox_drw).not(diode_exclude) + .and(pwell_block).and(ptap_holes).and(nbulay_drw) + .and(salblock_drw).and(nsd_block).and(nwell_holes) + .not(psd_drw).not(pwell).not(diode_exclude) + +schottcky_p_ = cont_drw.and(activ_drw).and(metal1_drw) + .and(schottky_mk).not(nwell_drw) + +# schottky_nbl1 is a fixed device (0.3um X 1.0 um) schottcky_p = schottcky_p_.with_bbox_min(0.3.um).with_bbox_max(1.0.um) # Using box with area 1x1 to be used as a reference to (m) schottcky_p_1x1 = schottcky_p.middle(as_boxes).sized(0.499.um) -schottcky_n = activ_drw.and(nwell_iso).and(recog_diode) - .not(nsd_block).not(salblock_drw).not(psd_drw) - .not(diode_exclude) +schottcky_n = activ_drw.and(nwell_iso).interacting(schottky_mk) + .not(nsd_block).not(salblock_drw).not(diode_exclude) +# define port for schottcky schottcky_n_port = cont_drw.and(schottcky_n).not_interacting(schottcky_p) schottcky_sub = ptap.extents.covering(schottcky_p).covering(schottcky_n) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs index 41f49b76..e8a7ec0f 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/esd_derivations.lvs @@ -23,7 +23,6 @@ logger.info('Starting ESD DERIVATIONS') - # General esd_exclude = trans_drw.join(polyres_drw).join(extblock_drw) .join(nsd_drw).join(recog_diode).join(recog_diode) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs index 7fd467d1..57cc7c57 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs @@ -24,8 +24,8 @@ logger.info('Starting GF180 LVS connectivity setup (Inter-layer)') # Inter-layer -connect(pwell_con, ptap) -connect(nwell_con, ntap) +connect(pwell, ptap) +connect(nwell_drw, ntap) connect(ntap, cont_drw) connect(ptap, cont_drw) connect(poly_con, cont_drw) @@ -59,4 +59,4 @@ connect(topmetal2_con, topmetal2_label) logger.info('Starting SG13G2 LVS connectivity setup (Global)') # Global -connect_global(pwell_con, substrate_name) +connect_global(pwell, substrate_name) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs index 216074e2..bab24406 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs @@ -37,7 +37,7 @@ pwell = pwell_drw.join(CHIP.not(nwell_drw.join(pwell_block))) # psd, nsd active & res psd = psd_drw nsd_res = nsd_drw.and(psd).interacting(polyres_drw) -# nsd_all = CHIP.not(psd.join(nsd_block)) +nsd_all = CHIP.not(psd.join(nsd_block)).join(nsd_res) # n & p activ nactiv = activ_drw.not(psd.join(nsd_block)) @@ -45,8 +45,6 @@ pactiv = activ_drw.and(psd) # res/cap exclusion res_mk = polyres_drw.join(res_drw) -nwell_con = nwell_drw.not(res_mk) -pwell_con = pwell.not(res_mk) poly_con = gatpoly_drw.not(res_mk) metal1_con = metal1_drw.not(metal1_res) topmetal1_con = topmetal1_drw.not(ind_drw) @@ -62,9 +60,15 @@ ngate_hv_base = ngate.and(thickgateox_drw) pgate_hv_base = pgate.and(thickgateox_drw) # S/D FETs -nsd_fet = nactiv.outside(nwell_n_iso).interacting(ngate).not(ngate).not(res_mk) -psd_fet = pactiv.and(nwell_n_iso).interacting(pgate).not(pgate).not(res_mk) +nsd_fet = nactiv.not(nwell_drw).interacting(ngate).not(ngate).not_interacting(res_mk) +psd_fet = pactiv.and(nwell_drw).interacting(pgate).not(pgate).not_interacting(res_mk) # n & p taps (short connections) ntap = nactiv.and(nwell_n_iso).not(res_mk).not(recog_diode).not(gatpoly_drw) ptap = pactiv.and(pwell).not(substrate_drw).not(res_mk).not(recog_diode).not(gatpoly_drw) + +# Derived - Layers (Special) +nwell_holes = nwell_drw.holes +ptap_holes = ptap.holes +ntap_holes = ntap.holes +pwell_blk_holes = pwell_block.holes diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs index 4e6a266a..fbf0b2eb 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs @@ -28,7 +28,7 @@ connect(ind2_ports, ind_pin) connect(ind_pin, ind_text) connect(ind_pin, topmetal2_con) connect(ind2_sub, pwell_block) -connect(pwell_block, pwell_con) +connect(pwell_block, pwell) # ind3 connect(ind3_ports, ind_pin) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_derivations.lvs index 929933a1..ff49046a 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_derivations.lvs @@ -23,9 +23,12 @@ logger.info('Starting MOSFET DERIVATIONS') -mos_exclude = heatres_drw.join(salblock_drw).join(trans_drw) - .join(polyres_drw).join(recog_drw).join(extblock_drw) - .join(nsd_drw).join(recog_diode).join(recog_esd).join(ind_drw) +mos_exclude = pwell_block.join(nsd_drw).join(trans_drw) + .join(emwind_drw).join(emwihv_drw).join(heatres_drw) + .join(salblock_drw).join(polyres_drw).join(mim_drw) + .join(extblock_drw).join(res_drw).join(activ_mask) + .join(pwell_blk_holes).join(recog_diode).join(recog_esd) + .join(ind_drw).join(ind_pin).join(ind_drw).join(substrate_drw) # ============== # ---- NMOS ---- @@ -33,13 +36,13 @@ mos_exclude = heatres_drw.join(salblock_drw).join(trans_drw) logger.info('Starting NMOS DERIVATIONS') -nmos_exclude = nwell_n_iso.join(pwell_block).join(mos_exclude) +nmos_exclude = nwell_drw.join(psd).join(mos_exclude) # nmos - LV -ngate_lv = ngate_lv_base.interacting(heattrans_drw).not(nmos_exclude) +ngate_lv = ngate_lv_base.and(heattrans_drw).not(nmos_exclude) # nmos - HV -ngate_hv = ngate_hv_base.interacting(heattrans_drw).not(nmos_exclude) +ngate_hv = ngate_hv_base.and(heattrans_drw).not(nmos_exclude) # ============== # ---- PMOS ---- @@ -47,10 +50,10 @@ ngate_hv = ngate_hv_base.interacting(heattrans_drw).not(nmos_exclude) logger.info('Starting PMOS DERIVATIONS') -pmos_exclude = nbulay_drw.join(mos_exclude) +pmos_exclude = pwell.join(nsd_all).join(nwell_holes).join(mos_exclude) # pmos - LV -pgate_lv = pgate_lv_base.interacting(heattrans_drw).not(pmos_exclude) +pgate_lv = pgate_lv_base.and(heattrans_drw).not(pmos_exclude) # pmos - HV -pgate_hv = pgate_hv_base.interacting(heattrans_drw).not(pmos_exclude) +pgate_hv = pgate_hv_base.and(heattrans_drw).not(pmos_exclude) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_extraction.lvs index 581f27fe..a6275d10 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_extraction.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/mos_extraction.lvs @@ -38,7 +38,7 @@ extract_devices(mos4('sg13_lv_nmos'), 'tS' => nsd_fet, 'tD' => nsd_fet, 'tG' => poly_con, - 'W' => pwell_con }) + 'W' => pwell }) # nmos - HV logger.info('Extraction of NMOS-HV transistor') @@ -48,7 +48,7 @@ extract_devices(mos4('sg13_hv_nmos'), 'tS' => nsd_fet, 'tD' => nsd_fet, 'tG' => poly_con, - 'W' => pwell_con }) + 'W' => pwell }) # ============== # ---- PMOS ---- @@ -64,7 +64,7 @@ extract_devices(mos4('sg13_lv_pmos'), 'tS' => psd_fet, 'tD' => psd_fet, 'tG' => poly_con, - 'W' => nwell_con }) + 'W' => nwell_drw }) # pmos - HV logger.info('Extraction of PMOS-HV transistor') @@ -74,4 +74,4 @@ extract_devices(mos4('sg13_hv_pmos'), 'tS' => psd_fet, 'tD' => psd_fet, 'tG' => poly_con, - 'W' => nwell_con }) + 'W' => nwell_drw }) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_derivations.lvs index 1ec8316d..a6f18e7f 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_derivations.lvs @@ -23,28 +23,32 @@ logger.info('Starting RESISTOR DERIVATIONS') -polyres_exclude = activ_drw.join(nwell_drw).join(thickgateox_drw) - .join(heattrans_drw).join(trans_drw).join(nbulay_drw) - .join(nsd_block).join(recog_diode).join(recog_esd).join(ind_drw) +polyres_exclude = activ_drw.join(nwell_drw).join(pwell_block) + .join(nsd_block).join(nbulay_drw).join(thickgateox_drw) + .join(heattrans_drw).join(trans_drw).join(emwind_drw) + .join(emwihv_drw).join(mim_drw).join(activ_mask) + .join(pwell_blk_holes).join(recog_diode).join(recog_esd) + .join(ind_drw).join(ind_pin).join(substrate_drw) # ============== # ---- POLY ---- # ============== ## polyres -polyres = polyres_drw.and(heatres_drw).and(extblock_drw).interacting(gatpoly_drw).not(polyres_exclude) +polyres_mk = polyres_drw.and(heatres_drw).and(extblock_drw) + .and(pwell).interacting(gatpoly_drw).not(polyres_exclude) ## rhigh -rhigh_res = polyres.and(psd_drw).and(salblock_drw).and(nsd_drw) +rhigh_res = polyres_mk.and(psd_drw).and(nsd_drw).and(salblock_drw) rhigh_ports = gatpoly_drw.interacting(rhigh_res).not(rhigh_res) ## rppd -rppd_res = polyres.and(psd_drw).and(salblock_drw).not(nsd_drw) +rppd_res = polyres_mk.and(psd_drw).and(salblock_drw).not(nsd_all) rppd_ports = gatpoly_drw.interacting(rppd_res).not(rppd_res) ## rsil rsil_exc = psd_drw.join(salblock_drw).join(nsd_drw).join(nsd_block) -rsil_res = polyres.and(res_drw).not(rsil_exc) +rsil_res = polyres_mk.and(res_drw).and(nsd_all).not(rsil_exc) rsil_ports = gatpoly_drw.interacting(rsil_res).not(rsil_res) # =============== diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_extraction.lvs index c7276e44..d2760f92 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_extraction.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/res_extraction.lvs @@ -34,7 +34,7 @@ extract_devices(GeneralNTerminalExtractor.new('res_rsil', 2), { 'ports' => rsil_ports, 'meas_mk' => polyres_drw, 'dev_mk' => polyres_drw.interacting(rsil_res), - 'sub_mk' => pwell_con + 'sub_mk' => pwell }) # rppd logger.info('Extracting rppd resistor') @@ -43,7 +43,7 @@ extract_devices(GeneralNTerminalExtractor.new('res_rppd', 2), { 'ports' => rppd_ports, 'meas_mk' => polyres_drw, 'dev_mk' => polyres_drw.interacting(rppd_res), - 'sub_mk' => pwell_con + 'sub_mk' => pwell }) # rhigh @@ -53,7 +53,7 @@ extract_devices(GeneralNTerminalExtractor.new('res_rhigh', 2), { 'ports' => rhigh_ports, 'meas_mk' => polyres_drw, 'dev_mk' => polyres_drw.interacting(rhigh_res), - 'sub_mk' => pwell_con + 'sub_mk' => pwell }) # =============== diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_derivations.lvs index 722933b0..28e93b28 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_derivations.lvs @@ -21,24 +21,19 @@ logger.info('Starting RF-MOSFET DERIVATIONS') -rfmos_exclude = heattrans_drw.join(mos_exclude) -rfnmos_gr = ptap.holes -rfpmos_gr = ntap.holes -ntap_ext = ntap.extents - # =============== # --- RF-NMOS --- # =============== logger.info('Starting RF-NMOS DERIVATIONS') -rfnmos_exclude = nwell_n_iso.join(pwell_block).join(rfmos_exclude) +rfnmos_exclude = nmos_exclude.join(heattrans_drw) # rfnmos - LV -rfngate_lv = ngate_lv_base.and(rfnmos_gr).not(rfnmos_exclude) +rfngate_lv = ngate_lv_base.and(ptap_holes).not(rfnmos_exclude) # rfnmos - HV -rfngate_hv = ngate_hv_base.and(rfnmos_gr).not(rfnmos_exclude) +rfngate_hv = ngate_hv_base.and(ptap_holes).not(rfnmos_exclude) # =============== # --- RF-PMOS --- @@ -46,11 +41,10 @@ rfngate_hv = ngate_hv_base.and(rfnmos_gr).not(rfnmos_exclude) logger.info('Starting RF-PMOS DERIVATIONS') -rfpmos_exclude = nbulay_drw.join(rfmos_exclude) +rfpmos_exclude = pmos_exclude.join(heattrans_drw) # rfpmos - LV -rfpgate_lv = pgate_lv_base.and(rfpmos_gr).not(rfpmos_exclude) -# rfpmos_sub = ptap.and(ntap_ext.covering(rfpgate_lv).and(nwell_drw)) +rfpgate_lv = pgate_lv_base.and(ntap_holes).not(rfpmos_exclude) # rfpmos - HV -rfpgate_hv = pgate_hv_base.and(rfpmos_gr).not(rfpmos_exclude) +rfpgate_hv = pgate_hv_base.and(ntap_holes).not(rfpmos_exclude) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_extraction.lvs index 5109ec44..f528a823 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_extraction.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/rfmos_extraction.lvs @@ -32,7 +32,7 @@ logger.info('Extraction of RF-NMOS-LV transistor') extract_devices(mos4('rfnmos'), { 'SD' => nsd_fet, 'G' => rfngate_lv, - 'W' => pwell_con, + 'W' => pwell, 'tS' => nsd_fet, 'tD' => nsd_fet, 'tG' => poly_con }) @@ -42,7 +42,7 @@ logger.info('Extraction of RF-NMOS-HV transistor') extract_devices(mos4('rfnmoshv'), { 'SD' => nsd_fet, 'G' => rfngate_hv, - 'W' => pwell_con, + 'W' => pwell, 'tS' => nsd_fet, 'tD' => nsd_fet, 'tG' => poly_con }) @@ -59,7 +59,7 @@ extract_devices(mos4('rfpmos'), 'tS' => psd_fet, 'tD' => psd_fet, 'tG' => poly_con, - 'W' => nwell_con }) + 'W' => nwell_drw }) # rfpmos - HV logger.info('Extraction of RF-PMOS-HV transistor') @@ -69,4 +69,4 @@ extract_devices(mos4('rfpmoshv'), 'tS' => psd_fet, 'tD' => psd_fet, 'tG' => poly_con, - 'W' => nwell_con }) + 'W' => nwell_drw }) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_connections.lvs similarity index 94% rename from ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_connections.lvs rename to ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_connections.lvs index 6926260a..4d1c5139 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_connections.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_connections.lvs @@ -25,8 +25,8 @@ logger.info('Starting LVS Taps CONNECTIONS') # ntap1 connect(ntap1_n, cont_drw) -connect(ntap1_p, nwell_con) +connect(ntap1_p, nwell_drw) # ptap1 connect(ptap1_n, cont_drw) -connect(ptap1_p, pwell_con) +connect(ptap1_p, pwell) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_derivations.lvs similarity index 77% rename from ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_derivations.lvs rename to ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_derivations.lvs index 8d8bab53..0fcb0255 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_derivations.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_derivations.lvs @@ -23,14 +23,15 @@ logger.info('Starting Taps DERIVATIONS') -taps_exclude = gatpoly_drw.join(heattrans_drw).join(trans_drw) - .join(heatres_drw).join(polyres_drw).join(salblock_drw) - .join(extblock_drw).join(nsd_drw).join(res_drw) +taps_exclude = gatpoly_drw.join(nsd_drw).join(heattrans_drw) + .join(trans_drw).join(emwind_drw).join(emwihv_drw) + .join(heatres_drw).join(salblock_drw).join(polyres_drw) + .join(mim_drw).join(extblock_drw).join(res_drw) .join(activ_mask).join(recog_diode).join(recog_esd) - .join(ind_drw) + .join(ind_drw).join(ind_pin) # === ntap1 === -ntap1_exc = psd_drw.join(taps_exclude) +ntap1_exc = pwell.join(psd_drw).join(taps_exclude) # ntap1_n = nactiv.and(nwell_iso).not(ntap1_exc) # Modified to catch similar structure in pnpMPA-Base node ntap1_n = nactiv.and(nwell_iso).extents.not_interacting(ntap1_exc) @@ -39,4 +40,4 @@ ntap1_p = nwell_iso.covering(ntap1_n) # === ptap1 === ptap1_exc = nwell_drw.join(nbulay_drw).join(taps_exclude) ptap1_n = pactiv.and(pwell).interacting(substrate_drw).not(ptap1_exc) -ptap1_p = pwell_con.covering(ptap1_n) +ptap1_p = pwell.covering(ptap1_n) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs similarity index 90% rename from ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_extraction.lvs rename to ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs index f2d8d7b1..8e08e659 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/taps_extraction.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/tap_extraction.lvs @@ -26,11 +26,7 @@ logger.info('Starting Taps EXTRACTION') # ntap1 logger.info('Extracting ntap1 device') extract_devices(diode('ntap1', CustomTap), { 'N' => ntap1_n, 'P' => ntap1_p }) -enable_parameter('ntap1', 'A') -enable_parameter('ntap1', 'P') # ptap1 logger.info('Extracting ptap1 device') extract_devices(diode('ptap1', CustomTap), { 'N' => ptap1_n, 'P' => ptap1_p }) -# enable_parameter('ptap1', 'A') -# enable_parameter('ptap1', 'P') diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py index d8358a97..09ca3f66 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py @@ -22,8 +22,8 @@ run_lvs.py (--layout=) (--netlist=) [--thr=] [--run_dir=] [--topcell=] [--run_mode=] [--lvs_sub=] [--no_net_names] [--spice_comments] [--net_only] - [--top_lvl_pins] [--no_simplify] [--combine] [--purge] [--purge_nets] - [--schematic_simplify] [--verbose] + [--top_lvl_pins] [--no_simplify] [--combine] [--purge] [--purge_nets] + [--schematic_simplify] [--verbose] Options: --help -h Print this help message. diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2.lvs index 88537bce..c1e16def 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2.lvs +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2.lvs @@ -268,7 +268,7 @@ logger.info('Starting base layers derivations') # ------ Taps DERIVATIONS ------- #================================ -# %include rule_decks/taps_derivations.lvs +# %include rule_decks/tap_derivations.lvs #================================================ #------------ DEVICES CONNECTIVITY -------------- @@ -334,7 +334,7 @@ logger.info('Starting SG13G2 LVS DEVICES EXTRACTION') # ------- Taps EXTRACTIONS ------ #================================ -# %include rule_decks/taps_extraction.lvs +# %include rule_decks/tap_extraction.lvs #================================================ #------------- COMPARISON OPTIONS --------------- diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile index fc560146..dad87c29 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile @@ -37,7 +37,7 @@ test-LVS-main: test-LVS-MOS test-LVS-RFMOS test-LVS-BJT test-LVS-DIODE test-LVS- .ONESHELL: test-LVS-%: @echo "========== LVS-$* testing ==========" - @ python3 run_regression.py --device_name=$* + @ python3 run_regression.py --device=$* #================================= # -------- test-LVS-switch ------- diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py index 6242f7fe..cab547cb 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py +++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py @@ -260,7 +260,7 @@ def run_test_case( switches = " ".join(get_switches(sw_file, device_name)) else: # Get switches - switches = " -rd lvs_sub=sub!" # default switch + switches = " --lvs_sub=sub!" # default switch # Creating run folder structure and copy testcases in it pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1]) @@ -274,9 +274,8 @@ def run_test_case( # command to run LVS call_str = ( - f"klayout -b -r {lvs_dir}/sg13g2.lvs -rd input={layout_path_run} " - f"-rd schematic={device_name}.cdl -rd report={device_name}.lvsdb " - f"-rd target_netlist={device_name}_extracted.cir {switches} > {pattern_log} 2>&1" + f"python3 {lvs_dir}/run_lvs.py --layout={layout_path_run} " + f"--netlist={netlist_path_run} --run_dir={output_loc} {switches} > {pattern_log} 2>&1" ) # Starting klayout run @@ -542,7 +541,7 @@ def main(lvs_dir, output_path, target_device_group): if target_device_group and (target_device_group not in allowed_devices): logging.error( - "Allowed devices are (MOS, RFMOS, BJT, DIODE, RES, CAP, ESD, TAP, IND) only, please recheck" + "Allowed devices are (MOS, RFMOS, BJT, DIODE, RES, CAP, ESD, TAP, IND) only" ) exit(1) diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/diode_devices/layout/schottky_nbl1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/diode_devices/layout/schottky_nbl1.gds index 638ce544..5ed98942 100644 Binary files a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/diode_devices/layout/schottky_nbl1.gds and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/diode_devices/layout/schottky_nbl1.gds differ diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/mos_devices/layout/sg13_lv_nmos.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/mos_devices/layout/sg13_lv_nmos.gds index 4f109ad7..b009adbf 100644 Binary files a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/mos_devices/layout/sg13_lv_nmos.gds and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/mos_devices/layout/sg13_lv_nmos.gds differ diff --git a/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt index d73e740b..dccddc67 100644 --- a/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt +++ b/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt @@ -16,8 +16,8 @@ IHP SiGe 130nm technology 0.001 - $(appdata_path)/tech - $(appdata_path)/tech + + sg13g2.lyp true diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 00000000..79e12092 --- /dev/null +++ b/requirements.txt @@ -0,0 +1,5 @@ +flake8 +docopt +pandas +klayout +pyyaml \ No newline at end of file