The FullStack IC Designer Development will base on the Caravel SoC backbone. We target two ASIC tapeouts: Google Efabless SKY130 with open source EDA flow (Openlane & Efabless Caravel) and TSMC 0.18um with commercial EDA flow. We also plan to develop a validation system for the chips that come back as verification.
Meeting Slides:
fsic-1st-meeting
fsic-2nd-meeting
fsic-3rd-meeting
全端IC設計工程師開發流程@伴伴學Discoard:
https://discordapp.com/channels/838422912507052062/1077220224820068363