Merge pull request #12 from abs-tudelft/chore/chisel-6-update

Update to comply with Chisel v6 and chiseltest v6 updates.

build.sbt

@@ -1,4 +1,4 @@
-val chiselVersion = "5.1.0"
+val chiselVersion = "6.3.0"
 
 ThisBuild / scalaVersion := "2.13.12"
 
@@ -25,7 +25,7 @@ lazy val library: Project = (project in file("library"))
     commonSettings,
     name                                     := "Tydi-Chisel",
     description                              := "Tydi-Chisel is an implementation of Tydi concepts in the Chisel HDL.",
-    libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % Test
+    libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % Test
   )
 //  .dependsOn(testingTools % "test->test")
 
@@ -34,7 +34,7 @@ lazy val testingTools: Project = (project in file("testing"))
     commonSettings,
     name                                     := "Tydi-Chisel-Test",
     description                              := "This package contains the testing tools for Tydi-Chisel",
-    libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "5.0.2"
+    libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "6.0.0"
   )
   .dependsOn(library % "compile->compile") // Make testingTools project depend on the library project
 

library/src/main/scala/nl/tudelft/tydi_chisel/TydiLib.scala

@@ -5,7 +5,6 @@ import scala.collection.mutable.ListBuffer
 
 import chisel3._
 import chisel3.experimental.{BaseModule, ExtModule}
-import chisel3.internal.firrtl.Width
 import chisel3.util.{log2Ceil, Cat}
 import nl.tudelft.tydi_chisel.ReverseTranspiler._
 import nl.tudelft.tydi_chisel.utils.ComplexityConverter

library/src/main/scala/nl/tudelft/tydi_chisel/examples/pipeline/PipelineExample.scala

@@ -1,7 +1,6 @@
 package nl.tudelft.tydi_chisel.examples.pipeline
 
 import chisel3._
-import chisel3.internal.firrtl.Width
 import chisel3.util.Counter
 import circt.stage.ChiselStage.{emitCHIRRTL, emitSystemVerilog}
 import nl.tudelft.tydi_chisel._

library/src/main/scala/nl/tudelft/tydi_chisel/examples/rgb/Rgb.scala

@@ -1,7 +1,6 @@
 package nl.tudelft.tydi_chisel.examples.rgb
 
 import chisel3._
-import chisel3.internal.firrtl.Width
 import circt.stage.ChiselStage.{emitCHIRRTL, emitSystemVerilog}
 import nl.tudelft.tydi_chisel._
 

library/src/main/scala/nl/tudelft/tydi_chisel/examples/timestamped_message/TimestampedMessage.scala

@@ -1,7 +1,6 @@
 package nl.tudelft.tydi_chisel.examples.timestamped_message
 
 import chisel3._
-import chisel3.internal.firrtl.Width
 import circt.stage.ChiselStage.{emitCHIRRTL, emitSystemVerilog}
 import nl.tudelft.tydi_chisel._
 

library/src/test/scala/gcd/GCDSpec.scala

@@ -23,9 +23,7 @@ class GCDSpec extends AnyFreeSpec with ChiselScalatestTester {
   "Gcd should calculate proper greatest common denominator" in {
     test(new DecoupledGcd(16)) { dut =>
       dut.input.initSource()
-      dut.input.setSourceClock(dut.clock)
       dut.output.initSink()
-      dut.output.setSinkClock(dut.clock)
 
       val testValues = for { x <- 0 to 10; y <- 0 to 10 } yield (x, y)
       val inputSeq   = testValues.map { case (x, y) => (new GcdInputBundle(16)).Lit(_.value1 -> x.U, _.value2 -> y.U) }