This repo contains FPGA implementations of the PDP-6 and PDP-10 (KA10). Most of the verilog is a transcription of the actual schematics. Since the real machines are asynchronous some trickery had to be done to simulate the timing. They use delays that are triggered by pulses and output another pulse after some time. Instead of pulses I use clock enables, and delays are implemented by a counter synchronized to the 50MHz system clock.
The PDP-6 and KA10 both have their respective TTY, PTR and PTP interaces simulated. In addition we have the type 340 display and spacewar consoles.
The next steps will be DECtape (both 551 and TD10) and a disk to actually get some operating systems running.
The supported boards are the DE0-Nano-SoC and DE10-Nano. Both have an ARM HPS on the same chip as the FPGA.
The ARM HPS and FPGA can communicate through various bridges. The lightweight HPS-to-FPGA bridge is used for memory mapped IO. The memory modules that use SDRAM use the FPGA-to-HPS bridge.
The FE program handles peripheral IO and the virtual front panel on the ARM side. It is modeled very much after DDT, which you are expected to be familiar with.
FE sends points generated by the 340 controller over the network
to a 340 simulator crt.
common verilog and qsys tcl files for common components
pdp6 verilog and qsys tcl files for PDP-6 components
ka10 verilog and qsys tcl files for KA10 components
rtl verilog for non-qsys modules
roms rom files
quartus quartus projects
tb test simulations for icarus verilog
host programs to run on the HPS or another machine
fe: DDT-like frontend (HPS)
crt: crt simulation (networked)
statdisp: display PDP-6 status on OLED display (HPS)