From 58715b8e659b1e49164f72c0f14a572704f087ee Mon Sep 17 00:00:00 2001
From: BeshoyMorad <besh0morta@gmail.com>
Date: Sat, 3 Dec 2022 17:25:57 +0200
Subject: [PATCH] FINISH Phase One

---
 .gitignore              |  3 ++-
 Final Phase 1/BWZZ.v    |  3 ++-
 Final Phase 1/instr.txt | 41 ++++++++++-------------------------
 Final Phase 1/wave.do   | 47 +++++++++++++++++++++++++++++++++++++++++
 input.txt               | 37 ++++++--------------------------
 input1.txt              | 32 ++++++++++++++++++++++++++++
 6 files changed, 101 insertions(+), 62 deletions(-)
 create mode 100644 Final Phase 1/wave.do
 create mode 100644 input1.txt

diff --git a/.gitignore b/.gitignore
index 95552d2..0bda987 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,5 @@
 *.mti
 *.mpf
 *.wlf
-*/work
\ No newline at end of file
+*/work
+transcript
\ No newline at end of file
diff --git a/Final Phase 1/BWZZ.v b/Final Phase 1/BWZZ.v
index 585145d..bb67419 100644
--- a/Final Phase 1/BWZZ.v	
+++ b/Final Phase 1/BWZZ.v	
@@ -136,7 +136,7 @@ IdExBuffer ID_EX_Buffer(
 	.oMemWrite(ID_EX_MemWrite),
 	.oMemRead(ID_EX_MemRead),
 	.oDestOrPrivate(ID_EX_DestOrPrivate),
-	.oSPOrALUres(ID_EX_DestOrPrivate),
+	.oSPOrALUres(ID_EX_SPOrALUres),
 	.oimmOrReg(ID_EX_immOrReg),
 	.oupdateStatus(ID_EX_updateStatus),
 	.oRegDestAddress(regDestAddressID_EX),
@@ -176,6 +176,7 @@ SavedFlages savedFlag (
 wire [15:0] ALUResult;
 
 ExecuteStage ALUStage(
+	.ImmOrReg(ID_EX_immOrReg),
 	.ALUControl(ID_EX_AlUControl),
 	.RegSrc(ID_EX_RegSrc),
 	.RegDst(ID_EX_RegDest),
diff --git a/Final Phase 1/instr.txt b/Final Phase 1/instr.txt
index 5e8f317..d768251 100644
--- a/Final Phase 1/instr.txt	
+++ b/Final Phase 1/instr.txt	
@@ -1,30 +1,11 @@
-0011100000010001
-0000000000000100
-0011100000010000
-0000000000000011
-0000100000000000
-0000000000000101
-0011100000010000
-0000000000000001
-0011100000010001
-0000000000000001
-0000001000110000
-1001000000100010
-0001011000010001
-1111111111111100
-0000001000010001
-1001100000100000
-1010111001010011
-0000000000010000
-1000111001010100
-0000000000010000
-0000001000010100
-1010100000101010
-1000111001010011
-0000000000010000
-0011101001010011
-0000000000000001
-0011101010110101
-0000000000000001
-0000001010100000
-0000000000001000
\ No newline at end of file
+1000100000001100
+0000000000000001
+1000100000010100
+0000000000000010
+0000000000000000
+0000000000000000
+0100100010010000
+0001101010101000
+0000000000000000
+0000000000000000
+1001100100110000
diff --git a/Final Phase 1/wave.do b/Final Phase 1/wave.do
new file mode 100644
index 0000000..60df35a
--- /dev/null
+++ b/Final Phase 1/wave.do	
@@ -0,0 +1,47 @@
+restart
+
+add wave sim:/BWZZ_TB/clk
+add wave sim:/BWZZ_TB/reset
+
+add wave -position insertpoint sim:/BWZZ_TB/yarb/PC
+add wave -position insertpoint sim:/BWZZ_TB/yarb/NextPC
+
+add wave sim:/BWZZ_TB/yarb/fetchStage/immediate
+add wave sim:/BWZZ_TB/yarb/fetchStage/finalInstruction
+
+add wave sim:/BWZZ_TB/yarb/IF_ID_Buffer/oInstruction
+add wave sim:/BWZZ_TB/yarb/IF_ID_Buffer/oimm
+
+add wave -position end sim:/BWZZ_TB/yarb/ALUStage/*
+
+add wave sim:/BWZZ_TB/yarb/DataMemory/Data_result
+add wave sim:/BWZZ_TB/yarb/DataMemory/Data
+
+add wave sim:/BWZZ_TB/yarb/MEM_WB_Buffer/oRegWrite
+add wave sim:/BWZZ_TB/yarb/MEM_WB_Buffer/oMemOrReg
+add wave sim:/BWZZ_TB/yarb/MEM_WB_Buffer/oRegDestAddress
+add wave sim:/BWZZ_TB/yarb/MEM_WB_Buffer/oDataRes
+add wave sim:/BWZZ_TB/yarb/MEM_WB_Buffer/oData
+
+add wave sim:/BWZZ_TB/yarb/WriteBackStage/memData
+add wave sim:/BWZZ_TB/yarb/WriteBackStage/aluData
+add wave sim:/BWZZ_TB/yarb/WriteBackStage/outputRes
+
+add wave sim:/BWZZ_TB/yarb/StatusRegisterBank/CCR
+add wave sim:/BWZZ_TB/yarb/StatusRegisterBank/carryFlag
+
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
\ No newline at end of file
diff --git a/input.txt b/input.txt
index b43d32c..c9eacbe 100644
--- a/input.txt
+++ b/input.txt
@@ -1,32 +1,9 @@
-MOV R1,R5 
-SETC 
-CLRC 
+LDM R1,1 
+LDM R2,2 
 NOP 
-NOT R1 
-DEC R1 
-INC R1  
 NOP 
-SETC 
-CLRC 
-NOT R0 
-INC R0 
-DEC R0 
-OUT R0 
-IN R2 
-MOV R7,R2 
-ADD R7,R2 
-SUB R2,R2 
-AND R2,R3 
-OR R2,R3 
-SHL R4,6 
-SHR R4,8 
-PUSH R3 
-POP R3 
-LDM R3,9 
-LDD R7,R4 
-STD R7,R4 
-JZ R4 
-JN R4 
-JC R5 
-JMP R5 
-CALL R5 
\ No newline at end of file
+ADD R1,R2 
+NOT R5 
+NOP 
+NOP 
+STD R2,R6 
\ No newline at end of file
diff --git a/input1.txt b/input1.txt
new file mode 100644
index 0000000..b43d32c
--- /dev/null
+++ b/input1.txt
@@ -0,0 +1,32 @@
+MOV R1,R5 
+SETC 
+CLRC 
+NOP 
+NOT R1 
+DEC R1 
+INC R1  
+NOP 
+SETC 
+CLRC 
+NOT R0 
+INC R0 
+DEC R0 
+OUT R0 
+IN R2 
+MOV R7,R2 
+ADD R7,R2 
+SUB R2,R2 
+AND R2,R3 
+OR R2,R3 
+SHL R4,6 
+SHR R4,8 
+PUSH R3 
+POP R3 
+LDM R3,9 
+LDD R7,R4 
+STD R7,R4 
+JZ R4 
+JN R4 
+JC R5 
+JMP R5 
+CALL R5 
\ No newline at end of file