Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Verilog file list suport #4926

Open
wants to merge 3 commits into
base: main
Choose a base branch
from
Open

Conversation

JasonBrave
Copy link
Contributor

What are the reasons/motivation for this change?

Most large Verilog/SystemVerilog IP use a file list/command '.f' file to hold list of Verilog file need to be compiled, this change make yosys able to directly parse file list.

Explain how this is achieved.

Implement a read_verilog_file_list command, that read in file list, and calls read_verilog on each Verilog file in the file list. Currently the command only handles file path in file list file, in a future PR I will implement support for +define+ and +incdir+ in file list file.

If applicable, please suggest to reviewers how they can test the change.

@JasonBrave JasonBrave requested a review from zachjs as a code owner March 3, 2025 02:12
@udif
Copy link
Contributor

udif commented Mar 3, 2025

Please note that most, if not all tools, accept any command line argument in their file lists, not just filenames or +define/+incdir.
As far as I remember, the slang front end handles this by reading -f files recursively as part of the command line parser.

Copy link
Member

@KrystalDelusion KrystalDelusion left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

If you're adding file list support for the verilog frontend, you should update the read pass in /frontends/verific/verific.cc to call it.

@@ -52,3 +53,4 @@ __pycache__
/venv
/boost
/ffi
/compile_commands.json
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

These should either both be in their alphabetical position, or both at the end (in date-added position)

log("\n");
}

void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You shouldn't be adding methods to the Pass struct, if you need to make a function call it should be a static function defined in the file. If you need shared state then you should use the worker pattern (defining a separate struct, which gets instanced and called from the execute method).

log("\n");
log(" -F file_list_path\n");
log(" File list file contains list of Verilog files to be parsed, any\n");
log(" ' path is treated relative to the file list file'\n");
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why is the second line in single quotes?

break;
}

if (args.size() != argidx) {
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This should be a call to extra_args().

command += " -sv";
}
command = command + ' ' + verilog_file_path;
Pass::call(design, command);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why use the command version of Pass::call and not the args version?

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I would also highly recommend using the -defer argument to read_verilog like read does.


std::string verilog_file_path;
if (relative_to_file_list_path) {
verilog_file_path = file_list_parent_dir.string() + '/' + v_file_name;
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

If you're using <filesystem> you should use the / operator for portability. i.e. verilog_file = file_list_parent_dir / v_file_name. It would also save on the converting it back into a path alter to check the extension, and you only convert to string when you pass it to read_verilog.

@KrystalDelusion
Copy link
Member

KrystalDelusion commented Mar 3, 2025

@udif The verific frontend for Yosys doesn't do this, so I don't think there's any reason that the read_verilog frontend should. It does however allow recursive calls with -f/-F in the file list. Also it calls it a command-file instead of a file list.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants