5-Stage-Pipeline-Processor

We have designed a 5 Stage Pipeline Processor based on the MIPS architecture

We have designed 19 instructions which are mentioned below:

ADD SUB AND OR XOR NOT CMP MOV NOP ADDI ANDI ORI XORI MOVI JC JZ LW SW JUMP

Name		Name	Last commit message	Last commit date
Latest commit History 24 Commits
ALU.v		ALU.v
ALU_control.v		ALU_control.v
Branch.v		Branch.v
Data_Mem.v		Data_Mem.v
Decode.v		Decode.v
Execute.v		Execute.v
Fetch.v		Fetch.v
Forwading_unit.v		Forwading_unit.v
ID_IE.v		ID_IE.v
IE_IM.v		IE_IM.v
IF_ID.v		IF_ID.v
IM_IW.v		IM_IW.v
Processor_5.v		Processor_5.v
README.md		README.md
Write_Back.v		Write_Back.v
control_unit.v		control_unit.v
mux_4x1.v		mux_4x1.v
processor_tb.v		processor_tb.v
reg_bank.v		reg_bank.v

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