(WiP) More restrictive column control overlay generation #1739
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erwei-xilinx
requested review from
stephenneuendorffer,
jgmelber,
fifield,
jackl-xilinx and
AndraBisca
as code owners
…lumn_control_overlay_generation
…lumn_control_overlay_generation
…p which infers row and col from addr
…rt of the control packet overlay
…ted control packet data generation
…trl pkt flows before others and (2) sorting ctrl pkt flows
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The new passes really should be separate from the PR updating the overlay pass. |
Ok let me break this PR up into multiple PRs. Will change the PR to draft. |
erwei-xilinx
changed the title
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To ensure control overlay consistency when reconfiguring across multiple designs.
AIECtrlPacketInferTilesPasswhich infers tile ops from control packet op's addresses; tile ops are handles used to generate column control overlays.AIECtrlPacketToDmaPasswhich converts control packet ops into memcpy ops (and sync ops) representing data movements, sending control packets from DDR via shim to tiles.ctrl_packet_reconfigto generate control packets using compiler passes, rather than copy-pasting from a text file.