AieMlMemTileStrmSwSlavePortMap is wrong

[makslevental]

aie-rt/driver/src/global/xaiemlgbl_reginit.c

Lines 1966 to 1994 in 026da82

	/* PhyPort 11 */
	.PortType = NORTH,
	.PortNum = 0,
	},
	{
	/* PhyPort 12 */
	.PortType = NORTH,
	.PortNum = 1,
	},
	{
	/* PhyPort 13 */
	.PortType = NORTH,
	.PortNum = 2,
	},
	{
	/* PhyPort 14 */
	.PortType = NORTH,
	.PortNum = 3,
	},
	{
	/* PhyPort 15 */
	.PortType = NORTH,
	.PortNum = 4,
	},
	{
	/* PhyPort 16 */
	.PortType = NORTH,
	.PortNum = 5,
	},

should be

	{
		/* PhyPort 11 */
		.PortType = SOUTH,
		.PortNum = 4,
	},
	{
		/* PhyPort 12 */
		.PortType = SOUTH,
		.PortNum = 5,
	},
	{
		/* PhyPort 13 */
		.PortType = NORTH,
		.PortNum = 0,
	},
	{
		/* PhyPort 14 */
		.PortType = NORTH,
		.PortNum = 1,
	},
	{
		/* PhyPort 15 */
		.PortType = NORTH,
		.PortNum = 2,
	},
	{
		/* PhyPort 16 */
		.PortType = NORTH,
		.PortNum = 3,
	},

See Figure 6-9: Stream-switch ports and connectivity matrix in arch spec.

cc @jtuyls