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Can't build a simple vision/L2 example #80
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These first few hurdles, in my case, can be bypassed with: CXXFLAGS += -I/home/xilinx/ros2_ws/acceleration/firmware/select/sysroots/aarch64-xilinx-linux/usr/include
LDFLAGS += -L/home/xilinx/ros2_ws/acceleration/firmware/select/sysroots/aarch64-xilinx-linux/usr/lib Which leads to further issues, so I'm stopping here and asking for support. AFAIK this should work out of the box, but it doesn't. Am I wrong somewhere? Otherwise, please clarify how to get this right. |
For the record, I tried other targets, this is not a target's issue. |
Hi @vmayoral , Few of the platforms specific flags as in here in all the Makefiles are set based on the platform. Hence if the build is targeted for a different platform, as in your case, these flags need to be manually set in the Makefile and the build is expected to work fine. Please try this and let us know (attaching the log) if issue still persists. |
This issue is also reported here #43 and we are working on removing this limitation from the Makefiles. |
@vt-lib-support, this points to Nevertheless, here's my attempt targeting the ZCU102 (which is listed as supported) on a plain new terminal: source /tools/Xilinx/Vitis/2020.2/settings64.sh
export DEVICE=/home/xilinx/ros2_ws/acceleration/firmware/zcu102/platform/xilinx_zcu102_base_202020_1.xpfm
export SYSROOT=/home/xilinx/ros2_ws/acceleration/firmware/zcu102/sysroots/aarch64-xilinx-linux
export EDGE_COMMON_SW=/home/xilinx/ros2_ws/acceleration/firmware/zcu102
make host xclbin TARGET=sw_emu HOST_ARCH=aarch64 xilinx@xilinx:~/ros2_ws/src/Vitis_Libraries/vision/L2/examples/resize$ make host xclbin TARGET=sw_emu HOST_ARCH=aarch64
Cannot find OpenCV include path. Please set OPENCV_INCLUDE variable
make: *** [Makefile:216: check_env] Error 1 This leads to instructions missing in the README @vt-lib-support. I'll try and get a complete setup running by setting the embedded variables right next. |
After a while on this, I gave up. There're simply too many things that need to be modified for this to be a useful blueprint at I unfortunately don't have more time to help with this but I encourage a huge re-consideration of the instructions provided and build logic (Makefiles essentially). After various modifications in the source code, and in the build system provided (I essentially discarded Makefiles and built a complete new CMakeLists.txt file that allowed me to integrate On a side note, @vt-lib-support please consider the input in here. As is, with The need for dockerized systematic builds across Xilinx's organization's examples is a huge need identified that I very much encourage. Edit: I'm still interested in getting HLS capabilities to work, so I'd appreciate insights on #79 (comment). |
* Add hls_security.h as top header. Add aes.h as header for Advanced Encryption Standard related function. Add aes.cpp for implementation of AES256 encryption module. * First commit in gh-pages * Update html * update sha2 doc * update aes doc * update doc html * delete old doc * update doc html * add .nojekyll * update doc on QoR * update doc * udpate doc * update doc * update doc * update doc * update benchmark doc page * update gh-pages on release note * update gh-pages * update doc pages * update gh-pages * Create .nojekyll * gh-pages XF Security -> Vitis Security * update doc * update doc to d2939b6 * update doc * update doc * update doc * update gh-pages * Update documentation 2019.2 (#4) * udpate gh-pages on 2019.2 * update gh-pages on 2020.1 * update gh-pages on 2020.1 * update doc (#37) * update 2020.2 gh-pages on version (#40) * Update index.html * Benchmarking for 2021.1 (#56) * update 2021.1 doc with correct version and aligned benchmark page title (#73) Co-authored-by: sdausr <sdausr@xilinx.com> * update HTML doc for benchmark page and logo (#75) Co-authored-by: sdausr <sdausr@xilinx.com> * update HTML doc for benchmark page and logo (#76) Co-authored-by: sdausr <sdausr@xilinx.com> * add release note (#80) Co-authored-by: sdausr <sdausr@xilinx.com> * Update index.html Co-authored-by: Tuo Lin <tuol@xilinx.com> Co-authored-by: Yuanjie Huang <yuanjieh@xilinx.com> Co-authored-by: Feng Xing <feng.xing@xilinx.com> Co-authored-by: SDA USR <sdausr@xilinx.com> Co-authored-by: SDA USR <1391+sdausr@users.noreply.gitenterprise.xilinx.com> Co-authored-by: Tuo Lin <tuo.lin@xilinx.com>
9d08e6d Update index.html 0114189 Merge pull request #93 from RepoOps/gh-pages-20210927-032739 cd52282 [xf_hpc] update release version cdffb7b update index 83b408e Merge pull request #92 from RepoOps/gh-pages-20210927-031807 c126cc9 Update release.rst.txt b5ede6b [xf_hpc] build documents 96dd08b Merge pull request #82 from RepoOps/gh-pages-20210615-023421 b886cd4 update documents a1cf259 Merge pull request #80 from RepoOps/gh-pages-20210614-075104 fb13c8b update release notes 6095532 Merge pull request #79 from RepoOps/gh-pages-20210610-095713 8f6b9e2 fix version errors 73ab5f2 Merge pull request #78 from RepoOps/gh-pages-20210610-070616 b5d0b01 update release notes 46a85d2 Merge pull request #76 from RepoOps/gh-pages-20210608-045126 32fd3e1 build documents ceb4613 update docs Co-authored-by: sdausr <sdausr@xilinx.com>
Hi, I am facing the same issue with exact hardware zcu102 and libraries. Thanks, |
Hi @kapoor7997 , Please post your error and the steps you used for the build. |
I followed the same steps as vmayoral and got the same error. The error I get is Error: Plese do the needful on that, I need support from the community. IT would be really appriciated if you can provide exact steps to create images and how I can use vitis vision library L2 demo om zcu102 board. Thanks, |
Hi @kapoor7997 , We see that you intend to build the function for zcu102 but have set the DEVICE to kv260 which looks incorrect. Please follow the steps mentioned in the Embedded Devices section of this README on how to get the required platform and follow the steps mentioned there to install sysroot. |
Hi vt-lib-support, In previous comment we just copied comments from the vmayoral as we observed the same error while building vitis vision library demo. Please find below mentioned actual error logs and steps which we followed from the README file which you have shared: we are trying to run the Vitis Vision Library color detection demo. Steps we followed on command prompt: source /tools/Xilinx/Vitis/2020.2/settings64.sh source /opt/xilinx/xrt/setup.sh Our Console Output: dev@dev-MS-7B98:~/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix$ make host xclbin TARGET=hw DEVICE=zcu102 HOST_ARCH=aarch64 I have attached snapshots confirming that the opencv exists in the usr/include and usr/lib of the sysroot that I generated from my petalinux project. It will be really appreciated if you can share any pre built images for vitis color detection demo or any kind of image processing demo for zcu102. We just wanna figure our what environment settings do we need so we can then write our actual code. We are not sure why opencv is not being detected for us. Thanks, |
Hi @kapoor7997 , Since you are already setting the DEVICE as env variable pointing to your platform xpfm file, there is no need to set it again with the make command. So your build command should be: Also, as your platform seems to be custom built (not among the one in platform_whitelist of description.json), please add the following flags in the Makefile:
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I was using the command as mentioned in the README you chared, which is- README command Your Command ****** v++ v2020.2 (64-bit) INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at: ===>The following messages were generated while performing high-level synthesis for kernel: ccm_accel Log file: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log : Now YOUR command ****** v++ v2020.2 (64-bit) INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at: ===>The following messages were generated while performing high-level synthesis for kernel: ccm_accel Log file: /home/dev/Downloads/XilinxVision/VisionLibraryStuff2020.2/Vitis_Libraries/vision/L2/examples/colorcorrectionmatrix/_x_temp.hw.ouropencvplatform5/ccm_accel/ccm_accel/vitis_hls.log : |
Hi @kapoor7997 , I see overall 3 issues in your build:
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vitis_hls.log First of I all I want to provide info about my system.
Now results of your previous instructions: Thanks, |
Hi @kapoor7997 , Regarding the effect of license expiration, you can get support on the Xilinx forums. On the build issues:
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Hi vt-lib-support, I followed your steps. I created a new Vitis Vision library from github in folder VLStuff2020.2v2. The commands I used are as follows: Then the synthesis succedded and after running the command Here we are using Xilinx's sysroots, xilinx common image files and xilinx xsa for platform .xpfm and the console output after running the run_script.sh is: root@xilinx-zcu102-2020_2:/media/sd-mmcblk0p1# sh run_script.sh Then we found from here(https://support.xilinx.com/s/article/1138667?language=en_US) that we need to add zocl, xrt and other things to the user-rootfsconfig. Now we had to create our own petalinux project because we dont have access to xilinx's petalinux project. So we created our own petalinux project with opencv enabled like its shown here(https://opencvguide.readthedocs.io/en/latest/opencvpetalinux/basics.html), And then added the following to the user-rootfsconfig like this: CONFIG_xrt And then in the rootfs config → Filesystem Packages → libs, we enabled the following: And then added device tree entry to the system-user.dtsi like this: &axi_intc_0 { &amba { and then created our image files from this petalinux project and then used xilinx's sysroots tobuild sd_card files and then ran this on the board after building. And we got the same error Console output after running run_script.sh with our petalinux project: root@xilinx-zcu102-2020_2:/mnt/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ How do we resolve this error. Need Help!!! Regards, |
Hi @kapoor7997 , Good to know that you were able to build and generate the sd_card for your project with the base platform. Before going to the analysis of runtime error, we would like to state that there is no need to update/modify/edit any parts of the generated sd_card image and it is expected to run as is. The article you pointed to is for creating a custom software platform instead of using Xilinx base platform. So it does not apply here. On the error, it could be an issue with the XRT version. You may try the following; On a new terminal, in the same project folder, source all the environment settings except the xrt and do the host and sd_card build as follows (this forces the executable to use the xrt from sysroot instead of local system):
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Hi vt-lib-support, I used all xilinx files and ran exact commands given by you. And as you suggested, I didn't source the xrt make host sd_card TARGET=hw HOST_ARCH=aarch64 And this is the result of the device console after executing the script run_script.sh root@zynqmp-common-2020_2: Attached is the picture of the xrt version from my board after building sd_card folder I have also attached the contents of the XRT library folder from the sysroots provided by xilinx which I used for building THEN I used the "make host xclbin TARGET=hw HOST_ARCH=aarch64" and "make run TARGET=hw HOST_ARCH=aarch64" and the console output is the following I ran run_script twice and console output is the following 1st run 2nd run root@zynqmp-common-2020_2:/media/sd-mmcblk0p1# export XCL_BINDIR=/mnt/sd-mmcblk0p1/ Also Attached the complete colsole output from the run. Thanks, |
My setup includes: I built everything from scratch cause I wanted to be sure non of my changes affect the build.
COMMANDS: I used the following commands for setting the environment variables for the colorcorrectionmatrix example from L2:- source /tools/Xilinx/Vitis/2020.2/settings64.sh Note: I did not add any of the following additional flags Here is the console output in a text file for the run on hardware(zcu102 board) The output looks like this QUESTION Thanks, |
Hi @kapoor7997 , Ques1: Does the base image platform have zocl and interrupts setup correectly in vivado design/hardware file(xsa). This looks like some issue with the hardware setup and not with the library code. (Please run software emulation and hardware emulation to confirm on your end too) We suggest you to create a ticket in the Xilinx forums where you can get the technical assistance to debug your stall issue on the board. This page has the info on the process. |
Hi vt-lib-support, As per your suggestion, we tried hw_emu and sw_emu. we ran the following commands from this link(https://xilinx.github.io/Vitis_Libraries/vision/2020.1/overview.html section Evaluating the Functionality) source /tools/Xilinx/Vitis/2020.2/settings64.sh And make host xclbin TARGET=sw_emu BOARD=Zynq ARCH=aarch64 In both cases we used xilinx base image and xilinx common image for sysroot. We got multiple errors and logs are attached. We have been working on getting the vitis vision libraries working for a month now and haven't gotten anywhere. 10 days ago, the vt-lib-support team completely stopped replying. I represent Crypto-knight Mining Corp from Vancouver. Thanks, |
b8aa0ac Merge pull request #98 from changg/round2-mk 0dafa9e fix 69ce1de Merge pull request #97 from changg/round2-mk 33635fb fix utils.mk bb09f85 Merge pull request #96 from tuol/fix_cr_1125397 26bfd12 upate description.json for GUI 6142bf4 Merge pull request #95 from tuol/fix_cr1110852 18b6b69 add description for cscmvSingleHBM 489d6fe Merge pull request #94 from changg/wa_u280 c83ed11 WA for u280 70d666c Revert "wa for xilinx_u280_xdma_201920_3" 27306c5 Merge pull request #93 from changg/wa_u280_2019 2b4ec88 wa for xilinx_u280_xdma_201920_3 af1d094 Merge pull request #92 from liyuanz/replace_cflags a9ff957 replace cflags with clflags eb58a83 Merge pull request #91 from tuol/fix_cr_1110852 c9ca9ab add description to L2/tests/cscmvSingleHbm b8e0210 Merge pull request #90 from tuol/fix_cr_1083211 75204c8 remove 'exclude' from description.json 965b2e0 Merge pull request #88 from liyuanz/replace_blacklist 0e87eee replace whiltelist/blacklist to allowlist/blocklist ad26de7 Merge pull request #87 from liyuanz/next 3db258c increase time def14fe Merge pull request #85 from changg/add_extraflags f8a6122 fix makefile 031de2c Merge pull request #84 from liyuanz/next f10953c increase time 4745f24 Merge pull request #83 from changg/fix_utils 6fb2652 fix utisl 7d9278f Merge pull request #82 from liyuanz/replace_targets c1c2de5 update targes 68ae52e Merge pull request #80 from changg/metadata 6225d51 draft metadata files e74cf2b change 2021.2_stable_latest to 2022.1_stable_latest Co-authored-by: sdausr <sdausr@xilinx.com>
Trying now quickly the examples aimed for Vitis (instead of for HLS which fail, refer to #79) described in the instructions.
Using in particular resize:
The text was updated successfully, but these errors were encountered: