Can't build a simple vision/L1 example #79
Comments
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Hi @vmayoral , I'm assuming you are building this example on a x86 CPU. If yes, the L1 examples expects OpenCV includes and libs also for x86. Hence the OPENCV_INCLUDE and OPENCV_LIB variables should point to the x86 version and not the aarch64 libs that you seem to be using from the sysroot path. |
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@vt-lib-support thanks for the quick reaction. Appreciate it. As a side comment:
Then this should be specified clearly, and an example should be provided (even if hardcoded for a particular setup) so that users have a good intuition of what's expected. There're too many assumption of previous background and familiarity with tools across the libraries. Note there's prior evidence showing how the current setup leads to confusion (e.g. here). I did what's suggested: and still crashes: dumpxilinx@xilinx:~/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize$ make run CSIM=1 CSYNTH=0 COSIM=0
Configured: settings.tcl
----
set XPART XCK26-SFVC784-2LV-C
set CSIM 1
set CSYNTH 0
set COSIM 0
set VIVADO_SYN 0
set VIVADO_IMPL 0
set XF_PROJ_ROOT "/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/"
set OPENCV_INCLUDE "/usr/include/opencv4"
set OPENCV_LIB "/usr/lib/x86_64-linux-gnu/"
set CUR_DIR "/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize"
----
vitis_hls -f run_hls.tcl;
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:13:49 MST 2021
**** IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'xilinx' on host 'xilinx' (Linux_x86_64 version 5.11.0-27-generic) on Mon Aug 30 10:08:49 CEST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize'
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset resize.prj
INFO: [HLS 200-10] Opening and resetting project '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj'.
WARNING: [HLS 200-40] No /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/sol1.aps file found.
INFO: [HLS 200-1510] Running: add_files /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_accel.cpp -cflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x -csimflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x
INFO: [HLS 200-10] Adding design file '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_accel.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_tb.cpp -cflags -I/usr/include/opencv4 -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x -csimflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x
INFO: [HLS 200-10] Adding test bench file '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_tb.cpp' to the project
INFO: [HLS 200-1510] Running: set_top resize_accel
INFO: [HLS 200-1510] Running: open_solution -reset sol1
INFO: [HLS 200-10] Creating and opening solution '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/sol1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part XCK26-SFVC784-2LV-C
INFO: [HLS 200-10] Setting target device to 'xck26-sfvc784-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 3.3
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.3ns.
INFO: [HLS 200-1510] Running: csim_design -ldflags -L /usr/lib/x86_64-linux-gnu/ -lopencv_imgcodecs -lopencv_imgproc -lopencv_core -lopencv_highgui -lopencv_flann -lopencv_features2d -argv /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//data/128x128.png
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
make[1]: Entering directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/csim/build'
Compiling ../../../../xf_resize_tb.cpp in debug mode
make[1]: Leaving directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/csim/build'
In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_structs.hpp:27:0,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_common.hpp:20,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_sw_utils.hpp:20,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_headers.hpp:28,
from ../../../../xf_resize_tb.cpp:17:
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:97:40: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <typename T> constexpr size_t bitwidth = sizeof(T) * CHAR_BIT;
^~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:99:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_int<W>> = W;
^~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:100:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_uint<W>> = W;
^~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:102:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:104:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:107:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bytewidth = (bitwidth<T> + CHAR_BIT - 1) / CHAR_BIT;
^~~~~~~~~
../../../../xf_resize_tb.cpp: In function ‘int main(int, char**)’:
../../../../xf_resize_tb.cpp:67:72: error: ‘CV_INTER_LINEAR’ was not declared in this scope
cv::resize(img, result_ocv, cv::Size(out_width, out_height), 0, 0, CV_INTER_LINEAR);
^~~~~~~~~~~~~~~
make[1]: *** [csim.mk:74: obj/xf_resize_tb.o] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 2.47 seconds. CPU system time: 0.32 seconds. Elapsed time: 2.56 seconds; current allocated memory: 195.019 MB.
4
while executing
"source run_hls.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "
INFO: [Common 17-206] Exiting vitis_hls at Mon Aug 30 10:08:53 2021...
make: *** [Makefile:249: runhls] Error 1I then fixed this through #81. But again, there're linking errors: make run CSIM=1 CSYNTH=0 COSIM=0
Configured: settings.tcl
----
set XPART XCK26-SFVC784-2LV-C
set CSIM 1
set CSYNTH 0
set COSIM 0
set VIVADO_SYN 0
set VIVADO_IMPL 0
set XF_PROJ_ROOT "/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/"
set OPENCV_INCLUDE "/usr/include/opencv4"
set OPENCV_LIB "/usr/lib/x86_64-linux-gnu/"
set CUR_DIR "/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize"
----
vitis_hls -f run_hls.tcl;
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:13:49 MST 2021
**** IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'xilinx' on host 'xilinx' (Linux_x86_64 version 5.11.0-27-generic) on Mon Aug 30 10:30:35 CEST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize'
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset resize.prj
INFO: [HLS 200-10] Opening and resetting project '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj'.
WARNING: [HLS 200-40] No /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/sol1.aps file found.
INFO: [HLS 200-1510] Running: add_files /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_accel.cpp -cflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x -csimflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x
INFO: [HLS 200-10] Adding design file '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_accel.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_tb.cpp -cflags -I/usr/include/opencv4 -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x -csimflags -I/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include -I /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/build -I ./ -D__SDSVHLS__ -std=c++0x
INFO: [HLS 200-10] Adding test bench file '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/examples/resize/xf_resize_tb.cpp' to the project
INFO: [HLS 200-1510] Running: set_top resize_accel
INFO: [HLS 200-1510] Running: open_solution -reset sol1
INFO: [HLS 200-10] Creating and opening solution '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/sol1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part XCK26-SFVC784-2LV-C
INFO: [HLS 200-10] Setting target device to 'xck26-sfvc784-2LV-c'
INFO: [HLS 200-1510] Running: create_clock -period 3.3
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.3ns.
INFO: [HLS 200-1510] Running: csim_design -ldflags -L /usr/lib/x86_64-linux-gnu/ -lopencv_imgcodecs -lopencv_imgproc -lopencv_core -lopencv_highgui -lopencv_flann -lopencv_features2d -argv /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//data/128x128.png
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
make[1]: Entering directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/csim/build'
Compiling ../../../../xf_resize_tb.cpp in debug mode
Compiling ../../../../xf_resize_accel.cpp in debug mode
Generating csim.exe
make[1]: Leaving directory '/home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resize/resize.prj/sol1/csim/build'
In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_structs.hpp:27:0,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_common.hpp:20,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_sw_utils.hpp:20,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_headers.hpp:28,
from ../../../../xf_resize_tb.cpp:17:
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:97:40: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <typename T> constexpr size_t bitwidth = sizeof(T) * CHAR_BIT;
^~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:99:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_int<W>> = W;
^~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:100:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_uint<W>> = W;
^~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:102:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:104:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:107:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bytewidth = (bitwidth<T> + CHAR_BIT - 1) / CHAR_BIT;
^~~~~~~~~
In file included from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_structs.hpp:27:0,
from /home/xilinx/ros2_ws/src/Vitis_Libraries/vision//L1/include/common/xf_common.hpp:20,
from ../../../../xf_resize_config.h:22,
from ../../../../xf_resize_accel.cpp:17:
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:97:40: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <typename T> constexpr size_t bitwidth = sizeof(T) * CHAR_BIT;
^~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:99:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_int<W>> = W;
^~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:100:38: warning: variable templates only available with -std=c++14 or -std=gnu++14
template <size_t W> constexpr size_t bitwidth<ap_uint<W>> = W;
^~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:102:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_fixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:104:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bitwidth<ap_ufixed<_AP_W, _AP_I, _AP_Q, _AP_O, _AP_N>> = _AP_W;
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tools/Xilinx/Vitis_HLS/2020.2/include/ap_axi_sdata.h:107:18: warning: variable templates only available with -std=c++14 or -std=gnu++14
constexpr size_t bytewidth = (bitwidth<T> + CHAR_BIT - 1) / CHAR_BIT;
^~~~~~~~~
/usr/lib/x86_64-linux-gnu//libgeos-3.8.0.so: undefined reference to `std::runtime_error::runtime_error(std::runtime_error&&)@GLIBCXX_3.4.26'
/usr/lib/x86_64-linux-gnu//libopencv_imgcodecs.so: undefined reference to `std::__cxx11::basic_stringstream<char, std::char_traits<char>, std::allocator<char> >::basic_stringstream()@GLIBCXX_3.4.26'
/usr/lib/x86_64-linux-gnu//libtbb.so.2: undefined reference to `__cxa_init_primary_exception@CXXABI_1.3.11'
/usr/lib/x86_64-linux-gnu//libtbb.so.2: undefined reference to `std::__exception_ptr::exception_ptr::exception_ptr(void*)@CXXABI_1.3.11'
/usr/lib/x86_64-linux-gnu//libdap.so.25: undefined reference to `std::logic_error::logic_error(std::logic_error&&)@GLIBCXX_3.4.26'
/usr/lib/x86_64-linux-gnu//libopencv_flann.so: undefined reference to `std::__cxx11::basic_ostringstream<char, std::char_traits<char>, std::allocator<char> >::basic_ostringstream()@GLIBCXX_3.4.26'
collect2: error: ld returned 1 exit status
make[1]: *** [Makefile.rules:393: csim.exe] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 8.22 seconds. CPU system time: 0.52 seconds. Elapsed time: 8.49 seconds; current allocated memory: 195.020 MB.
4
while executing
"source run_hls.tcl"
("uplevel" body line 1)
invoked from within
"uplevel \#0 [list source $arg] "
INFO: [Common 17-206] Exiting vitis_hls at Mon Aug 30 10:30:45 2021...
make: *** [Makefile:249: runhls] Error 1@vt-lib-support, is there a public CI that shows that this is maintained and works as is for |
|
Hi @vmayoral , The info related to the OpenCV lib version according to the target OS is mentioned in the Prerequisites section of the documentation. We will enhance this information and also will copy into the README too for easy visibility to the users. 2020.2 Vision library is tested against OpenCV version 3.4.2, as mentioned in the documentation. So, the fix that you provided in #81 might not be applicable to 2020.2 The 2021.1 release ( which happens to be the latest release) uses OpenCV 4.4 (mentioned in the documentation) and already uses the APIs that you provided in #81 Looking at the linking errors that you posted, seems like it is error related to incompatibility between the OpenCV libs and the tool's GCC compiler version. Please try building the OpenCV libs compatible to the GCC version that you are using for the CSIM build. Please let us know for any further assistance. |
I think you meant https://xilinx.github.io/Vitis_Libraries/vision/2020.2/overview.html#getting-started-with-vitis-vision, right?
Thanks for the heads up. Can you be more specific? Which version of the library with which version of the compiler? |
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* Squashed 'hpc/' changes from 1c6ac0e..f28aa9a f28aa9a update release notes e9f956a Merge branch 'dev2021.1' into next 04c17bc update release notes 366f577 update release notes 26599b6 Merge branch 'dev2021.1' into next 4e191d6 updates a40a413 update notes 01d565a Merge branch 'next' of gitenterprise.xilinx.com:FaaSApps/xf_hpc into next fd999c0 Merge branch 'dev2021.1' into next dbe158b fix version error bb0beb4 Merge pull request #77 from liangm/next 95b21eb merge dev2021.1 4ee28f5 Merge branch 'dev2021.1' of gitenterprise.xilinx.com:FaaSApps/xf_hpc into dev2021.1 a188c06 update makefiles 26fd0ea update release notes b7d6078 Update params.mk 550280c Update params.mk git-subtree-dir: hpc git-subtree-split: f28aa9aab61bf0cb761a7844986cad6a2320479f * Squashed 'codec/' changes from de296e9..15255a2 15255a2 Merge pull request #81 from yunleiz/mergenext b0d5c50 [kernel] fixed clamping after the idct c91288a Merge pull request #79 from yunleiz/mergenext d6b90eb [doc] image for document git-subtree-dir: codec git-subtree-split: 15255a29990d2fd5cbdbf24ff74223cb5612419a Co-authored-by: sdausr <sdausr@xilinx.com>
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f0e0005 Merge pull request #83 from liyuanz/add_time 361913d add time 64ea0f9 Merge pull request #82 from liyuanz/next 8386360 update 370bb26 Merge pull request #81 from liyuanz/next 4716b14 add memory or time 2b41485 Merge pull request #79 from yuxiangz/makefile a5df524 update makefile for hw_emu bc265f0 Merge pull request #77 from tianminr/L3_dev bd9b7c5 Merge pull request #76 from yuxiangz/sizein d2a2ab6 update scanline case 591cebc add golden out size 4898af0 push request for regress 4cee657 turn up c13c69b update error kernel for kernel_ratio setting 1379c0d Merge remote-tracking branch 'xf_ultrasound/next' into L3_dev 43ecd58 update L2 graph & kernel ratio setup for scanline 5c9a2e5 update host 8a8bc80 Merge pull request #71 from yuxiangz/graph_l3 bd69baf turn memory up 3 b7ee6a5 Merge pull request #73 from siyangw/IO_Dev f516f8e Merge pull request #72 from tianminr/L3_dev a467fa5 turn memory up 9d3c0cc revise description.json bbaee77 Merge pull request #70 from siyangw/IO_Dev f0d9dd8 scanline graph update 22db53e scanline sw_emu pass b0487bd update port name 4404027 sw_emu pass 2571dd9 plane wave pass sw_emu 19e4cc3 Merge remote-tracking branch 'ultrasound/next' into IO_Dev 081a881 plane wave pass x86sim and aiesim 5c27d04 build graph for L3 Co-authored-by: sdausr <sdausr@xilinx.com>
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I'm trying to build a simple Vitis Vision Library L1 example using Vitis
2020.2.Here's my setup for resize:
$ pwd /home/xilinx/ros2_ws/src/Vitis_Libraries/vision/L1/examples/resizeThen build following instructions:
This results into a number of failures which are available below:
errors
This setup is known to work with other HLS examples. These issues just arise when trying the vision examples. I spent some time researching similar issues in the public domain, as well as bypassing some of the undefined symbols by manually adding flags to
cflagsbut it didn't scale nice and errors kept piling up.Any guidance will be appreciated.
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