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Linux Device Tree
Georgi Angelov edited this page Nov 5, 2019
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3 revisions
decompiled
/dts-v1/;
// version: 17
// last_comp_version: 16
// boot_cpuid_phys: 0x0
/ {
compatible = "mediatek,mt3620";
interrupt-parent = <0x00000001>;
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
model = "MT3620";
cpus {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x00000000>;
phandle = <0x0000001c>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x00400000>;
};
flash@90000000 {
compatible = "azure-sphere-flash", "mtd-rom";
reg = <0x90000000 0x01000000>;
bank-width = <0x00000001>;
};
interrupt-controller@101000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <0x00000003>;
#address-cells = <0x00000000>;
interrupt-controller;
reg = <0x00101000 0x00001000 0x00102000 0x00001000>;
phandle = <0x00000001>;
};
uart_clk {
compatible = "fixed-clock";
clock-frequency = <0x018cba80>;
#clock-cells = <0x00000000>;
phandle = <0x00000002>;
};
i2c_clk {
compatible = "fixed-clock";
clock-frequency = <0x018cba80>;
#clock-cells = <0x00000000>;
phandle = <0x00000005>;
};
rtc_clk {
compatible = "fixed-clock";
clock-frequency = <0x00007d00>;
#clock-cells = <0x00000000>;
phandle = <0x00000007>;
};
adc_clk {
compatible = "fixed-clock";
clock-frequency = <0x001e8480>;
#clock-cells = <0x00000000>;
phandle = <0x00000019>;
};
spi_clk {
compatible = "fixed-clock";
clock-frequency = <0x04c4b400>;
#clock-cells = <0x00000000>;
phandle = <0x00000004>;
};
pwm_clk {
compatible = "fixed-clock";
clock-frequency = <0x001e8480>;
#clock-cells = <0x00000000>;
phandle = <0x00000006>;
};
timer {
compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
#interrupt-cells = <0x00000003>;
interrupts = <0x00000001 0x0000000d 0x00000f08 0x00000001 0x0000000e 0x00000f08 0x00000001 0x0000000b 0x00000f08 0x00000001 0x0000000a 0x00000f08>;
soc {
#address-cells = <0x00000001>;
#size-cells = <0x00000001>;
compatible = "simple-bus";
ranges;
phandle = <0x0000001d>;
uart@31040000 {
compatible = "mediatek,mt3620-uart";
reg = <0x31040000 0x00000400>;
interrupts = <0x00000000 0x00000005 0x00000004>;
clocks = <0x00000002>;
phandle = <0x0000001e>;
};
uart@38070500 {
compatible = "mediatek,mt3620-uart";
reg = <0x38070500 0x00000400>;
interrupts = <0x00000000 0x00000018 0x00000004>;
clocks = <0x00000002>;
phandle = <0x0000001f>;
};
uart@38080500 {
compatible = "mediatek,mt3620-uart";
reg = <0x38080500 0x00000400>;
interrupts = <0x00000000 0x00000054 0x00000004>;
clocks = <0x00000002>;
phandle = <0x00000020>;
};
uart@38090500 {
compatible = "mediatek,mt3620-uart";
reg = <0x38090500 0x00000400>;
interrupts = <0x00000000 0x00000058 0x00000004>;
clocks = <0x00000002>;
phandle = <0x00000021>;
};
uart@380A0500 {
compatible = "mediatek,mt3620-uart";
reg = <0x380a0500 0x00000400>;
/ {
/ {
// [NOP]
clocks = <0x00000002>;
phandle = <0x00000022>;
};
uart@380B0500 {
compatible = "mediatek,mt3620-uart";
reg = <0x380b0500 0x00000400>;
interrupts = <0x00000000 0x00000060 0x00000004>;
clocks = <0x00000002>;
phandle = <0x00000023>;
};
uart@380C0500 {
compatible = "mediatek,mt3620-uart";
reg = <0x380c0500 0x00000400>;
interrupts = <0x00000000 0x00000064 0x00000004>;
clocks = <0x00000002>;
phandle = <0x00000024>;
};
spi@38070300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x38070300 0x000000ff>;
interrupts = <0x00000000 0x00000016 0x00000004>;
dmas = <0x00000003 0x00000000 0x00000003 0x00000001>;
dma-names = "spi-dma-tx", "spi-dma-rx";
clocks = <0x00000004>;
status = "disabled";
phandle = <0x00000025>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
spi@38080300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x38080300 0x000000ff>;
interrupts = <0x00000000 0x00000052 0x00000004>;
dmas = <0x00000003 0x00000002 0x00000003 0x00000003>;
dma-names = "spi-dma-tx", "spi-dma-rx";
clocks = <0x00000004>;
status = "disabled";
phandle = <0x00000026>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
spi@38090300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x38090300 0x000000ff>;
interrupts = <0x00000000 0x00000056 0x00000004>;
dmas = <0x00000003 0x00000004 0x00000003 0x00000005>;
dma-names = "spi-dma-tx", "spi-dma-rx";
clocks = <0x00000004>;
status = "disabled";
phandle = <0x00000027>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
spi@380a0300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x380a0300 0x000000ff>;
/ {
/ {
// [NOP]
dmas = <0x00000003 0x00000006 0x00000003 0x00000007>;
dma-names = "spi-dma-tx", "spi-dma-rx";
clocks = <0x00000004>;
status = "disabled";
phandle = <0x00000028>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
spi@380b0300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x380b0300 0x000000ff>;
interrupts = <0x00000000 0x0000005e 0x00000004>;
dmas = <0x00000003 0x00000008 0x00000003 0x00000009>;
dma-names = "spi-dma-tx", "spi-dma-rx";
clocks = <0x00000004>;
status = "disabled";
phandle = <0x00000029>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
spi@380c0300 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "mediatek,mt3620-spi";
reg = <0x380c0300 0x000000ff>;
interrupts = <0x00000000 0x00000062 0x00000004>;
dmas = <0x00000003 0x0000000a 0x00000003 0x0000000b>;
/ {
dma-tx {
ma-rx {
clocks = <0x00000004>;
status = "disabled";
phandle = <0x0000002a>;
spidev@0 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000000>;
spi-max-frequency = <0x02625a00>;
};
spidev@1 {
compatible = "mediatek,mt3620-spi";
reg = <0x00000001>;
spi-max-frequency = <0x02625a00>;
};
};
i2c@38070200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x38070200 0x00000100 0x38070000 0x000000c0>;
interrupts = <0x00000000 0x00000015 0x00000004>;
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x00000000 0x00000003 0x00000001>;
dma-names = "i2c-gdma-tx", "i2c-gdma-rx";
status = "disabled";
phandle = <0x0000002b>;
};
i2c@38080200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x38080200 0x00000100 0x38080000 0x000000c0>;
interrupts = <0x00000000 0x00000051 0x00000004>;
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x00000002 0x00000003 0x00000003>;
dma-names = "i2c-gdma-tx", "i2c-gdma-rx";
status = "disabled";
phandle = <0x0000002c>;
};
i2c@38090200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x38090200 0x00000100 0x38090000 0x000000c0>;
interrupts = <0x00000000 0x00000055 0x00000004>;
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x00000004 0x00000003 0x00000005>;
dma-names = "i2c-gdma-tx", "i2c-gdma-rx";
status = "disabled";
phandle = <0x0000002d>;
};
i2c@380a0200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x380a0200 0x00000100 0x380a0000 0x000000c0>;
/ {
/ {
// [NOP]
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x00000006 0x00000003 0x00000007>;
dma-names = "i2c-gdma-tx", "i2c-gdma-rx";
status = "disabled";
phandle = <0x0000002e>;
};
i2c@380b0200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x380b0200 0x00000100 0x380b0000 0x000000c0>;
interrupts = <0x00000000 0x0000005d 0x00000004>;
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x00000008 0x00000003 0x00000009>;
dma-names = "i2c-gdma-tx", "i2c-gdma-rx";
status = "disabled";
phandle = <0x0000002f>;
};
i2c@380c0200 {
compatible = "mediatek,mt3620-i2c";
reg = <0x380c0200 0x00000100 0x380c0000 0x000000c0>;
interrupts = <0x00000000 0x00000061 0x00000004>;
clocks = <0x00000005>;
clock-names = "main";
dmas = <0x00000003 0x0000000a 0x00000003 0x0000000b>;
/ {
gdma-tx {
gdma-rx {
status = "disabled";
phandle = <0x00000030>;
};
pwm@38011000 {
compatible = "mediatek,mt3620-pwm";
reg = <0x38011000 0x00000200>;
clocks = <0x00000006>;
status = "disabled";
phandle = <0x00000031>;
};
pwm@38021000 {
compatible = "mediatek,mt3620-pwm";
reg = <0x38021000 0x00000200>;
clocks = <0x00000006>;
status = "disabled";
phandle = <0x00000032>;
};
pwm@38031000 {
compatible = "mediatek,mt3620-pwm";
reg = <0x38031000 0x00000200>;
clocks = <0x00000006>;
status = "disabled";
phandle = <0x00000033>;
};
timer@3103e000 {
compatible = "mediatek,mt3620-timer";
reg = <0x3103e000 0x00000044>;
interrupts = <0x00000000 0x00000020 0x00000004>;
clocks = <0x00000002 0x00000007>;
clock-names = "system-clk", "rtc-clk";
phandle = <0x00000034>;
};
watchdog@30050030 {
compatible = "mediatek,mt3620-wdt";
reg = <0x30050030 0x00000080>;
interrupts = <0x00000000 0x00000004 0x00000001>;
phandle = <0x00000035>;
};
audio-controller@380d0000 {
compatible = "mediatek,MT3620-afe-pcm";
reg = <0x380d0000 0x00020000 0x380f0000 0x00000004 0x38100000 0x00000004>;
interrupts = <0x00000000 0x0000009e 0x00000004>;
phandle = <0x00000008>;
};
sound {
compatible = "mediatek,MT3620-evb";
mediatek,platform = <0x00000008>;
status = "okay";
phandle = <0x00000036>;
};
mfd@38010000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38010000 0x00000300>;
phandle = <0x00000009>;
};
mfd@38020000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38020000 0x00000300>;
phandle = <0x0000000a>;
mfd@38030000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38030000 0x00000300>;
phandle = <0x0000000b>;
};
mfd@38040000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38040000 0x00000300>;
phandle = <0x0000000c>;
};
mfd@38050000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38050000 0x00000300>;
phandle = <0x0000000d>;
};
mfd@38060000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38060000 0x00000300>;
phandle = <0x0000000e>;
};
mfd@30020000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x30020000 0x00000300>;
phandle = <0x0000000f>;
};
mfd@38070000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38070000 0x00000100>;
phandle = <0x00000010>;
};
mfd@38080000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38080000 0x00000100>;
phandle = <0x00000011>;
};
mfd@38090000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38090000 0x00000100>;
phandle = <0x00000012>;
};
mfd@380A0000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x380a0000 0x00000100>;
// [NOP]
/ {
};
mfd@380B0000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x380b0000 0x00000100>;
phandle = <0x00000017>;
};
mfd@380C0000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x380c0000 0x00000100>;
phandle = <0x00000018>;
};
mfd@38000000 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x38000000 0x00000100>;
phandle = <0x00000013>;
};
mfd@380D0100 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x380d0100 0x00000100>;
phandle = <0x00000014>;
};
mfd@380E0100 {
compatible = "mediatek,mt3620-pctl-syscfg", "syscon";
reg = <0x380e0100 0x00000100>;
phandle = <0x00000015>;
};
pinctrl@31060000 {
compatible = "mediatek,mt3620-pinctrl";
reg = <0x31060000 0x00000100>;
pins-are-numbered;
gpio-controller;
#gpio-cells = <0x00000002>;
mediatek,pctl-regmap = <0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000d 0x0000000e 0x0000000f 0x00000010 0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016 0x00000017 0x00000018>;
firewall@30000000 {
compatible = "mediatek,mt3620-firewall";
reg = <0x30000000 0x00010000>;
interrupts = <0x00000000 0x0000001b 0x00000004>;
phandle = <0x00000037>;
};
Real_Time_Clock@30090000 {
compatible = "mediatek,mt3620-rtc";
reg = <0x30090000 0x00000200>;
interrupts = <0x00000000 0x00000000 0x00000004>;
phandle = <0x00000038>;
};
adc@38000100 {
compatible = "mediatek,mt3620-auxadc";
reg = <0x38000100 0x00000200>;
clocks = <0x00000019>;
clock-names = "main";
#io-channel-cells = <0x00000001>;
interrupts = <0x00000000 0x00000067 0x00000004>;
status = "disabled";
phandle = <0x00000039>;
};
mailbox@31000000 {
compatible = "mediatek,mt3620-mailbox";
reg = <0x31000000 0x00030000>;
#interrupt-cells = <0x00000003>;
interrupts = <0x00000000 0x0000002a 0x00000001 0x00000000 0x00000028 0x00000001 0x00000000 0x0000002d 0x00000001 0x00000000 0x00000030 0x00000001 0x00000000 0x0000002e 0x00000001 0x00000000 0x00000033 0x00000001 0x00000000 0x00000036 0x00000001 0x00000000
0x00000034 0x00000001 0x00000000 0x00000039 0x00000001>;
#mbox-cells = <0x00000001>;
mailbox-channel-count = <0x00000003>;
mailbox-max-fifo-count = <0x0000000f>;
phandle = [00 00 00];
0 {
ma1 {
_dma2 {
ma3 {
_dma4 {
ma5 {
_dma6 {
ma7 {
_dma8 {
ma9 {
_dma10 {
dma11 {
dma12 {
a13 {
dma14 {
a15 {
dma16 {
a17 {
dma18 {
a19 {
dma20 {
a21 {
dma22 {
a23 {
dma24 {
a25 {
dma26 {
a27 {
dma28 {
a29 {
dma30 {
_dma31 {
7_dma32 {
dma33 {
#dma-cells = <0x00000001>;
mediatek,ca7dma-dma-num = <0x00000022>;
mediatek,ca7dma-m2m-ch-s = <0x0000000d>;
mediatek,ca7dma-m2m-ch-e = <0x0000000e>;
mediatek,ca7dma-m2m-ch-num = <0x00000002>;
mediatek,ca7dma-peri-ch-s = <0x00000000>;
mediatek,ca7dma-peri-ch-e = <0x0000000c>;
mediatek,ca7dma-peri-ch-num = <0x0000000d>;
mediatek,ca7dma-vff-ch-s = <0x0000000f>;
mediatek,ca7dma-vff-ch-e = <0x00000021>;
mediatek,ca7dma-vff-ch-num = <0x00000013>;
status = "okay";
phandle = <0x00000003>;
};
reset {
compatible = "mediatek,mt362x-reset";
};
hwrng {
compatible = "microsoft,pluton-rng";
};
pluton {
compatible = "mediatek,mt3620-pluton";
mboxes = [00 00 00];
/ {
phandle = <0x0000001b>;
};
wifi {
compatible = "mediatek,mt3620-wifi";
hifproc = <0x0000001b>;
};
};
peripheral_map {
compatible = "microsoft,peripheral_map";
devices = [00 00 00 00 00 00 00 0f 00 00 00 07 00 00 00 0f 00 00 00 0e 00 00 00 ffffffff 00 01 00 00 00 04 00 0f 00 01 00 07 00 04 00 0f 00 02 00 00 00 08 00 0f 00 02 00 07 00 08 00 0f 08 00 00 0e 00 08 00 ffffffff 00 03 00 00 00 0c 00 0f 00 04 00 00 00 10 00 0f 10 00 00 0e 00 10 00 ffffffff 00 05 00 00 00 14 00 0f 00 06 00 00 00];
serial4 = "/soc/uart@38070500";
serial5 = "/soc/uart@38080500";
serial6 = "/soc/uart@38090500";
serial7 = "/soc/uart@380A0500";
serial8 = "/soc/uart@380B0500";
serial9 = "/soc/uart@380C0500";
i2c0 = "/soc/i2c@38070200";
i2c1 = "/soc/i2c@38080200";
i2c2 = "/soc/i2c@38090200";
i2c3 = "/soc/i2c@380a0200";
i2c4 = "/soc/i2c@380b0200";
i2c5 = "/soc/i2c@380c0200";
2c_clk = "/soc/spi@38070300";
spi1 = "/soc/spi@38080300";
spi2 = "/soc/spi@38090300";
spi3 = "/soc/spi@380a0300";
spi4 = "/soc/spi@380b0300";
spi5 = "/soc/spi@380c0300";
pwm0 = "/soc/pwm@38011000";
pwm1 = "/soc/pwm@38021000";
pwm2 = "/soc/pwm@38031000";
adc0 = "/soc/adc@38000100";
};
chosen {
};
__symbols__ {
cpu0 = "/cpus/cpu@0";
gic = "/interrupt-controller@101000";
uart_clk = "/uart_clk";
i2c_clk = "/i2c_clk";
rtc_clk = "/rtc_clk";
adc_clk = "/adc_clk";
spi_clk = "/spi_clk";
pwm_clk = "/pwm_clk";
soc = "/soc";
uart1 = "/soc/uart@31040000";
isu0_uart = "/soc/uart@38070500";
isu1_uart = "/soc/uart@38080500";
isu2_uart = "/soc/uart@38090500";
isu3_uart = "/soc/uart@380A0500";
isu4_uart = "/soc/uart@380B0500";
isu5_uart = "/soc/uart@380C0500";
isu0_spi = "/soc/spi@38070300";
isu1_spi = "/soc/spi@38080300";
isu2_spi = "/soc/spi@38090300";
isu3_spi = "/soc/spi@380a0300";
isu4_spi = "/soc/spi@380b0300";
isu5_spi = "/soc/spi@380c0300";
isu0_i2c = "/soc/i2c@38070200";
isu1_i2c = "/soc/i2c@38080200";
isu2_i2c = "/soc/i2c@38090200";
isu3_i2c = "/soc/i2c@380a0200";
isu4_i2c = "/soc/i2c@380b0200";
isu5_i2c = "/soc/i2c@380c0200";
pwm_group0 = "/soc/pwm@38011000";
pwm_group1 = "/soc/pwm@38021000";
pwm_group2 = "/soc/pwm@38031000";
timer = "/soc/timer@3103e000";
wdt = "/soc/watchdog@30050030";
afe = "/soc/audio-controller@380d0000";
sound = "/soc/sound";
gpio_pwm_0 = "/soc/mfd@38010000";
gpio_pwm_1 = "/soc/mfd@38020000";
gpio_pwm_2 = "/soc/mfd@38030000";
gpio_3 = "/soc/mfd@38040000";
gpio_4 = "/soc/mfd@38050000";
gpio_5 = "/soc/mfd@38060000";
gpio_nonmap = "/soc/mfd@30020000";
isu0_gpio = "/soc/mfd@38070000";
isu1_gpio = "/soc/mfd@38080000";
isu2_gpio = "/soc/mfd@38090000";
isu3_gpio = "/soc/mfd@380A0000";
isu4_gpio = "/soc/mfd@380B0000";
isu5_gpio = "/soc/mfd@380C0000";
adc_gpio = "/soc/mfd@38000000";
i2s0_gpio = "/soc/mfd@380D0100";
i2s1_gpio = "/soc/mfd@380E0100";
fwd = "/soc/firewall@30000000";
rtc = "/soc/Real_Time_Clock@30090000";
auxadc = "/soc/adc@38000100";
mailbox = "/soc/mailbox@31000000";
ca7dma = "/soc/dma@31050000";
pluton = "/soc/pluton";
hifproc = "/soc/hif-proc@60000000";
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
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};
};
};
};
};
};
};
};
};
};
};
};
};
};
};