Popular repositories Loading

1. RISC-V-Single-Cycle-Core RISC-V-Single-Cycle-Core Public

   This repository consists of Load, Store and Read word data paths using a Single Cycle Core.

   Verilog 1

2. RISC-V-32I-5-stage-Pipeline-Core RISC-V-32I-5-stage-Pipeline-Core Public

   Implementation of 5 Stage 32I RISC V Pipeline Processor.

   Verilog 1

3. Bi-directional-Visitor-Counter-IOT Bi-directional-Visitor-Counter-IOT Public

   Get an IoT based project on Visitor Counter

   C++

4. Varunkumar0610 Varunkumar0610 Public

5. Sign-Language-Recognition-and-Text-and-Speech-conversion Sign-Language-Recognition-and-Text-and-Speech-conversion Public

   An ML model, working on sign language using Mediapipe and Kneighbors Classifier.

   Python

6. Digital-VLSI-SoC-Design-and-Planning-Nasscom-VSD Digital-VLSI-SoC-Design-and-Planning-Nasscom-VSD Public

   2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)