Logic_Gates.vcd

$date
	Wed Jan 01 17:44:41 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module logic_gates_tb $end
$var wire 1 ! xor_out $end
$var wire 1 " xnor_out $end
$var wire 1 # or_out $end
$var wire 1 $ not_out_b $end
$var wire 1 % not_out_a $end
$var wire 1 & nor_out $end
$var wire 1 ' nand_out $end
$var wire 1 ( and_out $end
$var reg 1 ) a $end
$var reg 1 * b $end
$scope module uut $end
$var wire 1 ) a $end
$var wire 1 * b $end
$var reg 1 ( and_out $end
$var reg 1 ' nand_out $end
$var reg 1 & nor_out $end
$var reg 1 % not_out_a $end
$var reg 1 $ not_out_b $end
$var reg 1 # or_out $end
$var reg 1 " xnor_out $end
$var reg 1 ! xor_out $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
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0#
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0!
$end
#10
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1!
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1#
1*
#20
1$
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#30
1"
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#40