v0.11.2

.github/workflows/Pipeline.yml

@@ -2,6 +2,10 @@ name: Unit Testing, Coverage Collection, Package, Release, Documentation and Pub
 
 on: [ push ]
 
+defaults:
+  run:
+    shell: bash
+
 jobs:
   UnitTesting:
     name: ${{ matrix.icon }} Unit Tests using Python ${{ matrix.python }}
@@ -22,7 +26,7 @@ jobs:
       python: ${{ env.PYTHON }}
 
     steps:
-      - name: Checkout repository
+      - name: ⏬ Checkout repository
         uses: actions/checkout@v2
 
       - name: 🐍 Setup Python ${{ matrix.python }}
@@ -35,7 +39,7 @@ jobs:
           python -m pip install --upgrade pip
           pip install -r tests/requirements.txt
 
-      - name: Run unit tests
+      - name: ☑ Run unit tests
         run: |
           python -m pytest -rA tests/unit
 
@@ -49,7 +53,7 @@ jobs:
       python: ${{ env.PYTHON }}
 
     steps:
-      - name: 🔋 Checkout repository
+      - name: ⏬ Checkout repository
         uses: actions/checkout@v2
 
       - name: 🐍 Setup Python ${{ env.PYTHON }}
@@ -87,7 +91,7 @@ jobs:
           coverage-reports: ./coverage.xml
 
   Release:
-    name: Release Page on GitHub
+    name: 📝 Create 'Release Page' on GitHub
     runs-on: ubuntu-latest
 
     if: startsWith(github.ref, 'refs/tags')
@@ -184,7 +188,7 @@ jobs:
           retention-days: 1
 
   PublishOnPyPI:
-    name: Publish to PyPI
+    name: 🚀 Publish to PyPI
     runs-on: ubuntu-latest
 
     if: startsWith(github.ref, 'refs/tags')
@@ -199,7 +203,7 @@ jobs:
       artifact: ${{ env.ARTIFACT }}
 
     steps:
-      - name: Download artifacts '${{ env.ARTIFACT }}' from 'Package' job
+      - name: 📥 Download artifacts '${{ env.ARTIFACT }}' from 'Package' job
         uses: actions/download-artifact@v2
         with:
           name: ${{ env.ARTIFACT }}
@@ -222,31 +226,87 @@ jobs:
         run: |
           twine upload dist/*
 
+  VerifyDocs:
+    name: 👍 Verify example snippets using Python 3.9
+    runs-on: ubuntu-latest
+
+    env:
+      PYTHON: 3.9
+    outputs:
+      python: ${{ env.PYTHON }}
+
+    steps:
+      - name: ⏬ Checkout repository
+        uses: actions/checkout@v2
+
+      - name: ⚙ Setup GHDL
+        uses: ghdl/setup-ghdl-ci@master
+
+      - name: 🐍 Setup Python
+        uses: actions/setup-python@v2
+        with:
+          python-version: ${{ env.PYTHON }}
+
+      - name: 🐍 Install dependencies
+        run: |
+          pip3 install git+https://github.com/ghdl/ghdl.git@$(ghdl version hash)
+
+      - name: ✂ Extract code snippet from README
+        shell: python
+        run: |
+          from pathlib import Path
+          import re
+
+          ROOT = Path('.')
+
+          with (ROOT / 'README.md').open('r') as rptr:
+              content = rptr.read()
+
+          m = re.search(r"```py(thon)?(?P<code>.*?)```", content, re.MULTILINE|re.DOTALL)
+
+          if m is None:
+              raise Exception("Regular expression did not find the example in the README!")
+
+          with (ROOT / 'tests/docs/example.py').open('w') as wptr:
+              wptr.write(m["code"])
+
+#      - name: Print example.py
+#        run: cat tests/docs/example.py
+
+      - name: ☑ Run example snippet
+        working-directory: tests/docs
+        run: |
+          python3 example.py
+
+
   BuildTheDocs:
     name: 📓 Run BuildTheDocs and publish to GH-Pages
     runs-on: ubuntu-latest
-    steps:
 
-    - name: Checkout repository
-      uses: actions/checkout@v2
+    needs:
+      - VerifyDocs
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@v2
 
-    - name: 🚢 Build documentation in 'pyVHDLModel/doc'
-      run: |
-        docker build -t vhdl/doc - <<-EOF
-        FROM btdi/sphinx:featured
-        RUN apk add -U --no-cache graphviz
-        EOF
+      - name: 🚢 Build container image 'vhdl/doc'
+        run: |
+          docker build -t vhdl/doc - <<-EOF
+          FROM btdi/sphinx:featured
+          RUN apk add -U --no-cache graphviz
+          EOF
 
-    - name: 🛳️ Unknown
-      uses: buildthedocs/btd@v0
-      with:
-        token: ${{ github.token }}
+      - name: 🛳️ Build documentation from './pyVHDLModel/doc'
+        uses: buildthedocs/btd@v0
+        with:
+          token: ${{ github.token }}
 
-    - name: Upload artifacts to GitHub Pages
-      uses: actions/upload-artifact@master
-      with:
-        name: doc
-        path: doc/_build/html
+      - name: 📤 Upload artifacts to GitHub Pages
+        uses: actions/upload-artifact@master
+        with:
+          name: doc
+          path: doc/_build/html
 
   ArtifactCleanUp:
     name: 🗑️ Artifact Cleanup
@@ -260,8 +320,8 @@ jobs:
       ARTIFACT: ${{ needs.Package.outputs.artifact }}
 
     steps:
-    - name: 🗑️ Delete all Artifacts
-      uses: geekyeggo/delete-artifact@v1
-      with:
-        name: |
-          ${{ env.ARTIFACT }}
+      - name: 🗑️ Delete all Artifacts
+        uses: geekyeggo/delete-artifact@v1
+        with:
+          name: |
+            ${{ env.ARTIFACT }}

README.md

@@ -57,21 +57,21 @@ from pyGHDL.dom.NonStandard import Design, Document
 sourceFile = Path("example.vhdl")
 
 design = Design()
-library = Design.GetLibrary("lib")
+library = design.GetLibrary("lib")
 document = Document(sourceFile)
 design.AddDocument(document, library)
 
 for entity in document.Entities:
-  print("{}".format(entity.Name))
+  print("{}".format(entity.Identifier))
   print("  generics:")
-  for generic in entity.Generics:
+  for generic in entity.GenericItems:
     print("  - {} : {!s} {}".format(
-      generic.Identifier, generic.Mode, generic.SubTypeIndication)
+      generic.Identifier, generic.Mode, generic.Subtype)
     )
   print("  ports:")
-  for port in entity.Ports:
+  for port in entity.PortItems:
     print("  - {} : {!s} {}".format(
-      port.Identifier, port.Mode, port.SubTypeIndication)
+      port.Identifier, port.Mode, port.Subtype)
     )
 ```
 

doc/conf.py

@@ -37,7 +37,7 @@ def _LatestTagName():
 
 # The full version, including alpha/beta/rc tags
 version = "0.11"     # The short X.Y version.
-release = "0.11.1"   # The full version, including alpha/beta/rc tags.
+release = "0.11.2"   # The full version, including alpha/beta/rc tags.
 try:
 	if _IsUnderGitControl:
 		latestTagName = _LatestTagName()[1:]		# remove prefix "v"

doc/index.rst

@@ -57,6 +57,22 @@ Use Cases
 News
 ****
 
+.. only:: html
+
+   Jul. 2021 - First adoption and enhancements
+   ===========================================
+
+.. only:: latex
+
+   .. rubric:: First adoption and enhancements
+
+* `GHDL's <https://github.com/ghdl/ghdl>`__ is the first big adopter with `pyGHDL.dom <https://ghdl.github.io/ghdl/pyGHDL/pyGHDL.dom.html>`__
+  to generate a network of instantiated classes derived from ``pyVHDLModel``. |br|
+  It uses `pyGHDL <https://ghdl.github.io/ghdl/using/pyGHDL/index.html>`__ as a backend (GHDL build as shared object and
+  loaded into CPython via C-binding API (``ctypes``).
+* ...
+
+
 .. only:: html
 
    Jun. 2021 - Model and documentation enhancements

pyVHDLModel/VHDLModel.py

@@ -1312,7 +1312,7 @@ class AscendingRangeExpression(RangeExpression):
 
 @export
 class DescendingRangeExpression(RangeExpression):
-	_direction = Direction.To
+	_direction = Direction.DownTo
 	_FORMAT = ("", " downto ", "")
 
 

pyVHDLModel/__init__.py

@@ -40,4 +40,4 @@
 :copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany
 :license: Apache License, Version 2.0
 """
-__version__ = "0.11.1"
+__version__ = "0.11.2"

setup.py

@@ -53,7 +53,7 @@
 # Assemble all package information
 setuptools_setup(
 	name=projectName,
-	version="0.11.1",
+	version="0.11.2",
 
 	author="Patrick Lehmann",
 	author_email="Paebbels@gmail.com",

tests/docs/example.vhdl

@@ -0,0 +1,32 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity entity_1 is
+	generic (
+		FREQ : real     := (100.0 * 1024.0 * 1024.0);
+		BITS : positive := 8
+	);
+	port (
+	  Clock: in  std_logic;
+	  Reset: in  std_logic := '0';
+	  Q:     out std_logic_vector(BITS - 1 downto 0)
+	);
+end entity entity_1;
+
+architecture behav of entity_1 is
+	signal Reset_n : std_logic;
+begin
+	Reset_n <= (not Reset);
+
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if Reset_n = '0' then
+				Q <= (others => '0');
+			else
+				Q <= std_logic_vector(unsigned(Q) + 1);
+			end if;
+		end if;
+	end process;
+end architecture behav;