From e93b88d348b556bbecbd3dbb0ae13c73fdb19d20 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 09:20:31 +0200 Subject: [PATCH 1/9] Bump version to v0.11.1. --- doc/conf.py | 2 +- pyVHDLModel/__init__.py | 2 +- setup.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/conf.py b/doc/conf.py index 7a403c5a4..be24127f6 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -37,7 +37,7 @@ def _LatestTagName(): # The full version, including alpha/beta/rc tags version = "0.11" # The short X.Y version. -release = "0.11.0" # The full version, including alpha/beta/rc tags. +release = "0.11.1" # The full version, including alpha/beta/rc tags. try: if _IsUnderGitControl: latestTagName = _LatestTagName()[1:] # remove prefix "v" diff --git a/pyVHDLModel/__init__.py b/pyVHDLModel/__init__.py index c2bc9fffa..b9cdeba5d 100644 --- a/pyVHDLModel/__init__.py +++ b/pyVHDLModel/__init__.py @@ -40,4 +40,4 @@ :copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany :license: Apache License, Version 2.0 """ -__version__ = "0.11.0" +__version__ = "0.11.1" diff --git a/setup.py b/setup.py index 458532c76..f8249e037 100644 --- a/setup.py +++ b/setup.py @@ -53,7 +53,7 @@ # Assemble all package information setuptools_setup( name=projectName, - version="0.11.0", + version="0.11.1", author="Patrick Lehmann", author_email="Paebbels@gmail.com", From 86e345599697f097615a113d3ad876f081780abf Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 11:56:21 +0200 Subject: [PATCH 2/9] Prepared for PSL. --- pyVHDLModel/PSLModel.py | 81 ++++++++++++++++++++++++++++++++++++++++ pyVHDLModel/VHDLModel.py | 39 +++++++++++-------- 2 files changed, 104 insertions(+), 16 deletions(-) create mode 100644 pyVHDLModel/PSLModel.py diff --git a/pyVHDLModel/PSLModel.py b/pyVHDLModel/PSLModel.py new file mode 100644 index 000000000..14cef8037 --- /dev/null +++ b/pyVHDLModel/PSLModel.py @@ -0,0 +1,81 @@ +# ============================================================================= +# __ ___ _ ____ _ __ __ _ _ +# _ __ _ \ \ / / | | | _ \| | | \/ | ___ __| | ___| | +# | '_ \| | | \ \ / /| |_| | | | | | | |\/| |/ _ \ / _` |/ _ \ | +# | |_) | |_| |\ V / | _ | |_| | |___| | | | (_) | (_| | __/ | +# | .__/ \__, | \_/ |_| |_|____/|_____|_| |_|\___/ \__,_|\___|_| +# |_| |___/ +# ============================================================================== +# Authors: Patrick Lehmann +# +# Python module: An abstract PSL language model. +# +# Description: +# ------------------------------------ +# TODO: +# +# License: +# ============================================================================== +# Copyright 2017-2021 Patrick Lehmann - Boetzingen, Germany +# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 +# ============================================================================== +# +""" +This module contains a document language model for PSL. + +:copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany +:license: Apache License, Version 2.0 +""" +# load dependencies +from pydecor.decorators import export + +from pyVHDLModel.VHDLModel import PrimaryUnit, ModelEntity + + +__all__ = [] + +@export +class PSLPrimaryUnit(PrimaryUnit): + pass + + +@export +class PSLEntity(ModelEntity): + pass + + +@export +class VerificationUnit(PSLPrimaryUnit): + def __init__(self, identifier: str): + super().__init__(identifier) + + +@export +class VerificationProperty(PSLPrimaryUnit): + def __init__(self, identifier: str): + super().__init__(identifier) + + +@export +class VerificationMode(PSLPrimaryUnit): + def __init__(self, identifier: str): + super().__init__(identifier) + + +@export +class DefaultClock(PSLEntity): + pass diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 2d336cb8f..ba442d273 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -35,10 +35,10 @@ # ============================================================================== # """ +This module contains a document language model for VHDL. + :copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany :license: Apache License, Version 2.0 - -This module contains a document language model for VHDL. """ # load dependencies from enum import Enum, unique, IntEnum @@ -697,24 +697,26 @@ class Document(ModelEntity): A ``Document`` represents a sourcefile. It contains primary and secondary design units. """ - _path: Path #: path to the document. ``None`` if virtual document. - _contexts: List['Context'] #: List of all contexts defined in a document. - _configurations: List['Configuration'] #: List of all configurations defined in a document. - _entities: List['Entity'] #: List of all entities defined in a document. - _architectures: List['Architecture'] #: List of all architectures defined in a document. - _packages: List['Package'] #: List of all packages defined in a document. - _packageBodies: List['PackageBody'] #: List of all package bodies defined in a document. + _path: Path #: path to the document. ``None`` if virtual document. + _contexts: List['Context'] #: List of all contexts defined in a document. + _configurations: List['Configuration'] #: List of all configurations defined in a document. + _verificationUnits: List['VerificationUnit'] #: List of all PSL verification units defined in a document. + _entities: List['Entity'] #: List of all entities defined in a document. + _architectures: List['Architecture'] #: List of all architectures defined in a document. + _packages: List['Package'] #: List of all packages defined in a document. + _packageBodies: List['PackageBody'] #: List of all package bodies defined in a document. def __init__(self, path: Path): super().__init__() - self._path = path - self._contexts = [] - self._configurations = [] - self._entities = [] - self._architectures = [] - self._packages = [] - self._packageBodies = [] + self._path = path + self._contexts = [] + self._configurations = [] + self._verificationUnits = [] + self._entities = [] + self._architectures = [] + self._packages = [] + self._packageBodies = [] @property def Path(self) -> Path: @@ -730,6 +732,11 @@ def Configurations(self) -> List['Configuration']: """Returns a list of all configuration declarations found in this document.""" return self._configurations + @property + def VerificationUnits(self) -> List['VerificationUnit']: + """Returns a list of all configuration declarations found in this document.""" + return self._verificationUnits + @property def Entities(self) -> List['Entity']: """Returns a list of all entity declarations found in this document.""" From 9d1e17c943e50def488c1d88191a32d005b92a10 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 11:57:36 +0200 Subject: [PATCH 3/9] Added allocations. --- pyVHDLModel/VHDLModel.py | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index ba442d273..3869a0e3f 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1569,6 +1569,41 @@ class FunctionCall(BaseExpression): pass +@export +class Allocation(BaseExpression): + pass + + +@export +class SubtypeAllocation(Allocation): + _subtype: Symbol + + def __init__(self, subtype: Symbol): + self._subtype = subtype + + @property + def Subtype(self) -> Symbol: + return self._subtype + + def __str__(self) -> str: + return "new {subtype!s}".format(subtype=self._subtype) + + +@export +class QualifiedExpressionAllocation(Allocation): + _qualifiedExpression: QualifiedExpression + + def __init__(self, qualifiedExpression: QualifiedExpression): + self._qualifiedExpression = qualifiedExpression + + @property + def QualifiedExpression(self) -> QualifiedExpression: + return self._qualifiedExpression + + def __str__(self) -> str: + return "new {expr!s}".format(expr=self._qualifiedExpression) + + @export class AggregateElement(ModelEntity): """ From d501f6af15fca21d62c62e26edecd279d4ce6018 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 11:58:16 +0200 Subject: [PATCH 4/9] Unified '[sS]ubType' to '[sS]ubtype'. --- pyVHDLModel/VHDLModel.py | 148 +++++++++++++++++++-------------------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 3869a0e3f..08409fc78 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -67,7 +67,7 @@ class Protocol: ConfigurationOrSymbol = Union['Configuration', 'ConfigurationSymbol'] ContextOrSymbol = Union['Context', 'ContextSymbol'] -SubTypeOrSymbol = Union['SubType', 'SubTypeSymbol'] +SubtypeOrSymbol = Union['Subtype', 'SubtypeSymbol'] ConstantOrSymbol = Union['Constant', 'ConstantSymbol'] VariableOrSymbol = Union['Variable', 'VariableSymbol'] @@ -192,7 +192,7 @@ class PossibleReference(IntEnum): Configuration = 2**5 Context = 2**6 Type = 2**7 - SubType = 2**8 + Subtype = 2**8 ScalarType = 2**9 ArrayType = 2**10 RecordType = 2**11 @@ -497,30 +497,30 @@ def Context(self, value: 'Context') -> None: @export -class SubTypeSymbol(Symbol): +class SubtypeSymbol(Symbol): def __init__(self, symbolName: Name, possibleReferences: PossibleReference): - super().__init__(symbolName, PossibleReference.SubType + PossibleReference.TypeAttribute + possibleReferences) + super().__init__(symbolName, PossibleReference.Subtype + PossibleReference.TypeAttribute + possibleReferences) @property - def SubType(self) -> 'SubType': + def Subtype(self) -> 'Subtype': return self._reference - @SubType.setter - def SubType(self, value: 'SubType') -> None: + @Subtype.setter + def Subtype(self, value: 'Subtype') -> None: self._reference = value @export -class SimpleSubTypeSymbol(SubTypeSymbol): - def __init__(self, subTypeName: Name): - super().__init__(subTypeName, PossibleReference.ScalarType) +class SimpleSubtypeSymbol(SubtypeSymbol): + def __init__(self, subtypeName: Name): + super().__init__(subtypeName, PossibleReference.ScalarType) @export -class ConstrainedScalarSubTypeSymbol(SubTypeSymbol): +class ConstrainedScalarSubtypeSymbol(SubtypeSymbol): _range: 'Range' - def __init__(self, subTypeName: Name, rng: 'Range' = None): - super().__init__(subTypeName, PossibleReference.ArrayType) + def __init__(self, subtypeName: Name, rng: 'Range' = None): + super().__init__(subtypeName, PossibleReference.ArrayType) self._range = rng @property @@ -529,12 +529,12 @@ def Range(self) -> 'Range': @export -class ConstrainedCompositeSubTypeSymbol(SubTypeSymbol): +class ConstrainedCompositeSubtypeSymbol(SubtypeSymbol): _constraints: List[Constraint] - def __init__(self, subTypeName: Name, constraints: List[Constraint] = None): - super().__init__(subTypeName, PossibleReference.Unknown) - self._subType = None + def __init__(self, subtypeName: Name, constraints: List[Constraint] = None): + super().__init__(subtypeName, PossibleReference.Unknown) + self._subtype = None self._constraints = constraints @property @@ -795,8 +795,8 @@ class FullType(BaseType): @export -class SubType(BaseType): - _type: 'SubType' +class Subtype(BaseType): + _type: 'Subtype' _baseType: BaseType _range: 'Range' _resolutionFunction: 'Function' @@ -805,7 +805,7 @@ def __init__(self, identifier: str): super().__init__(identifier) @property - def Type(self) -> 'SubType': + def Type(self) -> 'Subtype': return self._type @property @@ -907,28 +907,28 @@ def Methods(self) -> List[Union['Procedure', 'Function']]: @export class AccessType(FullType): - _designatedSubType: SubTypeOrSymbol + _designatedSubtype: SubtypeOrSymbol - def __init__(self, identifier: str, designatedSubType: SubTypeOrSymbol): + def __init__(self, identifier: str, designatedSubtype: SubtypeOrSymbol): super().__init__(identifier) - self._designatedSubType = designatedSubType + self._designatedSubtype = designatedSubtype @property def DesignatedSubtype(self): - return self._designatedSubType + return self._designatedSubtype @export class FileType(FullType): - _designatedSubType: SubTypeOrSymbol + _designatedSubtype: SubtypeOrSymbol - def __init__(self, identifier: str, designatedSubType: SubTypeOrSymbol): + def __init__(self, identifier: str, designatedSubtype: SubtypeOrSymbol): super().__init__(identifier) - self._designatedSubType = designatedSubType + self._designatedSubtype = designatedSubtype @property def DesignatedSubtype(self): - return self._designatedSubType + return self._designatedSubtype @export @@ -980,9 +980,9 @@ def SecondaryUnits(self) -> List[Tuple[str, 'PhysicalIntegerLiteral']]: @export class ArrayType(CompositeType): _dimensions: List['Range'] - _elementType: SubType + _elementType: Subtype - def __init__(self, identifier: str, indices: List, elementSubType: SubTypeOrSymbol): + def __init__(self, identifier: str, indices: List, elementSubtype: SubtypeOrSymbol): super().__init__(identifier) self._dimensions = [] @@ -992,28 +992,28 @@ def Dimensions(self) -> List['Range']: return self._dimensions @property - def ElementType(self) -> SubType: + def ElementType(self) -> Subtype: return self._elementType @export class RecordTypeElement(ModelEntity): _identifier: str - _subType: SubTypeOrSymbol + _subtype: SubtypeOrSymbol - def __init__(self, identifier: str, subType: SubTypeOrSymbol): + def __init__(self, identifier: str, subtype: SubtypeOrSymbol): super().__init__() self._identifier = identifier - self._subType = subType + self._subtype = subtype @property def Identifier(self) -> str: return self._identifier @property - def SubType(self) -> SubTypeOrSymbol: - return self._subType + def Subtype(self) -> SubtypeOrSymbol: + return self._subtype @export @@ -1498,20 +1498,20 @@ class RotateLeftExpression(RotateExpression): @export class QualifiedExpression(BaseExpression, ParenthesisExpression): _operand: Expression - _subtype: SubTypeOrSymbol + _subtype: SubtypeOrSymbol - def __init__(self, subType: SubTypeOrSymbol, operand: Expression): + def __init__(self, subtype: SubtypeOrSymbol, operand: Expression): super().__init__() self._operand = operand - self._subtype = subType + self._subtype = subtype @property def Operand(self): return self._operand @property - def SubTyped(self): + def Subtyped(self): return self._subtype def __str__(self) -> str: @@ -1761,17 +1761,17 @@ class RangeSubtype(BaseConstraint): @export class Obj(ModelEntity, NamedEntity): - _subType: SubTypeOrSymbol + _subtype: SubtypeOrSymbol - def __init__(self, identifier: str, subType: SubTypeOrSymbol): + def __init__(self, identifier: str, subtype: SubtypeOrSymbol): super().__init__() NamedEntity.__init__(self, identifier) - self._subType = subType + self._subtype = subtype @property - def SubType(self) -> SubTypeOrSymbol: - return self._subType + def Subtype(self) -> SubtypeOrSymbol: + return self._subtype @export @@ -1797,8 +1797,8 @@ class BaseConstant(Obj): @export class Constant(BaseConstant, WithDefaultExpressionMixin): - def __init__(self, identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType) + def __init__(self, identifier: str, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype) WithDefaultExpressionMixin.__init__(self, defaultExpression) @@ -1806,8 +1806,8 @@ def __init__(self, identifier: str, subType: SubTypeOrSymbol, defaultExpression: class DeferredConstant(BaseConstant): _constantReference: Constant - def __init__(self, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) @property def ConstantReference(self) -> Constant: @@ -1816,8 +1816,8 @@ def ConstantReference(self) -> Constant: @export class Variable(Obj, WithDefaultExpressionMixin): - def __init__(self, identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType) + def __init__(self, identifier: str, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype) WithDefaultExpressionMixin.__init__(self, defaultExpression) @@ -1828,8 +1828,8 @@ class SharedVariable(Obj): @export class Signal(Obj, WithDefaultExpressionMixin): - def __init__(self, identifier: str, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super(Signal, self).__init__(identifier, subType) + def __init__(self, identifier: str, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super(Signal, self).__init__(identifier, subtype) WithDefaultExpressionMixin.__init__(self, defaultExpression) @@ -1883,14 +1883,14 @@ class Procedure(SubProgramm): @export class Function(SubProgramm): - _returnType: SubType + _returnType: Subtype def __init__(self, identifier: str, isPure: bool = True): super().__init__(identifier) self._isPure = isPure @property - def ReturnType(self) -> SubType: + def ReturnType(self) -> Subtype: return self._returnType @@ -1925,17 +1925,17 @@ def __init__(self, identifier: str, protectedType: ProtectedType): @export class Attribute(ModelEntity, NamedEntity): - _subType: SubTypeOrSymbol + _subtype: SubtypeOrSymbol - def __init__(self, identifier: str, subType: SubTypeOrSymbol): + def __init__(self, identifier: str, subtype: SubtypeOrSymbol): super().__init__() NamedEntity.__init__(self, identifier) - self._subType = subType + self._subtype = subtype @property - def SubType(self): - return self._subType + def Subtype(self): + return self._subtype @export @@ -2006,8 +2006,8 @@ class ParameterInterfaceItem(InterfaceItem): @export class GenericConstantInterfaceItem(Constant, GenericInterfaceItem, InterfaceItemWithMode): - def __init__(self, identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType, defaultExpression) + def __init__(self, identifier: str, mode: Mode, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype, defaultExpression) GenericInterfaceItem.__init__(self) InterfaceItemWithMode.__init__(self, mode) @@ -2047,46 +2047,46 @@ def __init__(self, identifier: str): @export class PortSignalInterfaceItem(Signal, PortInterfaceItem): - def __init__(self, identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType, defaultExpression) + def __init__(self, identifier: str, mode: Mode, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype, defaultExpression) PortInterfaceItem.__init__(self, mode) @export class ParameterConstantInterfaceItem(Constant, ParameterInterfaceItem, InterfaceItemWithMode): - def __init__(self, identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType, defaultExpression) + def __init__(self, identifier: str, mode: Mode, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype, defaultExpression) ParameterInterfaceItem.__init__(self) InterfaceItemWithMode.__init__(self, mode) @export class ParameterVariableInterfaceItem(Variable, ParameterInterfaceItem, InterfaceItemWithMode): - def __init__(self, identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType, defaultExpression) + def __init__(self, identifier: str, mode: Mode, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype, defaultExpression) ParameterInterfaceItem.__init__(self) InterfaceItemWithMode.__init__(self, mode) @export class ParameterSignalInterfaceItem(Signal, ParameterInterfaceItem, InterfaceItemWithMode): - def __init__(self, identifier: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression = None): - super().__init__(identifier, subType, defaultExpression) + def __init__(self, identifier: str, mode: Mode, subtype: SubtypeOrSymbol, defaultExpression: Expression = None): + super().__init__(identifier, subtype, defaultExpression) ParameterInterfaceItem.__init__(self) InterfaceItemWithMode.__init__(self, mode) @export class ParameterFileInterfaceItem(File, ParameterInterfaceItem): - def __init__(self, identifier: str, subType: SubTypeOrSymbol): - super().__init__(identifier, subType) + def __init__(self, identifier: str, subtype: SubtypeOrSymbol): + super().__init__(identifier, subtype) ParameterInterfaceItem.__init__(self) # class GenericItem(ModelEntity): # def __init__(self): # super().__init__() # self._name = None -# self._subType = None +# self._subtype = None # self._init = None # # @@ -2094,7 +2094,7 @@ def __init__(self, identifier: str, subType: SubTypeOrSymbol): # def __init__(self): # super().__init__() # self._name = None -# self._subType = None +# self._subtype = None # self._init = None # self._mode = None # self._class = None From 0d823ed53330f89bb29afbdf6783cf82725faab9 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:13:06 +0200 Subject: [PATCH 5/9] Reworked RangedScalarTypes. --- pyVHDLModel/VHDLModel.py | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 08409fc78..bc58f32c2 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -839,16 +839,17 @@ class RangedScalarType(ScalarType): A ``RangedScalarType`` is a base-class for all scalar types with a range. """ - _leftBound: Expression + _range: Union['Range', Name] + _leftBound: Expression _rightBound: Expression - @property - def LeftBound(self) -> Expression: - return self._leftBound + def __init__(self, identifier: str, rng: Union['Range', Name]): + super().__init__(identifier) + self._range = rng @property - def RightBound(self) -> Expression: - return self._rightBound + def Range(self) -> Union['Range', Name]: + return self._range @export @@ -947,14 +948,14 @@ def Literals(self) -> List['EnumerationLiteral']: @export class IntegerType(RangedScalarType, NumericType, DiscreteType): - def __init__(self, identifier: str): - super().__init__(identifier) + def __init__(self, identifier: str, rng: Union['Range', Name]): + super().__init__(identifier, rng) @export class RealType(RangedScalarType, NumericType): - def __init__(self, identifier: str): - super().__init__(identifier) + def __init__(self, identifier: str, rng: Union['Range', Name]): + super().__init__(identifier, rng) @export @@ -962,8 +963,8 @@ class PhysicalType(RangedScalarType, NumericType): _primaryUnit: str _secondaryUnits: List[Tuple[str, 'PhysicalIntegerLiteral']] - def __init__(self, identifier: str, primaryUnit: str, units: List[Tuple[str, 'PhysicalIntegerLiteral']]): - super().__init__(identifier) + def __init__(self, identifier: str, rng: Union['Range', Name], primaryUnit: str, units: List[Tuple[str, 'PhysicalIntegerLiteral']]): + super().__init__(identifier, rng) self._primaryUnit = primaryUnit self._secondaryUnits = units From f8626b790e31d301df42c4e65e73dc5e1bc6bb7f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:13:20 +0200 Subject: [PATCH 6/9] Added matching operators. --- pyVHDLModel/VHDLModel.py | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index bc58f32c2..c8ad1bc50 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1444,6 +1444,41 @@ class LessEqualExpression(RelationalExpression): _FORMAT = ("", " <= ", "") +@export +class MatchingRelationalExpression(RelationalExpression): + pass + + +@export +class MatchingEqualExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?= ", "") + + +@export +class MatchingUnequalExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?/= ", "") + + +@export +class MatchingGreaterThanExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?> ", "") + + +@export +class MatchingGreaterEqualExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?>= ", "") + + +@export +class MatchingLessThanExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?< ", "") + + +@export +class MatchingLessEqualExpression(MatchingRelationalExpression): + _FORMAT = ("", " ?<= ", "") + + @export class ShiftExpression(BinaryExpression): """ From c390617fd7f55f6842beb77a1bff76d517c08132 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 10:37:43 +0200 Subject: [PATCH 7/9] Simplified test code. --- doc/LanguageModel/DesignUnits.rst | 8 +-- doc/LanguageModel/Miscellaneous.rst | 12 ++--- pyVHDLModel/VHDLModel.py | 6 +++ tests/unit/Instantiate.py | 76 ++++++++++++++--------------- 4 files changed, 54 insertions(+), 48 deletions(-) diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index b265193ab..e9ab04d13 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -80,7 +80,7 @@ types). An entity's list of statements is called body items. # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryStatement]: @property def PackageReferences(self) -> List[UseClause]: @@ -128,7 +128,7 @@ Package # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryStatement]: @property def PackageReferences(self) -> List[UseClause]: @@ -175,7 +175,7 @@ Architeture # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryStatement]: @property def PackageReferences(self) -> List[UseClause]: @@ -220,7 +220,7 @@ Package Body # inherited from MixinDesignUnitWithContext @property - def LibraryReferences(self) -> List[Library]: + def LibraryReferences(self) -> List[LibraryStatement]: @property def PackageReferences(self) -> List[UseClause]: diff --git a/doc/LanguageModel/Miscellaneous.rst b/doc/LanguageModel/Miscellaneous.rst index f58518b43..25764c60d 100644 --- a/doc/LanguageModel/Miscellaneous.rst +++ b/doc/LanguageModel/Miscellaneous.rst @@ -36,7 +36,7 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a # from Design @property - def Libraries(self) -> List[Library]: + def Libraries(self) -> List[LibraryStatement]: @property def Documents(self) -> List[Document]: @@ -45,24 +45,24 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a .. _vhdlmodel-library: -Library -======= +LibraryStatement +================ A library contains multiple *design units*. Each design unit listed in a library is a *primary* design unit like: ``configuration``, ``entity``, ``package`` or ``context``. -**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Library`: +**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.LibraryStatement`: .. code-block:: Python @export - class Library(ModelEntity): + class LibraryStatement(ModelEntity): # inherited from ModelEntity @property def Parent(self) -> ModelEntity: - # from Library + # from LibraryStatement @property def Contexts(self) -> List[Context]: diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index c8ad1bc50..13692d71a 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1758,6 +1758,12 @@ class Range(ModelEntity): _rightBound: Expression _direction: Direction + def __init__(self, leftBound: Expression, rightBound: Expression, direction: Direction): + super().__init__() + self._leftBound = leftBound + self._rightBound = rightBound + self._direction = direction + @property def LeftBound(self) -> Expression: return self._leftBound diff --git a/tests/unit/Instantiate.py b/tests/unit/Instantiate.py index 72fc91905..4630b168b 100644 --- a/tests/unit/Instantiate.py +++ b/tests/unit/Instantiate.py @@ -37,9 +37,9 @@ from pathlib import Path from unittest import TestCase -from pyVHDLModel.VHDLModel import Design, Library, Document +from pyVHDLModel.VHDLModel import Design, Library, Document, Subtype, Range, IntegerLiteral, Direction, FloatingPointLiteral from pyVHDLModel.VHDLModel import Entity, Architecture, PackageBody, Package, Configuration, Context -from pyVHDLModel.VHDLModel import SubType, IntegerType, RealType, ArrayType, RecordType +from pyVHDLModel.VHDLModel import IntegerType, RealType, ArrayType, RecordType if __name__ == "__main__": @@ -53,103 +53,103 @@ def test_Design(self): design = Design() self.assertIsNotNone(design) - self.assertTrue(len(design.Documents) == 0) - self.assertTrue(len(design.Libraries) == 0) + self.assertEqual(len(design.Documents), 0) + self.assertEqual(len(design.Libraries), 0) def test_Library(self): library = Library("lib_1") self.assertIsNotNone(library) - self.assertTrue(library.Identifier == "lib_1") - self.assertTrue(len(library.Contexts) == 0) - self.assertTrue(len(library.Entities) == 0) - self.assertTrue(len(library.Packages) == 0) - self.assertTrue(len(library.Configurations) == 0) + self.assertEqual(library.Identifier, "lib_1") + self.assertEqual(len(library.Contexts), 0) + self.assertEqual(len(library.Entities), 0) + self.assertEqual(len(library.Packages), 0) + self.assertEqual(len(library.Configurations), 0) def test_Document(self): path = Path("tests.vhdl") document = Document(path) self.assertIsNotNone(document) - self.assertTrue(document.Path == path) - self.assertTrue(len(document.Entities) == 0) - self.assertTrue(len(document.Architectures) == 0) - self.assertTrue(len(document.Packages) == 0) - self.assertTrue(len(document.PackageBodies) == 0) - self.assertTrue(len(document.Contexts) == 0) - self.assertTrue(len(document.Configurations) == 0) + self.assertEqual(document.Path, path) + self.assertEqual(len(document.Entities), 0) + self.assertEqual(len(document.Architectures), 0) + self.assertEqual(len(document.Packages), 0) + self.assertEqual(len(document.PackageBodies), 0) + self.assertEqual(len(document.Contexts), 0) + self.assertEqual(len(document.Configurations), 0) def test_Entity(self): entity = Entity("entity_1") self.assertIsNotNone(entity) - self.assertTrue(entity.Identifier == "entity_1") - self.assertTrue(len(entity.GenericItems) == 0) - self.assertTrue(len(entity.PortItems) == 0) - self.assertTrue(len(entity.DeclaredItems) == 0) - self.assertTrue(len(entity.BodyItems) == 0) + self.assertEqual(entity.Identifier, "entity_1") + self.assertEqual(len(entity.GenericItems), 0) + self.assertEqual(len(entity.PortItems), 0) + self.assertEqual(len(entity.DeclaredItems), 0) + self.assertEqual(len(entity.BodyItems), 0) def test_Architecture(self): entity = Entity("entity_1") architecture = Architecture("arch_1", entity) self.assertIsNotNone(architecture) - self.assertTrue(architecture.Identifier == "arch_1") - self.assertTrue(len(architecture.DeclaredItems) == 0) - self.assertTrue(len(architecture.BodyItems) == 0) + self.assertEqual(architecture.Identifier, "arch_1") + self.assertEqual(len(architecture.DeclaredItems), 0) + self.assertEqual(len(architecture.BodyItems), 0) def test_Package(self): package = Package("pack_1") self.assertIsNotNone(package) - self.assertTrue(package.Identifier == "pack_1") - self.assertTrue(len(package.DeclaredItems) == 0) + self.assertEqual(package.Identifier, "pack_1") + self.assertEqual(len(package.DeclaredItems), 0) def test_PackageBody(self): packageBody = PackageBody("pack_1") self.assertIsNotNone(packageBody) - self.assertTrue(packageBody.Identifier == "pack_1") - self.assertTrue(len(packageBody.DeclaredItems) == 0) + self.assertEqual(packageBody.Identifier, "pack_1") + self.assertEqual(len(packageBody.DeclaredItems), 0) def test_Context(self): context = Context("ctx_1") self.assertIsNotNone(context) - self.assertTrue(context.Identifier == "ctx_1") + self.assertEqual(context.Identifier, "ctx_1") def test_Configuration(self): configuration = Configuration("conf_1") self.assertIsNotNone(configuration) - self.assertTrue(configuration.Identifier == "conf_1") + self.assertEqual(configuration.Identifier, "conf_1") def test_SubType(self): - subtype = SubType("bit") + subtype = Subtype("bit") self.assertIsNotNone(subtype) - self.assertTrue(subtype.Identifier == "bit") + self.assertEqual(subtype.Identifier, "bit") def test_Integer(self): - integer = IntegerType("integer") + integer = IntegerType("integer", Range(IntegerLiteral(0), IntegerLiteral(7), Direction.To)) self.assertIsNotNone(integer) - self.assertTrue(integer.Identifier == "integer") + self.assertEqual(integer.Identifier, "integer") def test_Real(self): - real = RealType("real") + real = RealType("real", Range(FloatingPointLiteral(0.0), FloatingPointLiteral(1.0), Direction.To)) self.assertIsNotNone(real) - self.assertTrue(real.Identifier == "real") + self.assertEqual(real.Identifier, "real") def test_Array(self): array = ArrayType("bit_vector", [], None) self.assertIsNotNone(array) - self.assertTrue(array.Identifier == "bit_vector") + self.assertEqual(array.Identifier, "bit_vector") def test_Record(self): record = RecordType("range_record") self.assertIsNotNone(record) - self.assertTrue(record.Identifier == "range_record") + self.assertEqual(record.Identifier, "range_record") From b1159dcfdc99a92f1d2718f8471fe566101b31e9 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 12:16:27 +0200 Subject: [PATCH 8/9] Exchanged sides in asserts to the understanding of pytests actual vs. expected order. --- tests/unit/Instantiate.py | 70 +++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/tests/unit/Instantiate.py b/tests/unit/Instantiate.py index 4630b168b..8750f0ce1 100644 --- a/tests/unit/Instantiate.py +++ b/tests/unit/Instantiate.py @@ -53,103 +53,103 @@ def test_Design(self): design = Design() self.assertIsNotNone(design) - self.assertEqual(len(design.Documents), 0) - self.assertEqual(len(design.Libraries), 0) + self.assertEqual(0, len(design.Documents)) + self.assertEqual(0, len(design.Libraries)) def test_Library(self): library = Library("lib_1") self.assertIsNotNone(library) - self.assertEqual(library.Identifier, "lib_1") - self.assertEqual(len(library.Contexts), 0) - self.assertEqual(len(library.Entities), 0) - self.assertEqual(len(library.Packages), 0) - self.assertEqual(len(library.Configurations), 0) + self.assertEqual("lib_1", library.Identifier) + self.assertEqual(0, len(library.Contexts)) + self.assertEqual(0, len(library.Entities)) + self.assertEqual(0, len(library.Packages)) + self.assertEqual(0, len(library.Configurations)) def test_Document(self): path = Path("tests.vhdl") document = Document(path) self.assertIsNotNone(document) - self.assertEqual(document.Path, path) - self.assertEqual(len(document.Entities), 0) - self.assertEqual(len(document.Architectures), 0) - self.assertEqual(len(document.Packages), 0) - self.assertEqual(len(document.PackageBodies), 0) - self.assertEqual(len(document.Contexts), 0) - self.assertEqual(len(document.Configurations), 0) + self.assertEqual(path, document.Path) + self.assertEqual(0, len(document.Entities)) + self.assertEqual(0, len(document.Architectures)) + self.assertEqual(0, len(document.Packages)) + self.assertEqual(0, len(document.PackageBodies)) + self.assertEqual(0, len(document.Contexts)) + self.assertEqual(0, len(document.Configurations)) def test_Entity(self): entity = Entity("entity_1") self.assertIsNotNone(entity) - self.assertEqual(entity.Identifier, "entity_1") - self.assertEqual(len(entity.GenericItems), 0) - self.assertEqual(len(entity.PortItems), 0) - self.assertEqual(len(entity.DeclaredItems), 0) - self.assertEqual(len(entity.BodyItems), 0) + self.assertEqual("entity_1", entity.Identifier) + self.assertEqual(0, len(entity.GenericItems)) + self.assertEqual(0, len(entity.PortItems)) + self.assertEqual(0, len(entity.DeclaredItems)) + self.assertEqual(0, len(entity.BodyItems)) def test_Architecture(self): entity = Entity("entity_1") architecture = Architecture("arch_1", entity) self.assertIsNotNone(architecture) - self.assertEqual(architecture.Identifier, "arch_1") - self.assertEqual(len(architecture.DeclaredItems), 0) - self.assertEqual(len(architecture.BodyItems), 0) + self.assertEqual("arch_1", architecture.Identifier) + self.assertEqual(0, len(architecture.DeclaredItems)) + self.assertEqual(0, len(architecture.BodyItems)) def test_Package(self): package = Package("pack_1") self.assertIsNotNone(package) - self.assertEqual(package.Identifier, "pack_1") - self.assertEqual(len(package.DeclaredItems), 0) + self.assertEqual("pack_1", package.Identifier) + self.assertEqual(0, len(package.DeclaredItems)) def test_PackageBody(self): packageBody = PackageBody("pack_1") self.assertIsNotNone(packageBody) - self.assertEqual(packageBody.Identifier, "pack_1") - self.assertEqual(len(packageBody.DeclaredItems), 0) + self.assertEqual("pack_1", packageBody.Identifier) + self.assertEqual(0, len(packageBody.DeclaredItems)) def test_Context(self): context = Context("ctx_1") self.assertIsNotNone(context) - self.assertEqual(context.Identifier, "ctx_1") + self.assertEqual("ctx_1", context.Identifier) def test_Configuration(self): configuration = Configuration("conf_1") self.assertIsNotNone(configuration) - self.assertEqual(configuration.Identifier, "conf_1") + self.assertEqual("conf_1", configuration.Identifier) - def test_SubType(self): + def test_Subtype(self): subtype = Subtype("bit") self.assertIsNotNone(subtype) - self.assertEqual(subtype.Identifier, "bit") + self.assertEqual("bit", subtype.Identifier) def test_Integer(self): integer = IntegerType("integer", Range(IntegerLiteral(0), IntegerLiteral(7), Direction.To)) self.assertIsNotNone(integer) - self.assertEqual(integer.Identifier, "integer") + self.assertEqual("integer", integer.Identifier) def test_Real(self): real = RealType("real", Range(FloatingPointLiteral(0.0), FloatingPointLiteral(1.0), Direction.To)) self.assertIsNotNone(real) - self.assertEqual(real.Identifier, "real") + self.assertEqual("real", real.Identifier) def test_Array(self): array = ArrayType("bit_vector", [], None) self.assertIsNotNone(array) - self.assertEqual(array.Identifier, "bit_vector") + self.assertEqual("bit_vector", array.Identifier) def test_Record(self): - record = RecordType("range_record") + record = RecordType("rec", []) self.assertIsNotNone(record) - self.assertEqual(record.Identifier, "range_record") + self.assertEqual("rec", record.Identifier) From eaf1979f8e4093d0934b386c4d16a9712edac51c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 30 Jun 2021 13:48:42 +0200 Subject: [PATCH 9/9] Refined attribute specification. --- pyVHDLModel/PSLModel.py | 10 +++++++++- pyVHDLModel/VHDLModel.py | 22 ++++++++++++++++++++-- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/pyVHDLModel/PSLModel.py b/pyVHDLModel/PSLModel.py index 14cef8037..0412384ba 100644 --- a/pyVHDLModel/PSLModel.py +++ b/pyVHDLModel/PSLModel.py @@ -78,4 +78,12 @@ def __init__(self, identifier: str): @export class DefaultClock(PSLEntity): - pass + _identifier: str + + def __init__(self, identifier: str): + super().__init__() + self._identifier = identifier + + @property + def Identifier(self) -> str: + return self._identifier diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 13692d71a..19cacf1c5 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -1982,17 +1982,35 @@ def Subtype(self): @export class AttributeSpecification(ModelEntity): + _identifiers: List[Name] _attribute: Name + _entityClass: EntityClass + _expression: Expression - def __init__(self, attribute: Name): + def __init__(self, identifiers: List[Name], attribute: Name, entityClass: EntityClass, expression: Expression): super().__init__() + self._identifiers = identifiers self._attribute = attribute + self._entityClass = entityClass + self._expression = expression @property - def Attribute(self) -> Attribute: + def Identifiers(self) -> List[Name]: + return self._identifiers + + @property + def Attribute(self) -> Name: return self._attribute + @property + def EntityClass(self) -> EntityClass: + return self._entityClass + + @property + def Expression(self) -> Expression: + return self._expression + @export class InterfaceItem: