v0.11.1

doc/LanguageModel/DesignUnits.rst

@@ -80,7 +80,7 @@ types). An entity's list of statements is called body items.
 
      # inherited from MixinDesignUnitWithContext
      @property
-     def LibraryReferences(self) -> List[Library]:
+     def LibraryReferences(self) -> List[LibraryStatement]:
 
      @property
      def PackageReferences(self) -> List[UseClause]:
@@ -128,7 +128,7 @@ Package
 
      # inherited from MixinDesignUnitWithContext
      @property
-     def LibraryReferences(self) -> List[Library]:
+     def LibraryReferences(self) -> List[LibraryStatement]:
 
      @property
      def PackageReferences(self) -> List[UseClause]:
@@ -175,7 +175,7 @@ Architeture
 
      # inherited from MixinDesignUnitWithContext
      @property
-     def LibraryReferences(self) -> List[Library]:
+     def LibraryReferences(self) -> List[LibraryStatement]:
 
      @property
      def PackageReferences(self) -> List[UseClause]:
@@ -220,7 +220,7 @@ Package Body
 
      # inherited from MixinDesignUnitWithContext
      @property
-     def LibraryReferences(self) -> List[Library]:
+     def LibraryReferences(self) -> List[LibraryStatement]:
 
      @property
      def PackageReferences(self) -> List[UseClause]:

doc/LanguageModel/Miscellaneous.rst

@@ -36,7 +36,7 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a
 
      # from Design
      @property
-     def Libraries(self) -> List[Library]:
+     def Libraries(self) -> List[LibraryStatement]:
 
      @property
      def Documents(self) -> List[Document]:
@@ -45,24 +45,24 @@ a design has the two child nodes: ``Libraries`` and ``Documents``. Each is a
 
 .. _vhdlmodel-library:
 
-Library
-=======
+LibraryStatement
+================
 
 A library contains multiple *design units*. Each design unit listed in a library
 is a *primary* design unit like: ``configuration``, ``entity``, ``package`` or
 ``context``.
 
-**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Library`:
+**Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.LibraryStatement`:
 
 .. code-block:: Python
 
    @export
-   class Library(ModelEntity):
+   class LibraryStatement(ModelEntity):
      # inherited from ModelEntity
      @property
      def Parent(self) -> ModelEntity:
 
-     # from Library
+     # from LibraryStatement
      @property
      def Contexts(self) -> List[Context]:
 

doc/conf.py

@@ -37,7 +37,7 @@ def _LatestTagName():
 
 # The full version, including alpha/beta/rc tags
 version = "0.11"     # The short X.Y version.
-release = "0.11.0"   # The full version, including alpha/beta/rc tags.
+release = "0.11.1"   # The full version, including alpha/beta/rc tags.
 try:
 	if _IsUnderGitControl:
 		latestTagName = _LatestTagName()[1:]		# remove prefix "v"

pyVHDLModel/PSLModel.py

@@ -0,0 +1,89 @@
+# =============================================================================
+#             __     ___   _ ____  _     __  __           _      _
+#   _ __  _   \ \   / / | | |  _ \| |   |  \/  | ___   __| | ___| |
+#  | '_ \| | | \ \ / /| |_| | | | | |   | |\/| |/ _ \ / _` |/ _ \ |
+#  | |_) | |_| |\ V / |  _  | |_| | |___| |  | | (_) | (_| |  __/ |
+#  | .__/ \__, | \_/  |_| |_|____/|_____|_|  |_|\___/ \__,_|\___|_|
+#  |_|    |___/
+# ==============================================================================
+# Authors:            Patrick Lehmann
+#
+# Python module:      An abstract PSL language model.
+#
+# Description:
+# ------------------------------------
+#		TODO:
+#
+# License:
+# ==============================================================================
+# Copyright 2017-2021 Patrick Lehmann - Boetzingen, Germany
+# Copyright 2016-2017 Patrick Lehmann - Dresden, Germany
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# ==============================================================================
+#
+"""
+This module contains a document language model for PSL.
+
+:copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany
+:license: Apache License, Version 2.0
+"""
+# load dependencies
+from pydecor.decorators import export
+
+from pyVHDLModel.VHDLModel import PrimaryUnit, ModelEntity
+
+
+__all__ = []
+
+@export
+class PSLPrimaryUnit(PrimaryUnit):
+	pass
+
+
+@export
+class PSLEntity(ModelEntity):
+	pass
+
+
+@export
+class VerificationUnit(PSLPrimaryUnit):
+	def __init__(self, identifier: str):
+		super().__init__(identifier)
+
+
+@export
+class VerificationProperty(PSLPrimaryUnit):
+	def __init__(self, identifier: str):
+		super().__init__(identifier)
+
+
+@export
+class VerificationMode(PSLPrimaryUnit):
+	def __init__(self, identifier: str):
+		super().__init__(identifier)
+
+
+@export
+class DefaultClock(PSLEntity):
+	_identifier: str
+
+	def __init__(self, identifier: str):
+		super().__init__()
+		self._identifier = identifier
+
+	@property
+	def Identifier(self) -> str:
+		return self._identifier