diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index a42a05658..5d0230f91 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -101,7 +101,8 @@ class Direction(Enum): DownTo = 1 def __str__(self): - return ("to", "downto")[self.value] # TODO: check performance + index: int = self.value + return ("to", "downto")[index] # TODO: check performance @export @@ -121,7 +122,8 @@ class Mode(Enum): Linkage = 5 def __str__(self): - return ("", "in", "out", "inout", "buffer", "linkage")[self.value] # TODO: check performance + index: int = self.value + return ("", "in", "out", "inout", "buffer", "linkage")[index] # TODO: check performance @export @@ -445,10 +447,10 @@ def __init__(self, subTypeName: Name): class ConstrainedScalarSubTypeSymbol(SubTypeSymbol): _range: 'Range' - def __init__(self, subTypeName: Name, r: 'Range' = None): + def __init__(self, subTypeName: Name, rng: 'Range' = None): super().__init__(subTypeName) self._subType = None - self._range = r + self._range = rng @property def Range(self) -> 'Range': @@ -734,6 +736,7 @@ def __init__(self, name: str): @export class BaseType(ModelEntity, NamedEntity): """``BaseType`` is the base class of all type entities in this model.""" + def __init__(self, name: str): """ Initializes underlying ``BaseType``. @@ -1618,16 +1621,6 @@ class BaseConstraint(ModelEntity): pass -# FIXME: exists 2 times -@export -class RangeExpression(BaseConstraint): - _range: Range - - @property - def Range(self): - return self._range - - # FIXME: Is this used? @export class RangeAttribute(BaseConstraint): diff --git a/pyVHDLModel/__init__.py b/pyVHDLModel/__init__.py index 2b052dfdd..0ed569bc0 100644 --- a/pyVHDLModel/__init__.py +++ b/pyVHDLModel/__init__.py @@ -35,7 +35,9 @@ # ============================================================================== # """ +An abstract VHDL language model. + :copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany :license: Apache License, Version 2.0 """ -__version__ = "0.8.1" +__version__ = "0.10.5"