diff --git a/arch/arm64/boot/dts/vendor/.gitignore b/arch/arm64/boot/dts/vendor/.gitignore new file mode 100644 index 000000000000..d6b0c0528ef6 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/.gitignore @@ -0,0 +1,2 @@ +# Ignore camera directory +qcom/camera diff --git a/arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt b/arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt index 0660e025802e..ca786f1bce07 100755 --- a/arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt +++ b/arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt @@ -59,6 +59,9 @@ SoCs: - BENGAL compatible = "qcom,bengal" +- KHAJE + compatible = "qcom,khaje" + - SCUBA compatible = "qcom,scuba" @@ -247,6 +250,8 @@ compatible = "qcom,bengal-qrd" compatible = "qcom,bengal-idp" compatible = "qcom,bengalp" compatible = "qcom,bengalp-idp" +compatible = "qcom,khaje-idp" +compatible = "qcom,khaje-qrd" compatible = "qcom,scuba-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,scuba-qrd" diff --git a/arch/arm64/boot/dts/vendor/bindings/bt-fm/fm.txt b/arch/arm64/boot/dts/vendor/bindings/bt-fm/fm.txt new file mode 100755 index 000000000000..ed73e5d22180 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/bt-fm/fm.txt @@ -0,0 +1,29 @@ +Qti radio iris device + +-FM RX playback with no RDS + + FM samples is filtered by external RF chips at baseband, then send to Riva-FM core through serial link. + FM signal is demodulated then audio L/R samples are stored inside memory. + FM Rx received samples data is connected to external audio codec. + +-Audio playback to FM TX + + Used to play audio source to FM TX. + FM TX module will read the audio samples from memory then modulated samples will be send through serial interface to external RF chip. + +-RX playback with RDS + + FM Rx receive audio data along with RDS. + +-FM TX with RDS + + Used to send RDS messages to external FM receiver. + +Required Properties: +- compatible: "qcom,iris_fm" + +Example: + qcom,iris-fm { + compatible = "qcom,iris_fm"; + }; + diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,clock-cpu-8939.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,clock-cpu-8939.txt deleted file mode 100755 index e2190df5f55f..000000000000 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,clock-cpu-8939.txt +++ /dev/null @@ -1,79 +0,0 @@ -Qualcomm Technologies, Inc. MSM8939 CPU clock tree - -clock-cpu-8939 is a device that represents the MSM8939 or MSM8952 CPU -subsystem clock tree. It lists the various power supplies that need to be -scaled when the clocks are scaled and also other HW specific parameters like -fmax tables, avs settings table, etc. - -Required properties: -- compatible: Must be one of "qcom,clock-cpu-8939" or - "qcom,cpu-clock-8952", "qcom,cpu-clock-8917", - "qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429". -- reg: Pairs of physical base addresses and region sizes of - memory mapped registers. -- reg-names: Names of the bases for the above registers. Expected - bases are: - "apcs-c0-rcg-base", "apcs-c1-rcg-base", - "apcs-cci-rcg-base", "efuse", "efuse1", "efuse2" -- vdd-c0-supply: The regulator powering the little cluster -- vdd-c1-supply: The regulator powering the big cluster -- vdd-cci-supply: The regulator powering the CCI cluster -- qcom,speedX-bin-vY-ZZZ: - A table of CPU frequency (Hz) to voltage (corner) - mapping that represents the max frequency possible - for each supported voltage level for a CPU. 'X' is - the speed bin into which the device falls into - a - bin will have unique frequency-voltage relationships. - 'Y' is the characterization version, implying that - characterization (deciding what speed bin a device - falls into) methods and/or encoding may change. The - values 'X' and 'Y' are read from efuse registers, and - the right table is picked from multiple possible tables. - 'ZZZ' can be c1, c0 or cci depending on whether the table - is for the big cluster, little cluster or cci. -Optional properties: -- qcom,cpu-pcnoc-vote: Boolean to indicate cpu clocks would need to keep - active pcnoc vote. -- qcom,num-cluster: Boolean to indicate cpu clock code is used for single - cluster. -Example: - clock_cpu: qcom,cpu-clock-8939@f9015000 { - compatible = "qcom,cpu-clock-8939"; - reg = <0xf9015000 0x1000>, - <0xf9016000 0x1000>, - <0xf9011000 0x1000>, - <0xf900d000 0x1000>, - <0xf900f000 0x1000>, - <0xf9112000 0x1000>; - reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base", - "apcs-cci-rcg-base", "efuse", "efuse1", - "efuse2"; - vdd-c0-supply = <&apc_vreg_corner>; - vdd-c1-supply = <&apc_vreg_corner>; - vdd-cci-supply = <&apc_vreg_corner>; - qcom,speed0-bin-v0-c0 = - < 0 0>, - < 384000000 1>, - < 787200000 2>, - <1286400000 3>; - qcom,speed0-bin-v0-c1 = - < 0 0>, - < 384000000 1>, - < 787200000 2>, - <1785600000 3>; - qcom,speed0-bin-v0-cci = - < 0 0>, - < 150000000 1>, - < 300000000 2>, - < 600000000 3>; - clocks = <&clock_gcc clk_gpll0_ao>, - <&clock_gcc clk_a53ss_c0_pll>, - <&clock_gcc clk_gpll0_ao>, - <&clock_gcc clk_a53ss_c1_pll>, - <&clock_gcc clk_gpll0_ao>, - <&clock_gcc clk_a53ss_cci_pll>; - clock-names = "clk-c0-4", "clk-c0-5", - "clk-c1-4", "clk-c1-5", - "clk-cci-4", "clk-cci-5"; - #clock-cells = <1>; -}; diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,debugcc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,debugcc.txt index 35fcde1f015e..59b99da25c7c 100755 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,debugcc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,debugcc.txt @@ -6,7 +6,8 @@ Required properties : "qcom,bengal-debugcc", "qcom,lagoon-debugcc" "qcom,sdm660-debugcc" "qcom,sdm429w-debugcc" "qcom,msm8937-debugcc" "qcom,msm8917-debugcc" - "qcom,sdm429w-debugcc "or "qcom,qm215-debugcc". + "qcom,sdm429w-debugcc", "qcom,qm215-debugcc" + or "qcom,sdm450-debugcc", "qcom,khaje-debugcc". - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. - qcom,camcc: phandle to the Camera CC device node. diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,dispcc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,dispcc.txt index de9da0833f1f..725cd3a5265b 100755 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,dispcc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,dispcc.txt @@ -9,7 +9,8 @@ Required properties : "qcom,lito-dispcc" "qcom,bengal-dispcc" "qcom,lagoon-dispcc" - "qcom,scuba-dispcc". + "qcom,scuba-dispcc" + "qcom,khaje-dispcc". - reg : shall contain base register location and length. - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf of the clocks. diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gcc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gcc.txt index 179f56cbc334..932c0243721b 100755 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gcc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gcc.txt @@ -31,12 +31,12 @@ Required properties : "qcom,gcc-msm8917" "qcom,gcc-msm8937" "qcom,gcc-sdm429w" + "qcom,gcc-sdm450" "qcom,gcc-mdss-msm8937" - "qcom,gcc-mdss-8917" + "qcom,gcc-mdss-qm215" "qcom,gcc-mdss-sdm429w" - "qcom,gcc-mdss-sdm429" "qcom,gcc-mdss-sdm439" - "qcom,gcc-mdss-sdm429w" + "qcom,khaje-gcc" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gpucc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gpucc.txt index 0d5a86e5f819..c9e1a75794a5 100755 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gpucc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,gpucc.txt @@ -9,7 +9,8 @@ Required properties : "qcom,lagoon-gpucc", "qcom,gpu-sdm660", "qcom,gpucc-sdm660", - "qcom,gpucc-sdm630". + "qcom,gpucc-sdm630", + "qcom,khaje-gpucc". - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,rpmcc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,rpmcc.txt index 4a3152d91bae..d99daf4cd708 100755 --- a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,rpmcc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,rpmcc.txt @@ -18,9 +18,9 @@ Required properties : "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-bengal", "qcom,rpmcc" "qcom,rpmcc-sdm660", "qcom,rpmcc" - "qcom,rpmcc-msm8937", "qcom,rpmcc" - "qcom,rpmcc-msm8917", "qcom,rpmcc" + "qcom,rpmcc-sdm439", "qcom,rpmcc" "qcom,rpmcc-qm215", "qcom,rpmcc" + "qcom,rpmcc-sdm450", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/arch/arm64/boot/dts/vendor/bindings/clock/qcom,sdm-cpucc.txt b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,sdm-cpucc.txt new file mode 100755 index 000000000000..4b6d9101c6ac --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/clock/qcom,sdm-cpucc.txt @@ -0,0 +1,96 @@ +Qualcomm Technologies, Inc. SDM CPU clock driver +--------------------------------------------------- + +It is the clock controller driver which provides higher frequency +clocks and allows CPU frequency scaling on sdm based platforms. + +Required properties: +- compatible: Shall contain following: + "qcom,cpu-clock-sdm", "qcom,cpu-clock-qm215", + "qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429" +- clocks: Phandle to the clock device. +- clock-names: Names of the used clocks. Shall contain following: + "xo_ao", "gpll0_ao" +- reg: Shall contain base register offset and size. +- reg-names: Names of the bases for the above registers. Shall contain following: + "apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse" +- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL. +- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL. +- cpu-vdd-supply: The regulator powering the APSS C1 RCG and APSS CCI RCG. +- qcom,speedX-bin-vY-Z: A table of CPU frequency (Hz) to regulator voltage (uV) mapping. + Format: + This represents the max frequency possible for each possible + power configuration for a CPU that's binned as speed bin X, + speed bin revision Y. Version can be between [0-3]. Z + is the mux id c1 or cci. +- #clock-cells: Shall contain 1. + +Example: + clock_cpu: qcom,clock-cpu@0b011050 { + compatible = "qcom,cpu-clock-sdm"; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0_AO_OUT_MAIN>; + clock-names = "xo_ao", "gpll0_ao" ; + reg = <0xb011050 0x8>, + <0xb1d1050 0x8>, + <0xb016000 0x34>, + <0x00a412c 0x8>; + reg-names = "apcs-c1-rcg-base", + "apcs-cci-rcg-base", "apcs_pll", "efuse"; + cpu-vdd-supply = <&apc_vreg_corner>; + vdd_dig_ao-supply = <&L12A_AO; + vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>; + qcom,speed0-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>; + + qcom,speed0-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed1-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1804800000 5>; + + qcom,speed1-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed4-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>, + < 1958400000 5>, + < 2016000000 6>; + + qcom,speed4-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + qcom,speed5-bin-v0-c1 = + < 0 0>, + < 960000000 1>, + < 1305600000 1>, + < 1497600000 2>, + < 1708800000 3>; + + qcom,speed5-bin-v0-cci = + < 0 0>, + < 400000000 1>, + < 533333333 3>; + + #clock-cells = <1>; + }; diff --git a/arch/arm64/boot/dts/vendor/bindings/cnss/cnss-wlan.txt b/arch/arm64/boot/dts/vendor/bindings/cnss/cnss-wlan.txt index 8301c02e6330..3de21e43ca7e 100755 --- a/arch/arm64/boot/dts/vendor/bindings/cnss/cnss-wlan.txt +++ b/arch/arm64/boot/dts/vendor/bindings/cnss/cnss-wlan.txt @@ -82,6 +82,7 @@ Optional properties: - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO enable to resolve PMU power up issues. Provide BT GPIO using this config param. + - qcom,sw-ctrl-gpio: Switch control GPIO for device power control Example: diff --git a/arch/arm64/boot/dts/vendor/bindings/cnss/wcnss-wlan.txt b/arch/arm64/boot/dts/vendor/bindings/cnss/wcnss-wlan.txt new file mode 100755 index 000000000000..fbe1bcadf437 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/cnss/wcnss-wlan.txt @@ -0,0 +1,110 @@ +* Qualcomm Technologies Inc. WCNSS Platform Driver + +WCNSS driver is the platform driver. It is used for performing the cold +boot-up of the wireless device. It is responsible for adjusting +the necessary I/O rails and enabling appropriate gpios for wireless +connectivity subsystem. + +Required properties: +- compatible: "wcnss_wlan" +- reg: physical address and length of the register set for the device. +- reg-names: "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base", + "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base", + "pronto_saw2_base", "wlan_tx_phy_aborts","wlan_brdg_err_source", + "wlan_tx_status", "alarms_txctl", "alarms_tactl", + "pronto_mcu_base", "pronto_qfuse". +- interupts: Pronto to Apps interrupts for tx done and rx pending. +- qcom,pronto-vddmx-supply: regulator to supply pronto pll. +- qcom,pronto-vddcx-supply: voltage corner regulator to supply WLAN/BT/FM +digital module. +- qcom,pronto-vddpx-supply: regulator to supply WLAN DAC. +- qcom,iris-vddxo-supply : regulator to supply RF XO. +- qcom,iris-vddrfa-supply : regulator to supply RFA digital. +- qcom,iris-vddpa-supply : regulator to supply RF PA. +- qcom,iris-vdddig-supply : regulator to supply RF digital(BT/FM). +- gpios: gpio numbers to configure 5-wire interface of WLAN connectivity +- qcom,has-48mhz-xo: boolean flag to determine the usage of 24MHz XO from RF +- qcom,has-pronto-hw: boolean flag to determine the revId of the WLAN subsystem +- qcom,wcnss-adc_tm: ADC handle for vbatt notification APIs. +- qcom,wcnss-vadc: VADC handle for battery voltage notification APIs. +- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt +- pinctrl-names : Names corresponding to the numbered pinctrl states +- clocks: from common clock binding: handle to xo, rf_clk and wcnss snoc clocks. +- clock-names: Names of all the clocks that are accessed by the subsystem +- qcom,vdd-voltage-level: This property represents (nominal, min, max) voltage +for iris and pronto regulators in milli-volts. +- qcom,vdd-current: This property represents current value for +iris and pronto regulators in micro-amps. + +Optional properties: +- qcom,has-autodetect-xo: boolean flag to determine whether Iris XO auto detect +should be performed during boot up. +- qcom,snoc-wcnss-clock-freq: indicates the wcnss snoc clock frequency in Hz. +If wcnss_snoc clock is specified in the list of clocks, this property needs +to be set to make it functional. +- qcom,wlan-rx-buff-count: WLAN RX buffer count is a configurable value, +using a smaller count for this buffer will reduce the memory usage. +- qcom,is-pronto-v3: boolean flag to determine the pronto hardware version +in use. subsequently correct workqueue will be used by DXE engine to push frames +in TX data path. +- qcom,is-dual-band-disable: boolean flag to determine the WLAN dual band +capability. +- qcom,is-pronto-vadc: boolean flag to determine Battery voltage feature +support for pronto hardware. +- qcom,wcnss-pm : +Power manager related parameter for LDO configuration. + 11 - WCN CORE rail LDO number + 21 - WCN PA rail LDO number + 1200 - WCN XO settling time (usec) + 1 - WCN RPM power collapse enabled + 1 - WCN standalone power collapse enabled + 6 - GPIO strength value +- qcom,has-vsys-adc-channel: boolean flag to determine which ADC HW channel need +to use for VBATT feature. +- qcom,has-a2xb-split-reg: boolean flag to determine A2xb split timeout limit +register is available or not. + +Example: + +qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; +reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8841_s1>; + qcom,pronto-vddcx-supply = <&pm8841_s2_corner>; + qcom,pronto-vddpx-supply = <&pm8941_s3>; + qcom,iris-vddxo-supply = <&pm8941_l6>; + qcom,iris-vddrfa-supply = <&pm8941_l11>; + qcom,iris-vddpa-supply = <&pm8941_l19>; + qcom,iris-vdddig-supply = <&pm8941_l3>; + + gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>, + <&msmgpio 39 0>, <&msmgpio 40 0>; + qcom,has-48mhz-xo; + qcom,is-pronto-vt; + qcom,wlan-rx-buff-count = <512>; + qcom,has-pronto-hw; + qcom,wcnss-adc_tm = <&pm8226_adc_tm>; + + pinctrl-names = "wcnss_default", "wcnss_sleep"; + pinctrl-0 = <&wcnss_default>; + pinctrl-1 = <&wcnss_sleep>; + pinctrl-2 = <&wcnss_gpio_default>; + + clocks = <&clock_rpm clk_xo_wlan_clk>, + <&clock_rpm clk_rf_clk2>, + <&clock_debug clk_gcc_debug_mux>, + <&clock_gcc clk_wcnss_m_clk>, + <&clock_gcc clk_snoc_wcnss_a_clk>; + + clock-names = "xo", "rf_clk", "measure", "wcnss_debug", + "snoc_wcnss"; + + qcom,snoc-wcnss-clock-freq = <200000000>; + qcom,wcnss-pm = <11 21 1200 1 1 6>; +}; diff --git a/arch/arm64/boot/dts/vendor/bindings/display/msm/sde.txt b/arch/arm64/boot/dts/vendor/bindings/display/msm/sde.txt index 00108a47d68d..73c73c15591b 100755 --- a/arch/arm64/boot/dts/vendor/bindings/display/msm/sde.txt +++ b/arch/arm64/boot/dts/vendor/bindings/display/msm/sde.txt @@ -282,6 +282,13 @@ Optional properties: DSPP offsets. Since LTM hardware is represented as part of DSPP block, the LTM offsets are calculated based on the corresponding DSPP base. +- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware. +- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. +- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. +- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. - qcom,sde-vbif-id: Array of vbif ids corresponding to the offsets defined in property: qcom,sde-vbif-off. - qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit diff --git a/arch/arm64/boot/dts/vendor/bindings/iio/adc/qcom-rradc.txt b/arch/arm64/boot/dts/vendor/bindings/iio/adc/qcom-rradc.txt index 1ab49edfe30c..f21aa9015ae5 100755 --- a/arch/arm64/boot/dts/vendor/bindings/iio/adc/qcom-rradc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/iio/adc/qcom-rradc.txt @@ -45,6 +45,10 @@ Optional property: - qcom,pmic-revid : Phandle pointing to the revision peripheral node. Use it to query the PMIC fabrication ID for applying the appropriate temperature compensation parameters. + +- qcom,rradc-fg-reset-wa : With this property enabled, RRADC can register for a power supply + notifier and reset FG through a power supply property if it gets stuck. + Example: /* RRADC node */ diff --git a/arch/arm64/boot/dts/vendor/bindings/leds/leds-qpnp-flash-v2.txt b/arch/arm64/boot/dts/vendor/bindings/leds/leds-qpnp-flash-v2.txt index a282b4c8d9a4..682f8afbdf59 100755 --- a/arch/arm64/boot/dts/vendor/bindings/leds/leds-qpnp-flash-v2.txt +++ b/arch/arm64/boot/dts/vendor/bindings/leds/leds-qpnp-flash-v2.txt @@ -22,6 +22,12 @@ Optional properties: 128, 192. Unit is uS. - qcom,warmup-delay-us : Integer type to specify warm up delay. Valid values are 32, 64, 128, 192. Unit is uS. +- qcom,ramp-up-step : Integer property to specify flash current ramp up time + step. Unit is in nS. Allowed values are: 200, 400, 800, 1600, + 3200, 6400, 12800, 25600. +- qcom,ramp-down-step : Integer property to specify flash current ramp down + time step. Unit is in nS. Allowed values are: 200, 400, 800, 1600, + 3200, 6400, 12800, 25600. - qcom,short-circuit-det : Boolean property which enables short circuit fault detection. - qcom,open-circuit-det : Boolean property which enables open circuit fault detection. - qcom,vph-droop-det : Boolean property which enables VPH droop detection. diff --git a/arch/arm64/boot/dts/vendor/bindings/media/video/msm-vidc.txt b/arch/arm64/boot/dts/vendor/bindings/media/video/msm-vidc.txt index 264725fb1f2e..793a1a61d3df 100755 --- a/arch/arm64/boot/dts/vendor/bindings/media/video/msm-vidc.txt +++ b/arch/arm64/boot/dts/vendor/bindings/media/video/msm-vidc.txt @@ -11,6 +11,7 @@ Required properties: - "qcom,bengal-vidc" : Invokes driver specific data for BENGAL. - "qcom,lagoon-vidc" : Invokes driver specific data for LAGOON. - "qcom,scuba-vidc" : Invokes driver specific data for SCUBA. + - "qcom,qcs8250-vidc" : Invokes driver specific data for KONA. Optional properties: - reg : offset and length of the register set for the device. - sku-index : sku version of the hardware. diff --git a/arch/arm64/boot/dts/vendor/bindings/mfd/qcom-pm8xxx.txt b/arch/arm64/boot/dts/vendor/bindings/mfd/qcom-pm8xxx.txt index 07f49254f366..3d3d628dd97e 100755 --- a/arch/arm64/boot/dts/vendor/bindings/mfd/qcom-pm8xxx.txt +++ b/arch/arm64/boot/dts/vendor/bindings/mfd/qcom-pm8xxx.txt @@ -65,6 +65,7 @@ The below bindings specify the set of valid subnodes. "qcom,pm8941-rtc" "qcom,pm8018-rtc" "qcom,pmk8350-rtc" + "qcom,pm8916-rtc" - reg: Usage: required diff --git a/arch/arm64/boot/dts/vendor/bindings/misc/qcom,qrc.txt b/arch/arm64/boot/dts/vendor/bindings/misc/qcom,qrc.txt new file mode 100755 index 000000000000..619807939286 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/misc/qcom,qrc.txt @@ -0,0 +1,13 @@ +Qualcomm Technologies, Inc. qrc driver + +Driver for QTI robotic controller. + +Required properties: + +compatible = "qcom,qrc-uart"; + +Example: + +qrc: qcom,qrc_uart { + compatible = "qcom,qrc-uart"; +}; diff --git a/arch/arm64/boot/dts/vendor/bindings/net/btusb.txt b/arch/arm64/boot/dts/vendor/bindings/net/btusb.txt index d883a35641d1..37d67926dd6d 100755 --- a/arch/arm64/boot/dts/vendor/bindings/net/btusb.txt +++ b/arch/arm64/boot/dts/vendor/bindings/net/btusb.txt @@ -35,7 +35,7 @@ Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt: compatible = "usb1286,204e"; reg = <1>; interrupt-parent = <&gpio0>; - interrupt-names = "wakeup"; + interrupt-name = "wakeup"; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/vendor/bindings/net/nfc/nxp-nci.txt b/arch/arm64/boot/dts/vendor/bindings/net/nfc/nxp-nci.txt index 9e4dc510a40a..cfaf88998918 100755 --- a/arch/arm64/boot/dts/vendor/bindings/net/nfc/nxp-nci.txt +++ b/arch/arm64/boot/dts/vendor/bindings/net/nfc/nxp-nci.txt @@ -25,7 +25,7 @@ Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2): clock-frequency = <100000>; interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <29 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/vendor/bindings/net/nfc/pn544.txt b/arch/arm64/boot/dts/vendor/bindings/net/nfc/pn544.txt index 2bd82562ce8e..92f399ec22b8 100755 --- a/arch/arm64/boot/dts/vendor/bindings/net/nfc/pn544.txt +++ b/arch/arm64/boot/dts/vendor/bindings/net/nfc/pn544.txt @@ -25,7 +25,7 @@ Example (for ARM-based BeagleBone with PN544 on I2C2): clock-frequency = <400000>; interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/qpnp-linear-charger.txt b/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/qpnp-linear-charger.txt index e254001563f3..82ae6b49595d 100755 --- a/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/qpnp-linear-charger.txt +++ b/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/qpnp-linear-charger.txt @@ -18,6 +18,8 @@ Parent node required properties: - qcom,vddsafe-mv: Maximum Vdd voltage in mV. - qcom,vinmin-mv: Minimum input voltage in mV. - qcom,ibatsafe-ma: Safety battery current setting +- qcom,v-cutoff-mv: Cutoff voltage where the battery + is considered dead in mV. Parent node optional properties: - qcom,vbatweak-uv: Weak battery voltage threshold in uV, diff --git a/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/smb1398-charger.txt b/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/smb1398-charger.txt index 5f1588f6a647..5764c68dc84d 100755 --- a/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/smb1398-charger.txt +++ b/arch/arm64/boot/dts/vendor/bindings/power/supply/qcom/smb1398-charger.txt @@ -28,6 +28,10 @@ Charger specific properties: mode (auto transition between DIV2 CP and 3-level buck) as a pre-regulator stand between wireless receiver and downstream chargers. + "qcom,smb1394-div2-cp-primary" for SMB1394 working in DIV2 mode as + a primary companion charger. + "qcom,smb1394-div2-cp-secondary" for SMB1394 working in DIV2 mode as + a secondary companion charger. - interrupts Usage: optional diff --git a/arch/arm64/boot/dts/vendor/bindings/regulator/gdsc-regulator.txt b/arch/arm64/boot/dts/vendor/bindings/regulator/gdsc-regulator.txt index 4f31737f9aef..bb45a0653c0e 100755 --- a/arch/arm64/boot/dts/vendor/bindings/regulator/gdsc-regulator.txt +++ b/arch/arm64/boot/dts/vendor/bindings/regulator/gdsc-regulator.txt @@ -76,6 +76,8 @@ Optional properties: - qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement to leave the GDSC on that has been enabled by an entity external to HLOS. + - qcom,no-config-gdscr: Presence denotes HW only supports a single register + per GDSC. [1]: Documentation/devicetree/bindings/arm/msm/msm_bus.txt diff --git a/arch/arm64/boot/dts/vendor/bindings/thermal/qcom-thermal-efprom.txt b/arch/arm64/boot/dts/vendor/bindings/thermal/qcom-thermal-efprom.txt new file mode 100755 index 000000000000..d9e501038a91 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/thermal/qcom-thermal-efprom.txt @@ -0,0 +1,73 @@ +Modify Thermal Zone based on efuse data + +This driver is to enable/disable pre-configured thermal +zones selectively at runtime based on efuse data. It uses QFPROM +nvmem cell interface to read efuse data. It supports multiple +efuse condition. If any of the efuse condition fails, driver just +exits with default enabled thermal zones. + +Properties: + +- compatible: + Usage: Required + Value type: + Definition: shall be "qcom,thermal-qfprom-device". + +- nvmem-cells: + Usage: Required + Value type: + Definition: Array of phandles pointing to a nvmem-cells node + representing the efuse registers that has information that + is used to select the right thermal zone to enable. + Please refer nvmem-cells bindings + Documentation/devicetree/bindings/nvmem/nvmem.txt and also + example below. + + nvmem-cell-names: + Usage: Required + Value type: + Definition: Should be array of name for each nvmem-cells phandle data. + Please refer nvmem-cells bindings + Documentation/devicetree/bindings/nvmem/nvmem.txt and also + example below. + +- qcom,thermal-qfprom-bit-values: It should be array of bit mask values to + match with each nvmem-cells bit value respectively. If all + nvmem-cells values are matching with respective bit mask value + from this property, then driver will update thermal zones as + per thermal zones mentioned in 'qcom,thermal-zone-enable-list' + and 'qcom,thermal-zone-disable-list'. + +- qcom,thermal-zone-enable-list: + Usage: Required + Value type: + Definition: Should define this property with list of thermal zone + names those need to be enabled if nvmem-cells condition is met. + +- qcom,thermal-zone-disable-list: + Usage: Required + Value type: + Definition: Should define this property with list of thermal zone + names those need to be disabled if nvmem-cells condition is met. + +Example: + qcom-thermal-qfprom { + compatible = "qcom,thermal-qfprom-device"; + nvmem-cells = <&thermal_cpe>, <&thermal_revision>; + nvmem-cell-names = "cpe", "revision"; + qcom,thermal-qfprom-bit-values = <0x1 0x3> + qcom,thermal-zone-enable-list = "mdm-core-0-cpe-step", + "mdm-core-1-cpe-step"; + qcom,thermal-zone-disable-list = "mdm-core-0-step", + "mdm-core-1-step"; + }; + + In this example, driver gets efuse bit values of nvmem-cell register + for both 'cpe' and 'revision' nvmem cells. It then compares these efuse + values with property 'qcom,thermal-qfprom-bit-values' values (0x1 and + 0x3 here) respectively. If both efuse values are matching with this + property values, driver enables thermal zones listed in property + 'qcom,thermal-zone-enable-list' and disables thermal zones listed in + property 'qcom,thermal-zone-disable-list'. If any of the efuse + value is not matching with respective 'qcom,thermal-qfprom-bit-values' + values, driver just exits without modifying any thermal zone. diff --git a/arch/arm64/boot/dts/vendor/bindings/wcnss/wcnss-wlan.txt b/arch/arm64/boot/dts/vendor/bindings/wcnss/wcnss-wlan.txt new file mode 100755 index 000000000000..fbe1bcadf437 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/bindings/wcnss/wcnss-wlan.txt @@ -0,0 +1,110 @@ +* Qualcomm Technologies Inc. WCNSS Platform Driver + +WCNSS driver is the platform driver. It is used for performing the cold +boot-up of the wireless device. It is responsible for adjusting +the necessary I/O rails and enabling appropriate gpios for wireless +connectivity subsystem. + +Required properties: +- compatible: "wcnss_wlan" +- reg: physical address and length of the register set for the device. +- reg-names: "wcnss_mmio", "wcnss_fiq", "pronto_phy_base", "riva_phy_base", + "riva_ccu_base", "pronto_a2xb_base", "pronto_ccpu_base", + "pronto_saw2_base", "wlan_tx_phy_aborts","wlan_brdg_err_source", + "wlan_tx_status", "alarms_txctl", "alarms_tactl", + "pronto_mcu_base", "pronto_qfuse". +- interupts: Pronto to Apps interrupts for tx done and rx pending. +- qcom,pronto-vddmx-supply: regulator to supply pronto pll. +- qcom,pronto-vddcx-supply: voltage corner regulator to supply WLAN/BT/FM +digital module. +- qcom,pronto-vddpx-supply: regulator to supply WLAN DAC. +- qcom,iris-vddxo-supply : regulator to supply RF XO. +- qcom,iris-vddrfa-supply : regulator to supply RFA digital. +- qcom,iris-vddpa-supply : regulator to supply RF PA. +- qcom,iris-vdddig-supply : regulator to supply RF digital(BT/FM). +- gpios: gpio numbers to configure 5-wire interface of WLAN connectivity +- qcom,has-48mhz-xo: boolean flag to determine the usage of 24MHz XO from RF +- qcom,has-pronto-hw: boolean flag to determine the revId of the WLAN subsystem +- qcom,wcnss-adc_tm: ADC handle for vbatt notification APIs. +- qcom,wcnss-vadc: VADC handle for battery voltage notification APIs. +- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt +- pinctrl-names : Names corresponding to the numbered pinctrl states +- clocks: from common clock binding: handle to xo, rf_clk and wcnss snoc clocks. +- clock-names: Names of all the clocks that are accessed by the subsystem +- qcom,vdd-voltage-level: This property represents (nominal, min, max) voltage +for iris and pronto regulators in milli-volts. +- qcom,vdd-current: This property represents current value for +iris and pronto regulators in micro-amps. + +Optional properties: +- qcom,has-autodetect-xo: boolean flag to determine whether Iris XO auto detect +should be performed during boot up. +- qcom,snoc-wcnss-clock-freq: indicates the wcnss snoc clock frequency in Hz. +If wcnss_snoc clock is specified in the list of clocks, this property needs +to be set to make it functional. +- qcom,wlan-rx-buff-count: WLAN RX buffer count is a configurable value, +using a smaller count for this buffer will reduce the memory usage. +- qcom,is-pronto-v3: boolean flag to determine the pronto hardware version +in use. subsequently correct workqueue will be used by DXE engine to push frames +in TX data path. +- qcom,is-dual-band-disable: boolean flag to determine the WLAN dual band +capability. +- qcom,is-pronto-vadc: boolean flag to determine Battery voltage feature +support for pronto hardware. +- qcom,wcnss-pm : +Power manager related parameter for LDO configuration. + 11 - WCN CORE rail LDO number + 21 - WCN PA rail LDO number + 1200 - WCN XO settling time (usec) + 1 - WCN RPM power collapse enabled + 1 - WCN standalone power collapse enabled + 6 - GPIO strength value +- qcom,has-vsys-adc-channel: boolean flag to determine which ADC HW channel need +to use for VBATT feature. +- qcom,has-a2xb-split-reg: boolean flag to determine A2xb split timeout limit +register is available or not. + +Example: + +qcom,wcnss-wlan@fb000000 { + compatible = "qcom,wcnss_wlan"; + reg = <0xfb000000 0x280000>, + <0xf9011008 0x04>; +reg-names = "wcnss_mmio", "wcnss_fiq"; + interrupts = <0 145 0 0 146 0>; + interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; + + qcom,pronto-vddmx-supply = <&pm8841_s1>; + qcom,pronto-vddcx-supply = <&pm8841_s2_corner>; + qcom,pronto-vddpx-supply = <&pm8941_s3>; + qcom,iris-vddxo-supply = <&pm8941_l6>; + qcom,iris-vddrfa-supply = <&pm8941_l11>; + qcom,iris-vddpa-supply = <&pm8941_l19>; + qcom,iris-vdddig-supply = <&pm8941_l3>; + + gpios = <&msmgpio 36 0>, <&msmgpio 37 0>, <&msmgpio 38 0>, + <&msmgpio 39 0>, <&msmgpio 40 0>; + qcom,has-48mhz-xo; + qcom,is-pronto-vt; + qcom,wlan-rx-buff-count = <512>; + qcom,has-pronto-hw; + qcom,wcnss-adc_tm = <&pm8226_adc_tm>; + + pinctrl-names = "wcnss_default", "wcnss_sleep"; + pinctrl-0 = <&wcnss_default>; + pinctrl-1 = <&wcnss_sleep>; + pinctrl-2 = <&wcnss_gpio_default>; + + clocks = <&clock_rpm clk_xo_wlan_clk>, + <&clock_rpm clk_rf_clk2>, + <&clock_debug clk_gcc_debug_mux>, + <&clock_gcc clk_wcnss_m_clk>, + <&clock_gcc clk_snoc_wcnss_a_clk>; + + clock-names = "xo", "rf_clk", "measure", "wcnss_debug", + "snoc_wcnss"; + + qcom,snoc-wcnss-clock-freq = <200000000>; + qcom,wcnss-pm = <11 21 1200 1 1 6>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/Makefile b/arch/arm64/boot/dts/vendor/qcom/Makefile index 1296d58454eb..971c954297b4 100755 --- a/arch/arm64/boot/dts/vendor/qcom/Makefile +++ b/arch/arm64/boot/dts/vendor/qcom/Makefile @@ -208,6 +208,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) bengal-rumi-overlay.dtbo \ bengal-qrd-overlay.dtbo \ bengal-idp-overlay.dtbo \ + bengal-idp-nopmi-overlay.dtbo \ bengal-idp-usbc-overlay.dtbo \ bengalp-idp-overlay.dtbo \ bengal-idp-1gb-overlay.dtbo \ @@ -226,6 +227,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) bengal-rumi-overlay.dtbo-base := bengal.dtb bengal-qrd-overlay.dtbo-base := bengal.dtb bengal-idp-overlay.dtbo-base := bengal.dtb +bengal-idp-nopmi-overlay.dtbo-base := bengal.dtb bengal-idp-usbc-overlay.dtbo-base := bengal.dtb bengalp-idp-overlay.dtbo-base := bengalp.dtb bengal-idp-1gb-overlay.dtbo-base := bengal-1gb.dtb @@ -244,6 +246,7 @@ else dtb-$(CONFIG_ARCH_BENGAL) += bengal-rumi.dtb \ bengal-qrd.dtb \ bengal-idp.dtb \ + bengal-idp-nopmi.dtb \ bengal-idp-usbc.dtb \ bengalp-idp.dtb \ bengal-idp-1gb.dtb \ @@ -301,6 +304,21 @@ dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \ scuba-iot-idp-usbc-2gb.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_KHAJE) += \ + khaje-idp-overlay.dtbo \ + khaje-qrd-overlay.dtbo \ + khaje-idp-nopmi-overlay.dtbo + +khaje-idp-overlay.dtbo-base := khaje.dtb +khaje-qrd-overlay.dtbo-base := khaje.dtb +khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb +else +dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ + khaje-qrd.dtb \ + khaje-idp-nopmi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SDM660) += \ sdm660-mtp-external-codec-overlay.dtbo \ @@ -367,7 +385,12 @@ endif endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) -dtbo-$(CONFIG_ARCH_SDM439) += sdm439-mtp-overlay.dtbo + +dtbo-$(CONFIG_ARCH_SDM439) += sdm439-mtp-overlay.dtbo \ + sdm439-cdp-overlay.dtbo \ + sdm439-qrd-overlay.dtbo \ + sdm439-external-codec-mtp-overlay.dtbo \ + sdm439-rcm-overlay.dtbo dtbo-$(CONFIG_ARCH_SDM429) += sdm429-mtp-overlay.dtbo \ sdm429-cdp-overlay.dtbo \ @@ -376,10 +399,22 @@ dtbo-$(CONFIG_ARCH_SDM429) += sdm429-mtp-overlay.dtbo \ dtbo-$(CONFIG_ARCH_QM215) +=qm215-qrd-overlay.dtbo \ qcm2150-qrd-overlay.dtbo \ qm215-qrd-smb1360-overlay.dtbo + sdm439-mtp-overlay.dtbo-base := sdm439.dtb \ sda439.dtb \ msm8937-interposer-sdm439.dtb +sdm439-cdp-overlay.dtbo-base := sdm439.dtb \ + sda439.dtb \ + msm8937-interposer-sdm439.dtb + +sdm439-qrd-overlay.dtbo-base := sdm439.dtb \ + msm8937-interposer-sdm439.dtb + +sdm439-external-codec-mtp-overlay.dtbo-base := sdm439.dtb +sdm439-rcm-overlay.dtbo-base := sdm439.dtb + + sdm429-mtp-overlay.dtbo-base := sdm429.dtb \ sda429.dtb \ msm8937-interposer-sdm429.dtb diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi index c5b6c25a5cc8..5bd4d1ddc894 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi @@ -1289,6 +1289,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi index eef3e49bcece..f0456538d3ef 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi @@ -1 +1,2 @@ #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts new file mode 100755 index 000000000000..1bb7fc94db8a --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "bengal-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. BENGAL IDP nopmi"; + compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp"; + qcom,msm-id = <417 0x10000>, <444 0x10000>; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts new file mode 100755 index 000000000000..a9f8f46a5c5f --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "bengal.dtsi" +#include "bengal-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. BENGAL IDP nopmi"; + compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi new file mode 100755 index 000000000000..6f000afa510f --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi @@ -0,0 +1,53 @@ +#include "bengal-idp.dtsi" + +&led_flash_rear { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux2 { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; +}; + +&dsi_td4330_truly_v2_video { + /delete-property/ qcom,esd-check-enabled; +}; + +&dsi_td4330_truly_v2_cmd { + /delete-property/ qcom,esd-check-enabled; +}; + +&qupv3_se2_i2c { + synaptics_tcm@20 { + status = "disabled"; + }; + + novatek@62 { + status = "disabled"; + }; + + focaltech@38 { + status = "disabled"; + }; +}; + +&usb0 { + /delete-property/ extcon; + dwc3@4e00000 { + dr_mode = "peripheral"; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts index 5b1e7f3b1ddd..31af8abb5617 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts @@ -3,10 +3,13 @@ #include #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" +#include "bengal-thermal-pmi632-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. BENGAL IDP"; compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp"; qcom,msm-id = <417 0x10000>, <444 0x10000>; qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x25 0x0 0x0>; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi new file mode 100755 index 000000000000..ac778bd2ddc1 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi @@ -0,0 +1,64 @@ +#include "bengal-pmi632.dtsi" + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,qg-use-s7-ocv; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,hvdcp2-max-icl-ua = <2000000>; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,float-option = <1>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; +}; + +&usb0 { + extcon = <&pmi632_charger>, <&eud>; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <105 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&dsi_td4330_truly_v2_video { + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_td4330_truly_v2_cmd { + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_nt36525_truly_video { + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts index 4f2bb4c659a4..53da1e43b32d 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts @@ -3,6 +3,7 @@ #include #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" #include "bengal-idp-usbc.dtsi" / { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts index c9e9b2498e0a..a0ae3f5735c7 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts @@ -2,6 +2,7 @@ #include "bengal.dtsi" #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" #include "bengal-idp-usbc.dtsi" / { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts index 5c41c0d3d9a4..1ad45c71030f 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts @@ -2,9 +2,12 @@ #include "bengal.dtsi" #include "bengal-idp.dtsi" +#include "bengal-thermal-pmi632-overlay.dtsi" +#include "bengal-idp-pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. BENGAL IDP"; compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp"; qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x25 0x0 0x0>; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi index 6989918cd649..160eb3ce0a76 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi @@ -6,13 +6,6 @@ #include "bengal-sde-display.dtsi" #include "camera/bengal-camera-sensor-idp.dtsi" -&soc { - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-alium-3600mah.dtsi" - }; -}; - &qupv3_se1_i2c { status = "ok"; #include "smb1355.dtsi" @@ -64,68 +57,11 @@ }; }; -&pmi632_qg { - qcom,battery-data = <&mtp_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,qg-use-s7-ocv; -}; - -&pmi632_charger { - qcom,battery-data = <&mtp_batterydata>; - qcom,suspend-input-on-debug-batt; - qcom,sw-jeita-enable; - qcom,step-charging-enable; - qcom,hvdcp2-max-icl-ua = <2000000>; - /* SMB1355 only */ - qcom,sec-charger-config = <2>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,auto-recharge-soc = <98>; - qcom,flash-disable-soc = <10>; - qcom,hw-die-temp-mitigation; - qcom,hw-connector-mitigation; - qcom,connector-internal-pull-kohm = <100>; - qcom,float-option = <1>; - qcom,thermal-mitigation = <3000000 2500000 - 2000000 1500000 1000000 500000>; -}; - -&pmi632_gpios { - smb_en { - smb_en_default: smb_en_default { - pins = "gpio2"; - function = "func1"; - output-enable; - }; - }; - - pmi632_sense { - /* GPIO 7 and 8 are external-sense pins for PMI632 */ - pmi632_sense_default: pmi632_sense_default { - pins = "gpio7", "gpio8"; - bias-high-impedance; /* disable the GPIO */ - bias-disable; /* no-pull */ - }; - }; - - pmi632_ctm { - /* Disable GPIO1 for h/w base mitigation */ - pmi632_ctm_default: pmi632_ctm_default { - pins = "gpio1"; - bias-high-impedance; /* disable the GPIO */ - bias-disable; /* no-pull */ - }; - }; -}; - &pm6125_gpios { rf_pa1_therm { rf_pa1_therm_default: rf_pa1_therm_default { - pins = "gpio7"; + pins = "gpio7"; bias-high-impedance; }; }; @@ -141,10 +77,6 @@ }; }; -&usb0 { - extcon = <&pmi632_charger>, <&eud>; -}; - &soc { gpio_keys { compatible = "gpio-keys"; @@ -202,23 +134,6 @@ }; }; -&smb1355 { - pinctrl-names = "default"; - pinctrl-0 = <&smb_int_default>; - interrupt-parent = <&tlmm>; - interrupts = <105 IRQ_TYPE_LEVEL_LOW>; - status = "ok"; -}; - -&smb1355_charger { - pinctrl-names = "default"; - pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; - qcom,parallel-mode = <1>; - qcom,disable-ctm; - qcom,hw-die-temp-mitigation; - status = "ok"; -}; - &sdhc_1 { vdd-supply = <&L24A>; qcom,vdd-voltage-level = <2960000 2960000>; @@ -302,7 +217,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 82 0>; - qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; &dsi_td4330_truly_v2_cmd { @@ -314,7 +228,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 81 0>; qcom,platform-reset-gpio = <&tlmm 82 0>; - qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; &dsi_nt36525_truly_video { @@ -325,7 +238,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 82 0>; - qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; &dsi_r66451_amoled_hd_90hz_video { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi index eef3e49bcece..f0456538d3ef 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi @@ -1 +1,2 @@ #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi index 6d93a7a8ff9f..794b85be9d8e 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi @@ -1,4 +1,5 @@ #include "bengal.dtsi" +#include "bengal-pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. BENGAL-IOT"; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi index 8179bf419f81..05c53c52643c 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi @@ -1,4 +1,5 @@ #include "bengal.dtsi" +#include "bengal-pmi632.dtsi" / { }; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi new file mode 100755 index 000000000000..caa724a3851b --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi @@ -0,0 +1,138 @@ +#include "pmi632.dtsi" + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + }; +}; + +&pmi632_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; +}; + +&pmi632_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pmi632_vadc ADC_GPIO2_PU2>; + + /* Channel nodes */ + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&pmi632_gpios { + disp_pins { + disp_pins_default: disp_pins_default { + pins = "gpio6"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&thermal_zones { + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-step { + cooling-maps { + batt_cdev1 { + cooling-device = <&pmi632_charger 2 2>; + }; + + batt_cdev2 { + cooling-device = <&pmi632_charger 4 4>; + }; + + batt_cdev3 { + cooling-device = <&pmi632_charger 6 6>; + }; + + batt_cdev4 { + cooling-device = <&pmi632_charger 7 7>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi new file mode 100755 index 000000000000..413bac37972a --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi @@ -0,0 +1,24 @@ +#include "bengal-qrd.dtsi" + +&led_flash_rear { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux2 { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts index 1a4bfdca0386..3d020cf52cbc 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts @@ -2,6 +2,8 @@ /plugin/; #include "bengal-qrd.dtsi" +#include "bengal-qrd-pmi632.dtsi" +#include "bengal-thermal-pmi632-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Bengal QRD"; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi new file mode 100755 index 000000000000..706b1f9c7f61 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi @@ -0,0 +1,94 @@ +#include "bengal-pmi632.dtsi" + +&soc { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pmi632_qg { + qcom,battery-data = <&qrd_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,qg-use-s7-ocv; +}; + +&pmi632_charger { + qcom,battery-data = <&qrd_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + qcom,hvdcp2-max-icl-ua = <2000000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,float-option = <1>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&usb0 { + extcon = <&pmi632_charger>, <&eud>; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <105 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&dsi_td4330_truly_v2_video { + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_td4330_truly_v2_cmd { + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts index 8d1c093986b2..bb5260836605 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts @@ -2,6 +2,8 @@ #include "bengal.dtsi" #include "bengal-qrd.dtsi" +#include "bengal-qrd-pmi632.dtsi" +#include "bengal-thermal-pmi632-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. Bengal QRD"; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi index 18858d38abfb..2f457586e9dd 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi @@ -11,70 +11,6 @@ #include "smb1355.dtsi" }; -&soc { - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl466271_3300mAh.dtsi" - }; -}; - -&pmi632_qg { - qcom,battery-data = <&qrd_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,qg-use-s7-ocv; -}; - -&pmi632_charger { - qcom,battery-data = <&qrd_batterydata>; - qcom,suspend-input-on-debug-batt; - qcom,sw-jeita-enable; - qcom,step-charging-enable; - /* SMB1355 only */ - qcom,sec-charger-config = <2>; - qcom,hvdcp2-max-icl-ua = <2000000>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; - qcom,auto-recharge-soc = <98>; - qcom,flash-disable-soc = <10>; - qcom,hw-die-temp-mitigation; - qcom,hw-connector-mitigation; - qcom,connector-internal-pull-kohm = <100>; - qcom,float-option = <1>; - qcom,thermal-mitigation = <4200000 3500000 3000000 - 2500000 2000000 1500000 1000000 500000>; -}; - -&pmi632_gpios { - smb_en { - smb_en_default: smb_en_default { - pins = "gpio2"; - function = "func1"; - output-enable; - }; - }; - - pmi632_sense { - /* GPIO 7 and 8 are external-sense pins for PMI632 */ - pmi632_sense_default: pmi632_sense_default { - pins = "gpio7", "gpio8"; - bias-high-impedance; /* disable the GPIO */ - bias-disable; /* no-pull */ - }; - }; - - pmi632_ctm { - /* Disable GPIO1 for h/w base mitigation */ - pmi632_ctm_default: pmi632_ctm_default { - pins = "gpio1"; - bias-high-impedance; /* disable the GPIO */ - bias-disable; /* no-pull */ - }; - }; -}; - &pm6125_gpios { key_vol_up { key_vol_up_default: key_vol_up_default { @@ -87,10 +23,6 @@ }; }; -&usb0 { - extcon = <&pmi632_charger>, <&eud>; -}; - &qusb_phy0 { qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 @@ -260,23 +192,6 @@ }; }; -&smb1355 { - pinctrl-names = "default"; - pinctrl-0 = <&smb_int_default>; - interrupt-parent = <&tlmm>; - interrupts = <105 IRQ_TYPE_LEVEL_LOW>; - status = "ok"; -}; - -&smb1355_charger { - pinctrl-names = "default"; - pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; - qcom,parallel-mode = <1>; - qcom,disable-ctm; - qcom,hw-die-temp-mitigation; - status = "ok"; -}; - &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v3-660"; @@ -318,7 +233,6 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 82 0>; - qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; &dsi_td4330_truly_v2_cmd { @@ -330,7 +244,6 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-te-gpio = <&tlmm 81 0>; qcom,platform-reset-gpio = <&tlmm 82 0>; - qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; }; &sde_dsi { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts index 87c19bae131d..8440ce03b7eb 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts @@ -2,6 +2,7 @@ /plugin/; #include +#include "bengal-pmi632.dtsi" #include "bengal-rumi.dtsi" / { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts index b443a8490901..f2efdfa98c82 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts @@ -2,6 +2,7 @@ /memreserve/ 0x90000000 0x00000100; #include "bengal.dtsi" +#include "bengal-pmi632.dtsi" #include "bengal-rumi.dtsi" / { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi index d9fcada497f2..b6d7337b6f5f 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi @@ -5,19 +5,6 @@ #include "dsi-panel-r66451-hd-plus-90hz-cmd.dtsi" #include -&pmi632_gpios { - disp_pins { - disp_pins_default: disp_pins_default { - pins = "gpio6"; - function = "func1"; - qcom,drive-strength = <2>; - power-source = <0>; - bias-disable; - output-low; - }; - }; -}; - &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi index bfc70d7808e4..cea18dc794f7 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi @@ -1,24 +1,6 @@ #include &thermal_zones { - pmi632-tz { - cooling-maps { - trip0_bat { - trip = <&pmi632_trip0>; - cooling-device = - <&pmi632_charger (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; - }; - - trip1_bat { - trip = <&pmi632_trip1>; - cooling-device = - <&pmi632_charger THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - pm6125-tz { cooling-maps { trip0_cpu0 { @@ -71,94 +53,6 @@ }; }; }; - - pmi632-bcl-lvl0 { - cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl0>; - cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-5) - (THERMAL_MAX_LIMIT-5)>; - }; - - cpu4_cdev { - trip = <&bcl_lvl0>; - cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-5) - (THERMAL_MAX_LIMIT-5)>; - }; - }; - }; - - pmi632-bcl-lvl1 { - cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-4) - (THERMAL_MAX_LIMIT-4)>; - }; - - cpu4_cdev { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-4) - (THERMAL_MAX_LIMIT-4)>; - }; - - cpu6_cdev { - trip = <&bcl_lvl1>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - cpu7_cdev { - trip = <&bcl_lvl1>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; - - pmi632-bcl-lvl2 { - cooling-maps { - cpu4_cdev { - trip = <&bcl_lvl2>; - cooling-device = <&cpu4_isolate 1 1>; - }; - - cpu5_cdev { - trip = <&bcl_lvl2>; - cooling-device = <&cpu5_isolate 1 1>; - }; - }; - }; - - soc { - cooling-maps { - soc_cpu0 { - trip = <&pmi632_low_soc>; - cooling-device = - <&CPU0 (THERMAL_MAX_LIMIT-4) - (THERMAL_MAX_LIMIT-4)>; - }; - - soc_cpu4 { - trip = <&pmi632_low_soc>; - cooling-device = - <&CPU4 (THERMAL_MAX_LIMIT-4) - (THERMAL_MAX_LIMIT-4)>; - }; - - soc_cpu6 { - trip = <&pmi632_low_soc>; - cooling-device = <&cpu6_isolate 1 1>; - }; - - soc_cpu7 { - trip = <&pmi632_low_soc>; - cooling-device = <&cpu7_isolate 1 1>; - }; - }; - }; }; &mdss_mdp { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi new file mode 100755 index 000000000000..677104643447 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi @@ -0,0 +1,109 @@ +#include + +&thermal_zones { + pmi632-tz { + cooling-maps { + trip0_bat { + trip = <&pmi632_trip0>; + cooling-device = + <&pmi632_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + trip1_bat { + trip = <&pmi632_trip1>; + cooling-device = + <&pmi632_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-bcl-lvl0 { + cooling-maps { + cpu0_cdev { + trip = <&bcl_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + + cpu4_cdev { + trip = <&bcl_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + }; + }; + + pmi632-bcl-lvl1 { + cooling-maps { + cpu0_cdev { + trip = <&bcl_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + cpu4_cdev { + trip = <&bcl_lvl1>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + cpu6_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu7_cdev { + trip = <&bcl_lvl1>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + pmi632-bcl-lvl2 { + cooling-maps { + cpu4_cdev { + trip = <&bcl_lvl2>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu5_cdev { + trip = <&bcl_lvl2>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu0 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + soc_cpu4 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-4) + (THERMAL_MAX_LIMIT-4)>; + }; + + soc_cpu6 { + trip = <&pmi632_low_soc>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + soc_cpu7 { + trip = <&pmi632_low_soc>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi index a2525d63e04b..8f0ba2c0afbf 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi @@ -564,21 +564,6 @@ }; }; - chg-skin-therm-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>; - wake-capable-sensor; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - gpu-step { polling-delay-passive = <10>; polling-delay = <0>; @@ -1232,22 +1217,18 @@ batt_cdev1 { trip = <&skin_batt_trip0>; - cooling-device = <&pmi632_charger 2 2>; }; batt_cdev2 { trip = <&skin_batt_trip1>; - cooling-device = <&pmi632_charger 4 4>; }; batt_cdev3 { trip = <&skin_batt_trip2>; - cooling-device = <&pmi632_charger 6 6>; }; batt_cdev4 { trip = <&skin_batt_trip3>; - cooling-device = <&pmi632_charger 7 7>; }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi index 2e00ba31b410..5a97a533a994 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi @@ -43,7 +43,7 @@ qcom,bus-master = ; qcom,bus-slave = ; qcom,mode = "vidc-ar50-ddr"; - qcom,bus-range-kbps = <1000 2128000>; + qcom,bus-range-kbps = <1000 6500000>; }; arm9_bus_ddr { diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi index b97942308648..519586abfd05 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi @@ -2652,7 +2652,6 @@ #include "bengal-coresight.dtsi" #include "bengal-bus.dtsi" #include "bengal-vidc.dtsi" -#include "pmi632.dtsi" #include "pm6125.dtsi" &gcc_camss_top_gdsc { @@ -2888,59 +2887,6 @@ }; }; -&pmi632_vadc { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&conn_therm_default &skin_therm_default>; - - conn_therm { - reg = ; - label = "conn_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - skin_therm { - reg = ; - label = "skin_therm"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; -}; - -&pmi632_gpios { - conn_therm { - conn_therm_default: conn_therm_default { - pins = "gpio1"; - bias-high-impedance; - }; - }; - - skin_therm { - skin_therm_default: skin_therm_default { - pins = "gpio3"; - bias-high-impedance; - }; - }; - -}; - -&pmi632_adc_tm { - #address-cells = <1>; - #size-cells = <0>; - io-channels = <&pmi632_vadc ADC_GPIO2_PU2>; - - /* Channel nodes */ - skin_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - }; -}; - &msm_vidc { qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; qcom,clock-freq-threshold = <300000000>; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts index d8ba915bd6d4..b01175e8d5ce 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts @@ -3,6 +3,7 @@ #include #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. BENGALP IDP"; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts index 578d7158addc..db8a15bdda1b 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts +++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts @@ -2,6 +2,7 @@ #include "bengalp.dtsi" #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. BENGALP IDP"; diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi index eef3e49bcece..f0456538d3ef 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi @@ -1 +1,2 @@ #include "bengal-idp.dtsi" +#include "bengal-idp-pmi632.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi index 165af6ac1c46..8a9fa89897a8 100755 --- a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi @@ -1,4 +1,5 @@ #include "bengal.dtsi" +#include "bengal-pmi632.dtsi" / { model = "Qualcomm Technologies, Inc. BENGALP-IOT"; diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt index f67f4ef7986a..9f5be32843e1 100755 --- a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt +++ b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-csiphy.txt @@ -15,7 +15,8 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", - "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy". + "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", + "qcom,csiphy-v1.2.3", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-ife-csid.txt b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-ife-csid.txt index ecff78ee1b27..0a11bea1fba7 100755 --- a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-ife-csid.txt +++ b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-ife-csid.txt @@ -15,9 +15,10 @@ First Level Node - CAM IFE CSID device - compatible Usage: required Value type: - Definition: Should be "qcom,csid170", "qcom,csid175", "qcom,csid175_200", - "qcom,csid480", "qcom,csid-lite170", "qcom,csid-lite175", - "qcom,csid-lite480" or "qcom,csid-custom480". + Definition: Should be "qcom,csid170", "qcom,csid170_200", "qcom,csid175", + "qcom,csid175_200", "qcom,csid480", "qcom,csid-lite170", + "qcom,csid-lite175", "qcom,csid-lite480" or + "qcom,csid-custom480". - cell-index Usage: required diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-vfe.txt b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-vfe.txt index 2866d67cf5e2..e8df9d4388a4 100755 --- a/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-vfe.txt +++ b/arch/arm64/boot/dts/vendor/qcom/camera/bindings/msm-cam-vfe.txt @@ -18,7 +18,8 @@ Required properties: Value type: Definition: Should specify the compatibility string for matching the driver. e.g. "qcom,vfe480", "qcom,vfe175", "qcom,vfe170", "qcom,vfe175_130", - "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", "qcom,vfe-lite170". + "qcom,vfe170_150", "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", + "qcom,vfe-lite170". - cell-index Usage: required diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi new file mode 100755 index 000000000000..891567bb1042 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi @@ -0,0 +1,670 @@ +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <180>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <180>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + led-flash-src = <&led_flash_triple_rear>; + eeprom-src = <&eeprom_triple_wide>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <180>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + eeprom-src = <&eeprom_tof>; + sensor-position-roll = <0>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3600000 0>; + rgltr-max-voltage = <1800000 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi index 375f8841a274..51727ba40e67 100755 --- a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi @@ -282,6 +282,52 @@ clock-rates = <24000000>; }; + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_bob-supply = <&pm8150a_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rgbleft>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rgbleft>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2", + "CAM_VIO2", + "CAM_VDIG2"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Left (Master) */ qcom,cam-sensor2 { cell-index = <2>; @@ -334,6 +380,52 @@ clock-rates = <24000000>; }; + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vana-supply = <&pm8009_l6>; + cam_bob-supply = <&pm8150a_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rgbright>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rgbright>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA3", + "CAM_VIO3", + "CAM_VDIG3"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Right (Slave) */ qcom,cam-sensor3 { cell-index = <3>; @@ -342,6 +434,7 @@ sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof>; cam_vio-supply = <&pm8009_l7>; cam_bob-supply = <&pm8150a_bob>; cam_vana-supply = <&pm8009_l6>; @@ -503,42 +596,6 @@ rgltr-load-current = <100000>; }; - eeprom_front: qcom,eeprom2 { - cell-index = <2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pm8009_l7>; - cam_vana-supply = <&pm8009_l6>; - cam_vdig-supply = <&pm8009_l3>; - cam_clk-supply = <&titan_top_gdsc>; - cam_vaf-supply = <&pm8150a_l7>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; - rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_active_rst2>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_suspend_rst2>; - gpios = <&tlmm 96 0>, - <&tlmm 78 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; - sensor-position = <1>; - sensor-mode = <0>; - cci-master = <0>; - status = "disabled"; - clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; eeprom_triple_uw: qcom,eeprom6 { cell-index = <6>; @@ -577,40 +634,6 @@ clock-rates = <24000000>; }; - eeprom_tof: qcom,eeprom3 { - cell-index = <3>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pm8009_l7>; - cam_vdig-supply = <&vreg_tof>; - cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - rgltr-min-voltage = <0 3600000 0>; - rgltr-max-voltage = <0 3600000 0>; - rgltr-load-current = <180000 120000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_active_3>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_suspend_3>; - gpios = <&tlmm 97 0>, - <&tlmm 109 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; - sensor-position = <1>; - sensor-mode = <0>; - cci-master = <1>; - status = "disabled"; - clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; /* ET Left (Master) */ qcom,cam-sensor0 { diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi index 1aa64bc1795c..2557ae70469b 100755 --- a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi @@ -34,6 +34,17 @@ status = "ok"; }; + led_flash_hand_track: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + gpios = <&tlmm 118 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "HNDTCKING_LED_EN"; + gpio-req-tbl-delay = <20>; + status = "ok"; + }; + led_flash_triple_rear: qcom,camera-flash@4 { cell-index = <4>; compatible = "qcom,camera-flash"; @@ -486,6 +497,52 @@ clock-rates = <24000000>; }; + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_bob-supply = <&pm8150a_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rgbleft>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rgbleft>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2", + "CAM_VIO2", + "CAM_VDIG2"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Left (Master) */ qcom,cam-sensor2 { cell-index = <2>; @@ -538,6 +595,52 @@ clock-rates = <24000000>; }; + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vana-supply = <&pm8009_l6>; + cam_bob-supply = <&pm8150a_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rgbright>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rgbright>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA3", + "CAM_VIO3", + "CAM_VDIG3"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Right(Slave) */ qcom,cam-sensor3 { cell-index = <3>; @@ -546,6 +649,7 @@ sensor-position-roll = <90>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; + eeprom-src = <&eeprom_tof>; cam_vio-supply = <&pm8009_l7>; cam_bob-supply = <&pm8150a_bob>; cam_vana-supply = <&pm8009_l6>; @@ -597,6 +701,7 @@ sensor-position-roll = <90>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; + led-flash-src = <&led_flash_hand_track>; cam_vio-supply = <&pm8009_l7>; cam_bob-supply = <&pm8150a_bob>; cam_vana-supply = <&pm8009_l6>; @@ -705,42 +810,6 @@ rgltr-load-current = <100000>; }; - eeprom_front: qcom,eeprom2 { - cell-index = <2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pm8009_l7>; - cam_vana-supply = <&pm8009_l6>; - cam_vdig-supply = <&pm8009_l3>; - cam_clk-supply = <&titan_top_gdsc>; - cam_vaf-supply = <&pm8150a_l7>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; - rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; - rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; - rgltr-load-current = <120000 80000 1200000 0 100000>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_active_rst2>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_suspend_rst2>; - gpios = <&tlmm 96 0>, - <&tlmm 78 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; - sensor-position = <1>; - sensor-mode = <0>; - cci-master = <0>; - status = "disabled"; - clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; eeprom_triple_uw: qcom,eeprom6 { cell-index = <6>; @@ -779,41 +848,6 @@ clock-rates = <24000000>; }; - eeprom_tof: qcom,eeprom3 { - cell-index = <3>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pm8009_l7>; - cam_vdig-supply = <&vreg_tof>; - cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - rgltr-min-voltage = <0 3600000 0>; - rgltr-max-voltage = <0 3600000 0>; - rgltr-load-current = <180000 120000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_active_3>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_suspend_3>; - gpios = <&tlmm 97 0>, - <&tlmm 109 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; - sensor-position = <1>; - sensor-mode = <0>; - cci-master = <1>; - status = "disabled"; - clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; - }; - /* ET Left (Master): Combo Mode */ qcom,cam-sensor0 { cell-index = <4>; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi deleted file mode 100755 index 07d398e9e16c..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -&mdss_mdp { - dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p { - qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-t-clk-post = <0x03>; - qcom,mdss-dsi-t-clk-pre = <0x24>; - qcom,mdss-dsi-force-clock-lane-hs; - qcom,mdss-dsi-ext-bridge-mode; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1920>; - qcom,mdss-dsi-panel-height = <1080>; - qcom,mdss-dsi-h-front-porch = <88>; - qcom,mdss-dsi-h-back-porch = <148>; - qcom,mdss-dsi-h-pulse-width = <44>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <36>; - qcom,mdss-dsi-v-front-porch = <4>; - qcom,mdss-dsi-v-pulse-width = <5>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi deleted file mode 100755 index 9dc1a26207f3..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -&mdss_mdp { - dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video { - qcom,mdss-dsi-panel-name = - "hx83112a video mode dsi truly panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <65>; - qcom,mdss-pan-physical-height-dimension = <129>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <42>; - qcom,mdss-dsi-h-back-porch = <42>; - qcom,mdss-dsi-h-pulse-width = <10>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <15>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <3>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 04 B9 83 11 2A - 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54 - 33 - 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08 - 26 FC 01 00 03 15 A3 87 09 - 39 01 00 00 00 00 02 BD 02 - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 03 D2 2C 2C - 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A - CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00 - 28 0A 13 14 00 8A - 39 01 00 00 00 00 02 BD 02 - 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12 - 00 53 - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 04 B6 82 82 E3 - 39 01 00 00 00 00 02 CC 08 - 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01 - 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00 - 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00 - 00 00 00 00 0B 08 82 - 39 01 00 00 00 00 02 BD 01 - 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00 - 81 - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18 - 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 - 18 40 40 01 00 07 06 05 04 03 02 21 20 18 - 18 19 19 18 18 03 03 18 18 18 18 18 18 - 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18 - 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 - 18 40 40 02 03 04 05 06 07 00 01 20 21 18 - 18 18 18 19 19 20 20 18 18 18 18 18 18 - 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 - 39 01 00 00 00 00 02 BD 01 - 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA - AA AA AA AA AA AA AA AA AA AA AA AA AA AA - AA AA AA - 39 01 00 00 00 00 02 BD 02 - 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA - FF FA AA BA AA - 39 01 00 00 00 00 02 BD 03 - 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA - AA AA AA AA AA AA AA AA AA AA AA AA AA AA - AA AA AA - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00 - 32 02 02 00 00 02 02 02 05 14 14 32 B9 23 - B9 08 - 39 01 00 00 00 00 02 BD 01 - 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8 - 0E 01 - 39 01 00 00 00 00 02 BD 02 - 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - 00 04 00 00 00 00 02 00 - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 02 C1 01 - 39 01 00 00 00 00 02 BD 01 - 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 - C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 - 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 - 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 - C6 B8 9C 37 43 3D E5 00 - 39 01 00 00 00 00 02 BD 02 - 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 - C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 - 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 - 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 - C6 B8 9C 37 43 3D E5 00 - 39 01 00 00 00 00 02 BD 03 - 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 - C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 - 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 - 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 - C6 B8 9C 37 43 3D E5 00 - 39 01 00 00 00 00 02 BD 00 - 39 01 00 00 00 00 02 E9 C3 - 39 01 00 00 00 00 03 CB 92 01 - 39 01 00 00 00 00 02 E9 3F - 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00 - 39 01 00 00 00 00 03 51 0F FF - 39 01 00 00 00 00 02 53 24 - 39 01 00 00 00 00 02 55 00 - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 96 00 02 11 00 - 05 01 00 00 32 00 02 29 00]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 32 00 02 28 00 - 05 01 00 00 96 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi deleted file mode 100755 index 6de6c6c4c859..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -&mdss_mdp { - dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video { - qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <52>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <24>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <20>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 04 b9 ff 83 94 - 39 01 00 00 00 00 03 ba 33 83 - 39 01 00 00 00 00 10 b1 6c 12 12 - 37 04 11 f1 80 ec 94 23 80 c0 - d2 18 - 39 01 00 00 00 00 0c b2 00 64 0e - 0d 32 23 08 08 1c 4d 00 - 39 01 00 00 00 00 0d b4 00 ff 03 - 50 03 50 03 50 01 6a 01 6a - 39 01 00 00 00 00 02 bc 07 - 39 01 00 00 00 00 04 bf 41 0e 01 - 39 01 00 00 00 00 1f d3 00 07 00 - 00 00 10 00 32 10 05 00 00 32 - 10 00 00 00 32 10 00 00 00 36 - 03 09 09 37 00 00 37 - 39 01 00 00 00 00 2d d5 02 03 00 - 01 06 07 04 05 20 21 22 23 18 - 18 18 18 18 18 18 18 18 18 18 - 18 18 18 18 18 18 18 18 18 18 - 18 18 18 18 18 24 25 18 18 19 - 19 - 39 01 00 00 00 00 2d d6 05 04 07 - 06 01 00 03 02 23 22 21 20 18 - 18 18 18 18 18 58 58 18 18 18 - 18 18 18 18 18 18 18 18 18 18 - 18 18 18 18 18 25 24 19 19 18 - 18 - 39 01 00 00 00 00 02 cc 09 - 39 01 00 00 00 00 03 c0 30 14 - 39 01 00 00 00 00 05 c7 00 c0 40 c0 - 39 01 00 00 00 00 03 b6 43 43 - 05 01 00 00 c8 00 02 11 00 - 05 01 00 00 0a 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 - 05 01 00 00 00 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <1>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-panel-timings = [ - 79 1a 12 00 3e 42 - 16 1e 15 03 04 00 - ]; - qcom,mdss-dsi-t-clk-post = <0x04>; - qcom,mdss-dsi-t-clk-pre = <0x1b>; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; - qcom,mdss-pan-physical-width-dimension = <59>; - qcom,mdss-pan-physical-height-dimension = <104>; - - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi deleted file mode 100755 index 8a05258d0e43..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -&mdss_mdp { - dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly { - qcom,mdss-dsi-panel-name = - "nt35597 cmd mode dsi truly panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <1>; - qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <131>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x1 0x1>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1e - 15 01 00 00 00 00 02 0b 73 - 15 01 00 00 00 00 02 0c 73 - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f ae - 15 01 00 00 00 00 02 11 b8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5a 00 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 80 - 15 01 00 00 00 00 02 5d 81 - 15 01 00 00 00 00 02 5e 00 - 15 01 00 00 00 00 02 5f 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1c - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0f - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8a - 15 01 00 00 00 00 02 0a 13 - 15 01 00 00 00 00 02 0b 13 - 15 01 00 00 00 00 02 0c 15 - 15 01 00 00 00 00 02 0d 15 - 15 01 00 00 00 00 02 0e 17 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 1c - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0f - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8a - 15 01 00 00 00 00 02 1a 13 - 15 01 00 00 00 00 02 1b 13 - 15 01 00 00 00 00 02 1c 15 - 15 01 00 00 00 00 02 1d 15 - 15 01 00 00 00 00 02 1e 17 - 15 01 00 00 00 00 02 1f 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 e0 00 - 15 01 00 00 00 00 02 dc 21 - 15 01 00 00 00 00 02 dd 22 - 15 01 00 00 00 00 02 de 07 - 15 01 00 00 00 00 02 df 07 - 15 01 00 00 00 00 02 e3 6D - 15 01 00 00 00 00 02 e1 07 - 15 01 00 00 00 00 02 e2 07 - /* UD */ - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - /* CLK */ - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c D8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 7f 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 b3 C0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0a - 15 01 00 00 00 00 02 94 0a - /* Inversion Type */ - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b ff - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9d b0 - 15 01 00 00 00 00 02 9f 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 ec 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VESA DSC PPS settings - * (1440x2560 slide 16H) - */ - 39 01 00 00 00 00 11 c1 09 - 20 00 10 02 00 02 68 01 bb - 00 0a 06 67 04 c5 - - 39 01 00 00 00 00 03 c2 10 f0 - /* C0h = 0x0(2 Port SDC) - * 0x01(1 PortA FBC) - * 0x02(MTK) 0x03(1 PortA VESA) - */ - 15 01 00 00 00 00 02 c0 03 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3b 03 0a 0a - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 e5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 bb 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 fb 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - - qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi deleted file mode 100755 index 2d888cbce876..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi +++ /dev/null @@ -1,226 +0,0 @@ -&mdss_mdp { - dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly { - qcom,mdss-dsi-panel-name = - "nt35597 video mode dsi truly panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <1>; - qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <131>; - qcom,mdss-dsi-dma-schedule-line = <5>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1e - 15 01 00 00 00 00 02 0b 73 - 15 01 00 00 00 00 02 0c 73 - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f aE - 15 01 00 00 00 00 02 11 b8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5a 00 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 80 - 15 01 00 00 00 00 02 5d 81 - 15 01 00 00 00 00 02 5e 00 - 15 01 00 00 00 00 02 5f 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1c - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0f - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8a - 15 01 00 00 00 00 02 0a 13 - 15 01 00 00 00 00 02 0b 13 - 15 01 00 00 00 00 02 0c 15 - 15 01 00 00 00 00 02 0d 15 - 15 01 00 00 00 00 02 0e 17 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 1c - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0f - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8a - 15 01 00 00 00 00 02 1a 13 - 15 01 00 00 00 00 02 1b 13 - 15 01 00 00 00 00 02 1c 15 - 15 01 00 00 00 00 02 1d 15 - 15 01 00 00 00 00 02 1e 17 - 15 01 00 00 00 00 02 1f 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 e0 00 - 15 01 00 00 00 00 02 dc 21 - 15 01 00 00 00 00 02 dd 22 - 15 01 00 00 00 00 02 de 07 - 15 01 00 00 00 00 02 df 07 - 15 01 00 00 00 00 02 e3 6d - 15 01 00 00 00 00 02 e1 07 - 15 01 00 00 00 00 02 e2 07 - /* UD */ - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - /* CLK */ - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 7f 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0a - 15 01 00 00 00 00 02 94 0a - /* Inversion Type */ - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b ff - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9d b0 - 15 01 00 00 00 00 02 9f 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 ec 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VESA DSC PPS settings - * (1440x2560 slide 16H) - */ - 39 01 00 00 00 00 11 c1 09 - 20 00 10 02 00 02 68 01 bb - 00 0a 06 67 04 c5 - - 39 01 00 00 00 00 03 c2 10 f0 - /* C0h = 0x00(2 Port SDC); - * 0x01(1 PortA FBC); - * 0x02(MTK); 0x03(1 PortA VESA) - */ - 15 01 00 00 00 00 02 c0 03 - /* VBP+VSA=,VFP = 10H */ - 39 01 00 00 00 00 04 3b 03 0a 0a - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 e5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 bb 03 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 fb 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi deleted file mode 100755 index cddf9165ff1f..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi +++ /dev/null @@ -1,219 +0,0 @@ -&mdss_mdp { - dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd { - qcom,mdss-dsi-panel-name = - "Dual nt35597 cmd mode dsi truly panel without DSC"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <131>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-jitter = <0x1 0x1>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi deleted file mode 100755 index aff695014114..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -&mdss_mdp { - dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly { - qcom,mdss-dsi-panel-name = - "Dual nt35597 video mode dsi truly panel without DSC"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <131>; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-underflow-color = <0x3ff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-bpp = <24>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 FB 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 FF 24 - 15 01 00 00 00 00 02 FB 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 FF 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 03 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi deleted file mode 100755 index ffefa6a671d6..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -&mdss_mdp { - dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd { - qcom,mdss-dsi-panel-name = - "nt35695b truly fhd command mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,dsi-sec-ctrl-num = <1>; - qcom,dsi-sec-phy-num = <1>; - qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-post-init-delay = <1>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <60>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <2>; - qcom,mdss-dsi-v-front-porch = <12>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = - [15 01 00 00 10 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 03 55 - 15 01 00 00 00 00 02 05 50 - 15 01 00 00 00 00 02 06 a8 - 15 01 00 00 00 00 02 07 ad - 15 01 00 00 00 00 02 08 0c - 15 01 00 00 00 00 02 0b aa - 15 01 00 00 00 00 02 0c aa - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f b3 - 15 01 00 00 00 00 02 11 28 - 15 01 00 00 00 00 02 12 10 - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 4a - 15 01 00 00 00 00 02 15 12 - 15 01 00 00 00 00 02 16 12 - 15 01 00 00 00 00 02 30 01 - 15 01 00 00 00 00 02 72 11 - 15 01 00 00 00 00 02 58 82 - 15 01 00 00 00 00 02 59 00 - 15 01 00 00 00 00 02 5a 02 - 15 01 00 00 00 00 02 5b 00 - 15 01 00 00 00 00 02 5c 82 - 15 01 00 00 00 00 02 5d 80 - 15 01 00 00 00 00 02 5e 02 - 15 01 00 00 00 00 02 5f 00 - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 89 - 15 01 00 00 00 00 02 04 8a - 15 01 00 00 00 00 02 05 0f - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 1c - 15 01 00 00 00 00 02 09 00 - 15 01 00 00 00 00 02 0a 00 - 15 01 00 00 00 00 02 0b 00 - 15 01 00 00 00 00 02 0c 00 - 15 01 00 00 00 00 02 0d 13 - 15 01 00 00 00 00 02 0e 15 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 01 - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 89 - 15 01 00 00 00 00 02 14 8a - 15 01 00 00 00 00 02 15 0f - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 1c - 15 01 00 00 00 00 02 19 00 - 15 01 00 00 00 00 02 1a 00 - 15 01 00 00 00 00 02 1b 00 - 15 01 00 00 00 00 02 1c 00 - 15 01 00 00 00 00 02 1d 13 - 15 01 00 00 00 00 02 1e 15 - 15 01 00 00 00 00 02 1f 17 - 15 01 00 00 00 00 02 20 00 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 55 25 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 93 06 - 15 01 00 00 00 00 02 94 06 - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b 0f - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - 15 01 00 00 00 00 02 b6 21 - 15 01 00 00 00 00 02 b7 22 - 15 01 00 00 00 00 02 b8 07 - 15 01 00 00 00 00 02 b9 07 - 15 01 00 00 00 00 02 ba 22 - 15 01 00 00 00 00 02 bd 20 - 15 01 00 00 00 00 02 be 07 - 15 01 00 00 00 00 02 bf 07 - 15 01 00 00 00 00 02 c1 6d - 15 01 00 00 00 00 02 c4 24 - 15 01 00 00 00 00 02 e3 00 - 15 01 00 00 00 00 02 ec 00 - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bb 10 - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00]; - qcom,mdss-dsi-off-command = [05 01 00 00 14 - 00 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi deleted file mode 100755 index fe84525de197..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi +++ /dev/null @@ -1,177 +0,0 @@ -&mdss_mdp { - dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video { - qcom,mdss-dsi-panel-name = - "nt35695b truly fhd video mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-post-init-delay = <1>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <60>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-v-back-porch = <2>; - qcom,mdss-dsi-v-front-porch = <12>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-on-command = - [15 01 00 00 10 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 03 55 - 15 01 00 00 00 00 02 05 50 - 15 01 00 00 00 00 02 06 a8 - 15 01 00 00 00 00 02 07 ad - 15 01 00 00 00 00 02 08 0c - 15 01 00 00 00 00 02 0b aa - 15 01 00 00 00 00 02 0c aa - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f b3 - 15 01 00 00 00 00 02 11 28 - 15 01 00 00 00 00 02 12 10 - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 4a - 15 01 00 00 00 00 02 15 12 - 15 01 00 00 00 00 02 16 12 - 15 01 00 00 00 00 02 30 01 - 15 01 00 00 00 00 02 72 11 - 15 01 00 00 00 00 02 58 82 - 15 01 00 00 00 00 02 59 00 - 15 01 00 00 00 00 02 5a 02 - 15 01 00 00 00 00 02 5b 00 - 15 01 00 00 00 00 02 5c 82 - 15 01 00 00 00 00 02 5d 80 - 15 01 00 00 00 00 02 5e 02 - 15 01 00 00 00 00 02 5f 00 - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 89 - 15 01 00 00 00 00 02 04 8a - 15 01 00 00 00 00 02 05 0f - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 1c - 15 01 00 00 00 00 02 09 00 - 15 01 00 00 00 00 02 0a 00 - 15 01 00 00 00 00 02 0b 00 - 15 01 00 00 00 00 02 0c 00 - 15 01 00 00 00 00 02 0d 13 - 15 01 00 00 00 00 02 0e 15 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 01 - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 89 - 15 01 00 00 00 00 02 14 8a - 15 01 00 00 00 00 02 15 0f - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 1c - 15 01 00 00 00 00 02 19 00 - 15 01 00 00 00 00 02 1a 00 - 15 01 00 00 00 00 02 1b 00 - 15 01 00 00 00 00 02 1c 00 - 15 01 00 00 00 00 02 1d 13 - 15 01 00 00 00 00 02 1e 15 - 15 01 00 00 00 00 02 1f 17 - 15 01 00 00 00 00 02 20 00 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 55 25 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 93 06 - 15 01 00 00 00 00 02 94 06 - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b 0f - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - 15 01 00 00 00 00 02 b6 21 - 15 01 00 00 00 00 02 b7 22 - 15 01 00 00 00 00 02 b8 07 - 15 01 00 00 00 00 02 b9 07 - 15 01 00 00 00 00 02 ba 22 - 15 01 00 00 00 00 02 bd 20 - 15 01 00 00 00 00 02 be 07 - 15 01 00 00 00 00 02 bf 07 - 15 01 00 00 00 00 02 c1 6d - 15 01 00 00 00 00 02 c4 24 - 15 01 00 00 00 00 02 e3 00 - 15 01 00 00 00 00 02 ec 00 - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bb 03 - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00]; - qcom,mdss-dsi-off-command = [05 01 00 00 - 14 00 02 28 00 05 01 00 00 78 00 - 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi deleted file mode 100755 index d066925a86f2..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -&mdss_mdp { - dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd { - qcom,mdss-dsi-panel-name = - "Dual nt36850 cmd mode dsi truly panel without DSC"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <140>; - qcom,mdss-dsi-h-pulse-width = <20>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <20>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-on-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 36 00 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 03 44 03 e8 - 15 01 00 00 00 00 02 51 ff - 15 01 00 00 00 00 02 53 2c - 15 01 00 00 00 00 02 55 01 - 05 01 00 00 0a 00 02 20 00 - 15 01 00 00 00 00 02 bb 10 - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi deleted file mode 100755 index 11eb3a30d232..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -&mdss_mdp { - dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd { - qcom,mdss-dsi-panel-name = - "Dual s6e3ha3 amoled cmd mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <31>; - qcom,mdss-dsi-v-front-porch = <30>; - qcom,mdss-dsi-v-pulse-width = <8>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 - 39 01 00 00 00 00 05 2a 00 00 05 9f - 39 01 00 00 00 00 05 2b 00 00 09 ff - 39 01 00 00 00 00 03 f0 5a 5a - 39 01 00 00 00 00 02 b0 10 - 39 01 00 00 00 00 02 b5 a0 - 39 01 00 00 00 00 02 c4 03 - 39 01 00 00 00 00 0a - f6 42 57 37 00 aa cc d0 00 00 - 39 01 00 00 00 00 02 f9 03 - 39 01 00 00 00 00 14 - c2 00 00 d8 d8 00 80 2b 05 08 - 0e 07 0b 05 0d 0a 15 13 20 1e - 39 01 00 00 78 00 03 f0 a5 a5 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 53 20 - 39 01 00 00 00 00 02 51 60 - 05 01 00 00 05 00 02 29 00]; - qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 - 05 01 00 00 b4 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a - 39 00 00 00 05 00 03 f1 5a 5a - 39 00 00 00 05 00 03 fc 5a 5a - 39 00 00 00 05 00 02 b0 17 - 39 00 00 00 05 00 02 cb 10 - 39 00 00 00 05 00 02 b0 2d - 39 00 00 00 05 00 02 cb cd - 39 00 00 00 05 00 02 b0 0e - 39 00 00 00 05 00 02 cb 02 - 39 00 00 00 05 00 02 b0 0f - 39 00 00 00 05 00 02 cb 09 - 39 00 00 00 05 00 02 b0 02 - 39 00 00 00 05 00 02 f2 c9 - 39 00 00 00 05 00 02 b0 03 - 39 00 00 00 05 00 02 f2 c0 - 39 00 00 00 05 00 02 b0 03 - 39 00 00 00 05 00 02 f4 aa - 39 00 00 00 05 00 02 b0 08 - 39 00 00 00 05 00 02 b1 30 - 39 00 00 00 05 00 02 b0 09 - 39 00 00 00 05 00 02 b1 0a - 39 00 00 00 05 00 02 b0 0d - 39 00 00 00 05 00 02 b1 10 - 39 00 00 00 05 00 02 b0 00 - 39 00 00 00 05 00 02 f7 03 - 39 00 00 00 05 00 02 fe 30 - 39 01 00 00 05 00 02 fe b0]; - qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a - 39 00 00 00 05 00 03 f1 5a 5a - 39 00 00 00 05 00 03 fc 5a 5a - 39 00 00 00 05 00 02 b0 2d - 39 00 00 00 05 00 02 cb 4d - 39 00 00 00 05 00 02 b0 17 - 39 00 00 00 05 00 02 cb 04 - 39 00 00 00 05 00 02 b0 0e - 39 00 00 00 05 00 02 cb 06 - 39 00 00 00 05 00 02 b0 0f - 39 00 00 00 05 00 02 cb 05 - 39 00 00 00 05 00 02 b0 02 - 39 00 00 00 05 00 02 f2 b8 - 39 00 00 00 05 00 02 b0 03 - 39 00 00 00 05 00 02 f2 80 - 39 00 00 00 05 00 02 b0 03 - 39 00 00 00 05 00 02 f4 8a - 39 00 00 00 05 00 02 b0 08 - 39 00 00 00 05 00 02 b1 10 - 39 00 00 00 05 00 02 b0 09 - 39 00 00 00 05 00 02 b1 0a - 39 00 00 00 05 00 02 b0 0d - 39 00 00 00 05 00 02 b1 80 - 39 00 00 00 05 00 02 b0 00 - 39 00 00 00 05 00 02 f7 03 - 39 00 00 00 05 00 02 fe 30 - 39 01 00 00 05 00 02 fe b0]; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-tx-eot-append; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; - qcom,mdss-pan-physical-width-dimension = <68>; - qcom,mdss-pan-physical-height-dimension = <122>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi deleted file mode 100755 index 8ffa0eb7749d..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&mdss_mdp { - dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd { - qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; - qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-panel-destination = "display_1"; - qcom,mdss-dsi-panel-clockrate = <850000000>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <64>; - qcom,mdss-pan-physical-height-dimension = <117>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <0>; - qcom,mdss-dsi-h-back-porch = <0>; - qcom,mdss-dsi-h-pulse-width = <0>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <0>; - qcom,mdss-dsi-v-front-porch = <0>; - qcom,mdss-dsi-v-pulse-width = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 15 01 00 00 00 00 02 bb 10 - 15 01 00 00 00 00 02 b0 03 - 05 01 00 00 78 00 01 11 - 15 01 00 00 00 00 02 51 ff - 15 01 00 00 00 00 02 53 24 - 15 01 00 00 00 00 02 ff 23 - 15 01 00 00 00 00 02 08 05 - 15 01 00 00 00 00 02 46 90 - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 ff f0 - 15 01 00 00 00 00 02 92 01 - 15 01 00 00 00 00 02 ff 10 - /* enable TE generation */ - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 28 00 01 29]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 10 00 01 28 - 05 01 00 00 40 00 01 10]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi deleted file mode 100755 index 89df5ffd4029..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -&mdss_mdp { - dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { - qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; - qcom,mdss-pan-physical-width-dimension = <71>; - qcom,mdss-pan-physical-height-dimension = <129>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-tx-eot-append; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-jitter = <0x8 0xa>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi deleted file mode 100755 index feb55406288c..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -&mdss_mdp { - dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; - qcom,mdss-pan-physical-width-dimension = <71>; - qcom,mdss-pan-physical-height-dimension = <129>; - qcom,mdss-dsi-tx-eot-append; - - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 10 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi deleted file mode 100755 index c909864db377..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -&mdss_mdp { - dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd { - qcom,mdss-dsi-panel-name = - "Dual Sharp WQHD cmd mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-pan-physical-width-dimension = <68>; - qcom,mdss-pan-physical-height-dimension = <121>; - - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 - 20 00 20 02 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - 15 01 00 00 00 00 02 90 01 - 15 01 00 00 00 00 02 03 00 - 15 01 00 00 00 00 02 58 01 - 15 01 00 00 00 00 02 c9 00 - 15 01 00 00 00 00 02 c0 15 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi deleted file mode 100755 index 37330078b1ff..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -&mdss_mdp { - dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video { - qcom,mdss-dsi-panel-name = - "Dual Sharp wqhd video mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-pan-physical-width-dimension = <68>; - qcom,mdss-pan-physical-height-dimension = <121>; - - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 - 20 00 20 02 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 10 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - 15 01 00 00 00 00 02 90 01 - 15 01 00 00 00 00 02 03 00 - 15 01 00 00 00 00 02 58 01 - 15 01 00 00 00 00 02 c9 00 - 15 01 00 00 00 00 02 c0 15 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - }; - }; - }; -}; - diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi deleted file mode 100755 index 06a95cadbd58..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi +++ /dev/null @@ -1,626 +0,0 @@ -&mdss_mdp { - dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd { - qcom,mdss-dsi-panel-name = - "sharp 1080p 120hz dual dsi cmd mode panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,cmd-sync-wait-broadcast; - qcom,cmd-sync-wait-trigger; - qcom,mdss-tear-check-frame-rate = <12000>; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <28>; - qcom,mdss-dsi-h-back-porch = <4>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <12>; - qcom,mdss-dsi-v-front-porch = <12>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-on-command = - [15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 ba 07 - 15 01 00 00 00 00 02 c0 00 - 15 01 00 00 00 00 02 bb 10 - 15 01 00 00 00 00 02 d9 00 - 15 01 00 00 00 00 02 ef 70 - 15 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c - 15 01 00 00 00 00 02 e9 0e - 15 01 00 00 00 00 02 ea 0c - 15 01 00 00 00 00 02 35 00 - 15 01 00 00 00 00 02 c0 00 - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 59 6a - 15 01 00 00 00 00 02 0b 1b - 15 01 00 00 00 00 02 61 f7 - 15 01 00 00 00 00 02 62 6c - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 04 c8 - 15 01 00 00 00 00 02 05 1a - 15 01 00 00 00 00 02 0d 93 - 15 01 00 00 00 00 02 0e 93 - 15 01 00 00 00 00 02 0f 7e - 15 01 00 00 00 00 02 06 69 - 15 01 00 00 00 00 02 07 bc - 15 01 00 00 00 00 02 10 03 - 15 01 00 00 00 00 02 11 64 - 15 01 00 00 00 00 02 12 5a - 15 01 00 00 00 00 02 13 40 - 15 01 00 00 00 00 02 14 40 - 15 01 00 00 00 00 02 15 00 - 15 01 00 00 00 00 02 33 13 - 15 01 00 00 00 00 02 5a 40 - 15 01 00 00 00 00 02 5b 40 - 15 01 00 00 00 00 02 5e 80 - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 80 - 15 01 00 00 00 00 02 14 80 - 15 01 00 00 00 00 02 01 80 - 15 01 00 00 00 00 02 15 80 - 15 01 00 00 00 00 02 02 80 - 15 01 00 00 00 00 02 16 80 - 15 01 00 00 00 00 02 03 0a - 15 01 00 00 00 00 02 17 0c - 15 01 00 00 00 00 02 04 06 - 15 01 00 00 00 00 02 18 08 - 15 01 00 00 00 00 02 05 80 - 15 01 00 00 00 00 02 19 80 - 15 01 00 00 00 00 02 06 80 - 15 01 00 00 00 00 02 1a 80 - 15 01 00 00 00 00 02 07 80 - 15 01 00 00 00 00 02 1b 80 - 15 01 00 00 00 00 02 08 80 - 15 01 00 00 00 00 02 1c 80 - 15 01 00 00 00 00 02 09 80 - 15 01 00 00 00 00 02 1d 80 - 15 01 00 00 00 00 02 0a 80 - 15 01 00 00 00 00 02 1e 80 - 15 01 00 00 00 00 02 0b 1a - 15 01 00 00 00 00 02 1f 1b - 15 01 00 00 00 00 02 0c 16 - 15 01 00 00 00 00 02 20 17 - 15 01 00 00 00 00 02 0d 1c - 15 01 00 00 00 00 02 21 1d - 15 01 00 00 00 00 02 0e 18 - 15 01 00 00 00 00 02 22 19 - 15 01 00 00 00 00 02 0f 0e - 15 01 00 00 00 00 02 23 10 - 15 01 00 00 00 00 02 10 80 - 15 01 00 00 00 00 02 24 80 - 15 01 00 00 00 00 02 11 80 - 15 01 00 00 00 00 02 25 80 - 15 01 00 00 00 00 02 12 80 - 15 01 00 00 00 00 02 26 80 - 15 01 00 00 00 00 02 13 80 - 15 01 00 00 00 00 02 27 80 - 15 01 00 00 00 00 02 74 ff - 15 01 00 00 00 00 02 75 ff - 15 01 00 00 00 00 02 8d 00 - 15 01 00 00 00 00 02 8e 00 - 15 01 00 00 00 00 02 8f 9c - 15 01 00 00 00 00 02 90 0c - 15 01 00 00 00 00 02 91 0e - 15 01 00 00 00 00 02 d6 00 - 15 01 00 00 00 00 02 d7 20 - 15 01 00 00 00 00 02 d8 00 - 15 01 00 00 00 00 02 d9 88 - 15 01 00 00 00 00 02 e5 05 - 15 01 00 00 00 00 02 e6 10 - 15 01 00 00 00 00 02 54 06 - 15 01 00 00 00 00 02 55 05 - 15 01 00 00 00 00 02 56 04 - 15 01 00 00 00 00 02 58 03 - 15 01 00 00 00 00 02 59 33 - 15 01 00 00 00 00 02 5a 33 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5d 01 - 15 01 00 00 00 00 02 5e 0a - 15 01 00 00 00 00 02 5f 0a - 15 01 00 00 00 00 02 60 0a - 15 01 00 00 00 00 02 61 0a - 15 01 00 00 00 00 02 62 10 - 15 01 00 00 00 00 02 63 01 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 65 00 - 15 01 00 00 00 00 02 ef 00 - 15 01 00 00 00 00 02 f0 00 - 15 01 00 00 00 00 02 6d 20 - 15 01 00 00 00 00 02 66 44 - 15 01 00 00 00 00 02 68 01 - 15 01 00 00 00 00 02 69 00 - 15 01 00 00 00 00 02 67 11 - 15 01 00 00 00 00 02 6a 06 - 15 01 00 00 00 00 02 6b 31 - 15 01 00 00 00 00 02 6c 90 - 15 01 00 00 00 00 02 ab c3 - 15 01 00 00 00 00 02 b1 49 - 15 01 00 00 00 00 02 aa 80 - 15 01 00 00 00 00 02 b0 90 - 15 01 00 00 00 00 02 b2 a4 - 15 01 00 00 00 00 02 b3 00 - 15 01 00 00 00 00 02 b4 23 - 15 01 00 00 00 00 02 b5 00 - 15 01 00 00 00 00 02 b6 00 - 15 01 00 00 00 00 02 b7 00 - 15 01 00 00 00 00 02 b8 00 - 15 01 00 00 00 00 02 b9 00 - 15 01 00 00 00 00 02 ba 00 - 15 01 00 00 00 00 02 bb 00 - 15 01 00 00 00 00 02 bc 00 - 15 01 00 00 00 00 02 bd 00 - 15 01 00 00 00 00 02 be 00 - 15 01 00 00 00 00 02 bf 00 - 15 01 00 00 00 00 02 c0 00 - 15 01 00 00 00 00 02 c7 40 - 15 01 00 00 00 00 02 c9 00 - 15 01 00 00 00 00 02 c1 2a - 15 01 00 00 00 00 02 c2 2a - 15 01 00 00 00 00 02 c3 00 - 15 01 00 00 00 00 02 c4 00 - 15 01 00 00 00 00 02 c5 00 - 15 01 00 00 00 00 02 c6 00 - 15 01 00 00 00 00 02 c8 ab - 15 01 00 00 00 00 02 ca 00 - 15 01 00 00 00 00 02 cb 00 - 15 01 00 00 00 00 02 cc 20 - 15 01 00 00 00 00 02 cd 40 - 15 01 00 00 00 00 02 ce a8 - 15 01 00 00 00 00 02 cf a8 - 15 01 00 00 00 00 02 d0 00 - 15 01 00 00 00 00 02 d1 00 - 15 01 00 00 00 00 02 d2 00 - 15 01 00 00 00 00 02 d3 00 - 15 01 00 00 00 00 02 af 01 - 15 01 00 00 00 00 02 a4 1e - 15 01 00 00 00 00 02 95 41 - 15 01 00 00 00 00 02 96 03 - 15 01 00 00 00 00 02 98 00 - 15 01 00 00 00 00 02 9a 9a - 15 01 00 00 00 00 02 9b 03 - 15 01 00 00 00 00 02 9d 80 - 15 01 00 00 00 00 02 ff 26 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 fa d0 - 15 01 00 00 00 00 02 6b 80 - 15 01 00 00 00 00 02 6c 5c - 15 01 00 00 00 00 02 6d 0c - 15 01 00 00 00 00 02 6e 0e - 15 01 00 00 00 00 02 58 01 - 15 01 00 00 00 00 02 59 15 - 15 01 00 00 00 00 02 5a 01 - 15 01 00 00 00 00 02 5b 00 - 15 01 00 00 00 00 02 5c 01 - 15 01 00 00 00 00 02 5d 2b - 15 01 00 00 00 00 02 74 00 - 15 01 00 00 00 00 02 75 ba - 15 01 00 00 00 00 02 81 0a - 15 01 00 00 00 00 02 4e 81 - 15 01 00 00 00 00 02 4f 83 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 53 4d - 15 01 00 00 00 00 02 54 03 - 15 01 00 00 00 00 02 ff e0 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 b2 81 - 15 01 00 00 00 00 02 62 28 - 15 01 00 00 00 00 02 a2 09 - 15 01 00 00 00 00 02 b3 01 - 15 01 00 00 00 00 02 ed 00 - 15 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 75 00 - 15 01 00 00 00 00 02 76 71 - 15 01 00 00 00 00 02 77 00 - 15 01 00 00 00 00 02 78 84 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 7a a5 - 15 01 00 00 00 00 02 7b 00 - 15 01 00 00 00 00 02 7c bb - 15 01 00 00 00 00 02 7d 00 - 15 01 00 00 00 00 02 7e ce - 15 01 00 00 00 00 02 7f 00 - 15 01 00 00 00 00 02 80 e0 - 15 01 00 00 00 00 02 81 00 - 15 01 00 00 00 00 02 82 ef - 15 01 00 00 00 00 02 83 00 - 15 01 00 00 00 00 02 84 ff - 15 01 00 00 00 00 02 85 01 - 15 01 00 00 00 00 02 86 0b - 15 01 00 00 00 00 02 87 01 - 15 01 00 00 00 00 02 88 38 - 15 01 00 00 00 00 02 89 01 - 15 01 00 00 00 00 02 8a 5b - 15 01 00 00 00 00 02 8b 01 - 15 01 00 00 00 00 02 8c 95 - 15 01 00 00 00 00 02 8d 01 - 15 01 00 00 00 00 02 8e c4 - 15 01 00 00 00 00 02 8f 02 - 15 01 00 00 00 00 02 90 0d - 15 01 00 00 00 00 02 91 02 - 15 01 00 00 00 00 02 92 4a - 15 01 00 00 00 00 02 93 02 - 15 01 00 00 00 00 02 94 4c - 15 01 00 00 00 00 02 95 02 - 15 01 00 00 00 00 02 96 85 - 15 01 00 00 00 00 02 97 02 - 15 01 00 00 00 00 02 98 c3 - 15 01 00 00 00 00 02 99 02 - 15 01 00 00 00 00 02 9a e9 - 15 01 00 00 00 00 02 9b 03 - 15 01 00 00 00 00 02 9c 16 - 15 01 00 00 00 00 02 9d 03 - 15 01 00 00 00 00 02 9e 34 - 15 01 00 00 00 00 02 9f 03 - 15 01 00 00 00 00 02 a0 56 - 15 01 00 00 00 00 02 a2 03 - 15 01 00 00 00 00 02 a3 62 - 15 01 00 00 00 00 02 a4 03 - 15 01 00 00 00 00 02 a5 6c - 15 01 00 00 00 00 02 a6 03 - 15 01 00 00 00 00 02 a7 74 - 15 01 00 00 00 00 02 a9 03 - 15 01 00 00 00 00 02 aa 80 - 15 01 00 00 00 00 02 ab 03 - 15 01 00 00 00 00 02 ac 89 - 15 01 00 00 00 00 02 ad 03 - 15 01 00 00 00 00 02 ae 8b - 15 01 00 00 00 00 02 af 03 - 15 01 00 00 00 00 02 b0 8d - 15 01 00 00 00 00 02 b1 03 - 15 01 00 00 00 00 02 b2 8e - 15 01 00 00 00 00 02 b3 00 - 15 01 00 00 00 00 02 b4 71 - 15 01 00 00 00 00 02 b5 00 - 15 01 00 00 00 00 02 b6 84 - 15 01 00 00 00 00 02 b7 00 - 15 01 00 00 00 00 02 b8 a5 - 15 01 00 00 00 00 02 b9 00 - 15 01 00 00 00 00 02 ba bb - 15 01 00 00 00 00 02 bb 00 - 15 01 00 00 00 00 02 bc ce - 15 01 00 00 00 00 02 bd 00 - 15 01 00 00 00 00 02 be e0 - 15 01 00 00 00 00 02 bf 00 - 15 01 00 00 00 00 02 c0 ef - 15 01 00 00 00 00 02 c1 00 - 15 01 00 00 00 00 02 c2 ff - 15 01 00 00 00 00 02 c3 01 - 15 01 00 00 00 00 02 c4 0b - 15 01 00 00 00 00 02 c5 01 - 15 01 00 00 00 00 02 c6 38 - 15 01 00 00 00 00 02 c7 01 - 15 01 00 00 00 00 02 c8 5b - 15 01 00 00 00 00 02 c9 01 - 15 01 00 00 00 00 02 ca 95 - 15 01 00 00 00 00 02 cb 01 - 15 01 00 00 00 00 02 cc c4 - 15 01 00 00 00 00 02 cd 02 - 15 01 00 00 00 00 02 ce 0d - 15 01 00 00 00 00 02 cf 02 - 15 01 00 00 00 00 02 d0 4a - 15 01 00 00 00 00 02 d1 02 - 15 01 00 00 00 00 02 d2 4c - 15 01 00 00 00 00 02 d3 02 - 15 01 00 00 00 00 02 d4 85 - 15 01 00 00 00 00 02 d5 02 - 15 01 00 00 00 00 02 d6 c3 - 15 01 00 00 00 00 02 d7 02 - 15 01 00 00 00 00 02 d8 e9 - 15 01 00 00 00 00 02 d9 03 - 15 01 00 00 00 00 02 da 16 - 15 01 00 00 00 00 02 db 03 - 15 01 00 00 00 00 02 dc 34 - 15 01 00 00 00 00 02 dd 03 - 15 01 00 00 00 00 02 de 56 - 15 01 00 00 00 00 02 df 03 - 15 01 00 00 00 00 02 e0 62 - 15 01 00 00 00 00 02 e1 03 - 15 01 00 00 00 00 02 e2 6c - 15 01 00 00 00 00 02 e3 03 - 15 01 00 00 00 00 02 e4 74 - 15 01 00 00 00 00 02 e5 03 - 15 01 00 00 00 00 02 e6 80 - 15 01 00 00 00 00 02 e7 03 - 15 01 00 00 00 00 02 e8 89 - 15 01 00 00 00 00 02 e9 03 - 15 01 00 00 00 00 02 ea 8b - 15 01 00 00 00 00 02 eb 03 - 15 01 00 00 00 00 02 ec 8d - 15 01 00 00 00 00 02 ed 03 - 15 01 00 00 00 00 02 ee 8e - 15 01 00 00 00 00 02 ef 00 - 15 01 00 00 00 00 02 f0 71 - 15 01 00 00 00 00 02 f1 00 - 15 01 00 00 00 00 02 f2 84 - 15 01 00 00 00 00 02 f3 00 - 15 01 00 00 00 00 02 f4 a5 - 15 01 00 00 00 00 02 f5 00 - 15 01 00 00 00 00 02 f6 bb - 15 01 00 00 00 00 02 f7 00 - 15 01 00 00 00 00 02 f8 ce - 15 01 00 00 00 00 02 f9 00 - 15 01 00 00 00 00 02 fa e0 - 15 01 00 00 00 00 02 ff 21 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 00 - 15 01 00 00 00 00 02 01 ef - 15 01 00 00 00 00 02 02 00 - 15 01 00 00 00 00 02 03 ff - 15 01 00 00 00 00 02 04 01 - 15 01 00 00 00 00 02 05 0b - 15 01 00 00 00 00 02 06 01 - 15 01 00 00 00 00 02 07 38 - 15 01 00 00 00 00 02 08 01 - 15 01 00 00 00 00 02 09 5b - 15 01 00 00 00 00 02 0a 01 - 15 01 00 00 00 00 02 0b 95 - 15 01 00 00 00 00 02 0c 01 - 15 01 00 00 00 00 02 0d c4 - 15 01 00 00 00 00 02 0e 02 - 15 01 00 00 00 00 02 0f 0d - 15 01 00 00 00 00 02 10 02 - 15 01 00 00 00 00 02 11 4a - 15 01 00 00 00 00 02 12 02 - 15 01 00 00 00 00 02 13 4c - 15 01 00 00 00 00 02 14 02 - 15 01 00 00 00 00 02 15 85 - 15 01 00 00 00 00 02 16 02 - 15 01 00 00 00 00 02 17 c3 - 15 01 00 00 00 00 02 18 02 - 15 01 00 00 00 00 02 19 e9 - 15 01 00 00 00 00 02 1a 03 - 15 01 00 00 00 00 02 1b 16 - 15 01 00 00 00 00 02 1c 03 - 15 01 00 00 00 00 02 1d 34 - 15 01 00 00 00 00 02 1e 03 - 15 01 00 00 00 00 02 1f 56 - 15 01 00 00 00 00 02 20 03 - 15 01 00 00 00 00 02 21 62 - 15 01 00 00 00 00 02 22 03 - 15 01 00 00 00 00 02 23 6c - 15 01 00 00 00 00 02 24 03 - 15 01 00 00 00 00 02 25 74 - 15 01 00 00 00 00 02 26 03 - 15 01 00 00 00 00 02 27 80 - 15 01 00 00 00 00 02 28 03 - 15 01 00 00 00 00 02 29 89 - 15 01 00 00 00 00 02 2a 03 - 15 01 00 00 00 00 02 2b 8b - 15 01 00 00 00 00 02 2d 03 - 15 01 00 00 00 00 02 2f 8d - 15 01 00 00 00 00 02 30 03 - 15 01 00 00 00 00 02 31 8e - 15 01 00 00 00 00 02 32 00 - 15 01 00 00 00 00 02 33 71 - 15 01 00 00 00 00 02 34 00 - 15 01 00 00 00 00 02 35 84 - 15 01 00 00 00 00 02 36 00 - 15 01 00 00 00 00 02 37 a5 - 15 01 00 00 00 00 02 38 00 - 15 01 00 00 00 00 02 39 bb - 15 01 00 00 00 00 02 3a 00 - 15 01 00 00 00 00 02 3b ce - 15 01 00 00 00 00 02 3d 00 - 15 01 00 00 00 00 02 3f e0 - 15 01 00 00 00 00 02 40 00 - 15 01 00 00 00 00 02 41 ef - 15 01 00 00 00 00 02 42 00 - 15 01 00 00 00 00 02 43 ff - 15 01 00 00 00 00 02 44 01 - 15 01 00 00 00 00 02 45 0b - 15 01 00 00 00 00 02 46 01 - 15 01 00 00 00 00 02 47 38 - 15 01 00 00 00 00 02 48 01 - 15 01 00 00 00 00 02 49 5b - 15 01 00 00 00 00 02 4a 01 - 15 01 00 00 00 00 02 4b 95 - 15 01 00 00 00 00 02 4c 01 - 15 01 00 00 00 00 02 4d c4 - 15 01 00 00 00 00 02 4e 02 - 15 01 00 00 00 00 02 4f 0d - 15 01 00 00 00 00 02 50 02 - 15 01 00 00 00 00 02 51 4a - 15 01 00 00 00 00 02 52 02 - 15 01 00 00 00 00 02 53 4c - 15 01 00 00 00 00 02 54 02 - 15 01 00 00 00 00 02 55 85 - 15 01 00 00 00 00 02 56 02 - 15 01 00 00 00 00 02 58 c3 - 15 01 00 00 00 00 02 59 02 - 15 01 00 00 00 00 02 5a e9 - 15 01 00 00 00 00 02 5b 03 - 15 01 00 00 00 00 02 5c 16 - 15 01 00 00 00 00 02 5d 03 - 15 01 00 00 00 00 02 5e 34 - 15 01 00 00 00 00 02 5f 03 - 15 01 00 00 00 00 02 60 56 - 15 01 00 00 00 00 02 61 03 - 15 01 00 00 00 00 02 62 62 - 15 01 00 00 00 00 02 63 03 - 15 01 00 00 00 00 02 64 6c - 15 01 00 00 00 00 02 65 03 - 15 01 00 00 00 00 02 66 74 - 15 01 00 00 00 00 02 67 03 - 15 01 00 00 00 00 02 68 80 - 15 01 00 00 00 00 02 69 03 - 15 01 00 00 00 00 02 6a 89 - 15 01 00 00 00 00 02 6b 03 - 15 01 00 00 00 00 02 6c 8b - 15 01 00 00 00 00 02 6d 03 - 15 01 00 00 00 00 02 6e 8d - 15 01 00 00 00 00 02 6f 03 - 15 01 00 00 00 00 02 70 8e - 15 01 00 00 00 00 02 71 00 - 15 01 00 00 00 00 02 72 71 - 15 01 00 00 00 00 02 73 00 - 15 01 00 00 00 00 02 74 84 - 15 01 00 00 00 00 02 75 00 - 15 01 00 00 00 00 02 76 a5 - 15 01 00 00 00 00 02 77 00 - 15 01 00 00 00 00 02 78 bb - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 7a ce - 15 01 00 00 00 00 02 7b 00 - 15 01 00 00 00 00 02 7c e0 - 15 01 00 00 00 00 02 7d 00 - 15 01 00 00 00 00 02 7e ef - 15 01 00 00 00 00 02 7f 00 - 15 01 00 00 00 00 02 80 ff - 15 01 00 00 00 00 02 81 01 - 15 01 00 00 00 00 02 82 0b - 15 01 00 00 00 00 02 83 01 - 15 01 00 00 00 00 02 84 38 - 15 01 00 00 00 00 02 85 01 - 15 01 00 00 00 00 02 86 5b - 15 01 00 00 00 00 02 87 01 - 15 01 00 00 00 00 02 88 95 - 15 01 00 00 00 00 02 89 01 - 15 01 00 00 00 00 02 8a c4 - 15 01 00 00 00 00 02 8b 02 - 15 01 00 00 00 00 02 8c 0d - 15 01 00 00 00 00 02 8d 02 - 15 01 00 00 00 00 02 8e 4a - 15 01 00 00 00 00 02 8f 02 - 15 01 00 00 00 00 02 90 4c - 15 01 00 00 00 00 02 91 02 - 15 01 00 00 00 00 02 92 85 - 15 01 00 00 00 00 02 93 02 - 15 01 00 00 00 00 02 94 c3 - 15 01 00 00 00 00 02 95 02 - 15 01 00 00 00 00 02 96 e9 - 15 01 00 00 00 00 02 97 03 - 15 01 00 00 00 00 02 98 16 - 15 01 00 00 00 00 02 99 03 - 15 01 00 00 00 00 02 9a 34 - 15 01 00 00 00 00 02 9b 03 - 15 01 00 00 00 00 02 9c 56 - 15 01 00 00 00 00 02 9d 03 - 15 01 00 00 00 00 02 9e 62 - 15 01 00 00 00 00 02 9f 03 - 15 01 00 00 00 00 02 a0 6c - 15 01 00 00 00 00 02 a2 03 - 15 01 00 00 00 00 02 a3 74 - 15 01 00 00 00 00 02 a4 03 - 15 01 00 00 00 00 02 a5 80 - 15 01 00 00 00 00 02 a6 03 - 15 01 00 00 00 00 02 a7 89 - 15 01 00 00 00 00 02 a9 03 - 15 01 00 00 00 00 02 aa 8b - 15 01 00 00 00 00 02 ab 03 - 15 01 00 00 00 00 02 ac 8d - 15 01 00 00 00 00 02 ad 03 - 15 01 00 00 00 00 02 ae 8e - 15 01 00 00 00 00 02 af 00 - 15 01 00 00 00 00 02 b0 71 - 15 01 00 00 00 00 02 b1 00 - 15 01 00 00 00 00 02 b2 84 - 15 01 00 00 00 00 02 b3 00 - 15 01 00 00 00 00 02 b4 a5 - 15 01 00 00 00 00 02 b5 00 - 15 01 00 00 00 00 02 b6 bb - 15 01 00 00 00 00 02 b7 00 - 15 01 00 00 00 00 02 b8 ce - 15 01 00 00 00 00 02 b9 00 - 15 01 00 00 00 00 02 ba e0 - 15 01 00 00 00 00 02 bb 00 - 15 01 00 00 00 00 02 bc ef - 15 01 00 00 00 00 02 bd 00 - 15 01 00 00 00 00 02 be ff - 15 01 00 00 00 00 02 bf 01 - 15 01 00 00 00 00 02 c0 0b - 15 01 00 00 00 00 02 c1 01 - 15 01 00 00 00 00 02 c2 38 - 15 01 00 00 00 00 02 c3 01 - 15 01 00 00 00 00 02 c4 5b - 15 01 00 00 00 00 02 c5 01 - 15 01 00 00 00 00 02 c6 95 - 15 01 00 00 00 00 02 c7 01 - 15 01 00 00 00 00 02 c8 c4 - 15 01 00 00 00 00 02 c9 02 - 15 01 00 00 00 00 02 ca 0d - 15 01 00 00 00 00 02 cb 02 - 15 01 00 00 00 00 02 cc 4a - 15 01 00 00 00 00 02 cd 02 - 15 01 00 00 00 00 02 ce 4c - 15 01 00 00 00 00 02 cf 02 - 15 01 00 00 00 00 02 d0 85 - 15 01 00 00 00 00 02 d1 02 - 15 01 00 00 00 00 02 d2 c3 - 15 01 00 00 00 00 02 d3 02 - 15 01 00 00 00 00 02 d4 e9 - 15 01 00 00 00 00 02 d5 03 - 15 01 00 00 00 00 02 d6 16 - 15 01 00 00 00 00 02 d7 03 - 15 01 00 00 00 00 02 d8 34 - 15 01 00 00 00 00 02 d9 03 - 15 01 00 00 00 00 02 da 56 - 15 01 00 00 00 00 02 db 03 - 15 01 00 00 00 00 02 dc 62 - 15 01 00 00 00 00 02 dd 03 - 15 01 00 00 00 00 02 de 6c - 15 01 00 00 00 00 02 df 03 - 15 01 00 00 00 00 02 e0 74 - 15 01 00 00 00 00 02 e1 03 - 15 01 00 00 00 00 02 e2 80 - 15 01 00 00 00 00 02 e3 03 - 15 01 00 00 00 00 02 e4 89 - 15 01 00 00 00 00 02 e5 03 - 15 01 00 00 00 00 02 e6 8b - 15 01 00 00 00 00 02 e7 03 - 15 01 00 00 00 00 02 e8 8d - 15 01 00 00 00 00 02 e9 03 - 15 01 00 00 00 00 02 ea 8e - 15 01 00 00 00 00 02 FF 10 - 05 01 00 00 00 00 01 29]; - qcom,mdss-dsi-off-command = - [15 01 00 00 00 00 02 ff 10 - 05 01 00 00 10 00 01 28 - 15 01 00 00 00 00 02 b0 00 - 05 01 00 00 40 00 01 10 - 15 01 00 00 00 00 02 4f 01]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi deleted file mode 100755 index f62ce3b9d7b5..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi +++ /dev/null @@ -1,347 +0,0 @@ -&mdss_mdp { - dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { - qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-panel-mode-switch; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-t-clk-post = <0x03>; - qcom,mdss-dsi-t-clk-pre = <0x27>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,panel-ack-disabled; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <100>; - qcom,mdss-dsi-v-front-porch = <100>; - qcom,mdss-dsi-v-pulse-width = <40>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-cmd-mode; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = - [00 21 09 09 24 23 08 08 08 03 04 00]; - qcom,mdss-dsi-on-command = - [29 01 00 00 00 00 02 b0 03 - 05 01 00 00 0a 00 01 00 - /* Soft reset, wait 10ms */ - 15 01 00 00 0a 00 02 3a 77 - /* Set Pixel format (24 bpp) */ - 39 01 00 00 0a 00 05 2a 00 00 04 ff - /* Set Column address */ - 39 01 00 00 0a 00 05 2b 00 00 05 9f - /* Set page address */ - 15 01 00 00 0a 00 02 35 00 - /* Set tear on */ - 39 01 00 00 0a 00 03 44 00 00 - /* Set tear scan line */ - 15 01 00 00 0a 00 02 51 ff - /* write display brightness */ - 15 01 00 00 0a 00 02 53 24 - /* write control brightness */ - 15 01 00 00 0a 00 02 55 00 - /* CABC brightness */ - 05 01 00 00 78 00 01 11 - /* exit sleep mode, wait 120ms */ - 05 01 00 00 10 00 01 29]; - - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,cmd-to-video-mode-switch-commands = [ - 39 01 00 00 00 00 03 b0 a5 00 - 07 01 00 00 00 00 02 01 00 - 39 01 00 00 00 00 06 b2 00 5d 04 80 49 - 15 01 00 00 00 00 02 3d 10 - 15 01 00 00 00 00 02 36 00 - 15 01 00 00 00 00 02 55 0c - ]; - qcom,cmd-to-video-mode-switch-commands-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <100>; - qcom,mdss-dsi-v-front-porch = <100>; - qcom,mdss-dsi-v-pulse-width = <40>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-video-mode; - qcom,mdss-dsi-panel-timings = - [00 21 09 09 24 23 08 08 08 03 04 00]; - qcom,mdss-dsi-on-command = - [29 01 00 00 00 00 02 b0 03 - 05 01 00 00 0a 00 01 00 - /* Soft reset, wait 10ms */ - 15 01 00 00 0a 00 02 3a 77 - /* Set Pixel format (24 bpp) */ - 39 01 00 00 0a 00 05 2a 00 00 04 ff - /* Set Column address */ - 39 01 00 00 0a 00 05 2b 00 00 05 9f - /* Set page address */ - 15 01 00 00 0a 00 02 35 00 - /* Set tear on */ - 39 01 00 00 0a 00 03 44 00 00 - /* Set tear scan line */ - 15 01 00 00 0a 00 02 51 ff - /* write display brightness */ - 15 01 00 00 0a 00 02 53 24 - /* write control brightness */ - 15 01 00 00 0a 00 02 55 00 - /* CABC brightness */ - 05 01 00 00 78 00 01 11 - /* exit sleep mode, wait 120ms */ - 05 01 00 00 10 00 01 29]; - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,video-to-cmd-mode-switch-commands = [ - 39 01 00 00 00 00 03 b0 a5 00 - 07 01 00 00 00 00 02 01 00 - 39 01 00 00 00 00 06 b2 00 5d 04 80 49 - 15 01 00 00 00 00 02 3d 11 - 15 01 00 00 00 00 02 36 00 - 15 01 00 00 00 00 02 55 0b - ]; - qcom,video-to-cmd-mode-switch-commands-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <100>; - qcom,mdss-dsi-v-front-porch = <100>; - qcom,mdss-dsi-v-pulse-width = <40>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = - [00 21 09 09 24 23 08 08 08 03 04 00]; - qcom,mdss-dsi-on-command = - [29 01 00 00 00 00 02 b0 03 - 05 01 00 00 0a 00 01 00 - /* Soft reset, wait 10ms */ - 15 01 00 00 0a 00 02 3a 77 - /* Set Pixel format (24 bpp) */ - 39 01 00 00 0a 00 05 2a 00 00 04 ff - /* Set Column address */ - 39 01 00 00 0a 00 05 2b 00 00 05 9f - /* Set page address */ - 15 01 00 00 0a 00 02 35 00 - /* Set tear on */ - 39 01 00 00 0a 00 03 44 00 00 - /* Set tear scan line */ - 15 01 00 00 0a 00 02 51 ff - /* write display brightness */ - 15 01 00 00 0a 00 02 53 24 - /* write control brightness */ - 15 01 00 00 0a 00 02 55 00 - /* CABC brightness */ - 05 01 00 00 78 00 01 11 - /* exit sleep mode, wait 120ms */ - 05 01 00 00 10 00 01 29]; - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@3 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <460>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <100>; - qcom,mdss-dsi-v-front-porch = <740>; - qcom,mdss-dsi-v-pulse-width = <40>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = - [00 21 09 09 24 23 08 08 08 03 04 00]; - qcom,mdss-dsi-on-command = - [29 01 00 00 00 00 02 b0 03 - 05 01 00 00 0a 00 01 00 - /* Soft reset, wait 10ms */ - 15 01 00 00 0a 00 02 3a 77 - /* Set Pixel format (24 bpp) */ - 39 01 00 00 0a 00 05 2a 00 00 04 ff - /* Set Column address */ - 39 01 00 00 0a 00 05 2b 00 00 05 9f - /* Set page address */ - 15 01 00 00 0a 00 02 35 00 - /* Set tear on */ - 39 01 00 00 0a 00 03 44 00 00 - /* Set tear scan line */ - 15 01 00 00 0a 00 02 51 ff - /* write display brightness */ - 15 01 00 00 0a 00 02 53 24 - /* write control brightness */ - 15 01 00 00 0a 00 02 55 00 - /* CABC brightness */ - 05 01 00 00 78 00 01 11 - /* exit sleep mode, wait 120ms */ - 05 01 00 00 10 00 01 29]; - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@4 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <840>; - qcom,mdss-dsi-h-pulse-width = <40>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <100>; - qcom,mdss-dsi-v-front-porch = <1380>; - qcom,mdss-dsi-v-pulse-width = <40>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = - [00 21 09 09 24 23 08 08 08 03 04 00]; - qcom,mdss-dsi-on-command = - [29 01 00 00 00 00 02 b0 03 - 05 01 00 00 0a 00 01 00 - /* Soft reset, wait 10ms */ - 15 01 00 00 0a 00 02 3a 77 - /* Set Pixel format (24 bpp) */ - 39 01 00 00 0a 00 05 2a 00 00 04 ff - /* Set Column address */ - 39 01 00 00 0a 00 05 2b 00 00 05 9f - /* Set page address */ - 15 01 00 00 0a 00 02 35 00 - /* Set tear on */ - 39 01 00 00 0a 00 03 44 00 00 - /* Set tear scan line */ - 15 01 00 00 0a 00 02 51 ff - /* write display brightness */ - 15 01 00 00 0a 00 02 53 24 - /* write control brightness */ - 15 01 00 00 0a 00 02 55 00 - /* CABC brightness */ - 05 01 00 00 78 00 01 11 - /* exit sleep mode, wait 120ms */ - 05 01 00 00 10 00 01 29]; - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi deleted file mode 100755 index 310ce40cd902..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi +++ /dev/null @@ -1,474 +0,0 @@ -&mdss_mdp { - dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { - qcom,mdss-dsi-panel-name = - "Simulator cmd mode DSC3:1 10bit dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <30>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,panel-ack-disabled; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1e - 15 01 00 00 00 00 02 0b 73 - 15 01 00 00 00 00 02 0c 73 - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f aE - 15 01 00 00 00 00 02 11 b8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5a 00 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 80 - 15 01 00 00 00 00 02 5d 81 - 15 01 00 00 00 00 02 5e 00 - 15 01 00 00 00 00 02 5f 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1c - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0f - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8a - 15 01 00 00 00 00 02 0a 13 - 15 01 00 00 00 00 02 0b 13 - 15 01 00 00 00 00 02 0c 15 - 15 01 00 00 00 00 02 0d 15 - 15 01 00 00 00 00 02 0e 17 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 1c - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0f - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8a - 15 01 00 00 00 00 02 1a 13 - 15 01 00 00 00 00 02 1b 13 - 15 01 00 00 00 00 02 1c 15 - 15 01 00 00 00 00 02 1d 15 - 15 01 00 00 00 00 02 1e 17 - 15 01 00 00 00 00 02 1f 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 e0 00 - 15 01 00 00 00 00 02 dc 21 - 15 01 00 00 00 00 02 dd 22 - 15 01 00 00 00 00 02 de 07 - 15 01 00 00 00 00 02 df 07 - 15 01 00 00 00 00 02 e3 6d - 15 01 00 00 00 00 02 e1 07 - 15 01 00 00 00 00 02 e2 07 - /* UD */ - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - /* CLK */ - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 7f 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0a - 15 01 00 00 00 00 02 94 0a - /* Inversion Type */ - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b ff - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9d b0 - 15 01 00 00 00 00 02 9f 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 ec 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VESA DSC PPS settings - * (1440x2560 slide 16H) - */ - 39 01 00 00 00 00 11 c1 09 - 20 00 10 02 00 02 68 01 bb - 00 0a 06 67 04 c5 - - 39 01 00 00 00 00 03 c2 10 f0 - /* C0h = 0x0(2 Port SDC) - * 0x01(1 PortA FBC) - * 0x02(MTK) 0x03(1 PortA VESA) - */ - 15 01 00 00 00 00 02 c0 03 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3b 03 0a 0a - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 e5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 bb 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 fb 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - - qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <10>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <0>; - qcom,mdss-dsi-h-back-porch = <0>; - qcom,mdss-dsi-h-pulse-width = <0>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <0>; - qcom,mdss-dsi-v-front-porch = <0>; - qcom,mdss-dsi-v-pulse-width = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 15 01 00 00 00 00 02 bb 10 - 15 01 00 00 00 00 02 b0 03 - 05 01 00 00 78 00 01 11 - 15 01 00 00 00 00 02 51 ff - 15 01 00 00 00 00 02 53 24 - 15 01 00 00 00 00 02 ff 23 - 15 01 00 00 00 00 02 08 05 - 15 01 00 00 00 00 02 46 90 - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 ff f0 - 15 01 00 00 00 00 02 92 01 - 15 01 00 00 00 00 02 ff 10 - /* enable TE generation */ - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 28 00 01 29]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 10 00 01 28 - 05 01 00 00 40 00 01 10]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <10>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1e - 15 01 00 00 00 00 02 0b 73 - 15 01 00 00 00 00 02 0c 73 - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f aE - 15 01 00 00 00 00 02 11 b8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5a 00 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 80 - 15 01 00 00 00 00 02 5d 81 - 15 01 00 00 00 00 02 5e 00 - 15 01 00 00 00 00 02 5f 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1c - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0f - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8a - 15 01 00 00 00 00 02 0a 13 - 15 01 00 00 00 00 02 0b 13 - 15 01 00 00 00 00 02 0c 15 - 15 01 00 00 00 00 02 0d 15 - 15 01 00 00 00 00 02 0e 17 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 1c - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0f - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8a - 15 01 00 00 00 00 02 1a 13 - 15 01 00 00 00 00 02 1b 13 - 15 01 00 00 00 00 02 1c 15 - 15 01 00 00 00 00 02 1d 15 - 15 01 00 00 00 00 02 1e 17 - 15 01 00 00 00 00 02 1f 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 e0 00 - 15 01 00 00 00 00 02 dc 21 - 15 01 00 00 00 00 02 dd 22 - 15 01 00 00 00 00 02 de 07 - 15 01 00 00 00 00 02 df 07 - 15 01 00 00 00 00 02 e3 6d - 15 01 00 00 00 00 02 e1 07 - 15 01 00 00 00 00 02 e2 07 - /* UD */ - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - /* CLK */ - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 7f 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0a - 15 01 00 00 00 00 02 94 0a - /* Inversion Type */ - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b ff - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9d b0 - 15 01 00 00 00 00 02 9f 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 ec 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VESA DSC PPS settings - * (1440x2560 slide 16H) - */ - 39 01 00 00 00 00 11 c1 09 - 20 00 10 02 00 02 68 01 bb - 00 0a 06 67 04 c5 - - 39 01 00 00 00 00 03 c2 10 f0 - /* C0h = 0x0(2 Port SDC) - * 0x01(1 PortA FBC) - * 0x02(MTK) 0x03(1 PortA VESA) - */ - 15 01 00 00 00 00 02 c0 03 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3b 03 0a 0a - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 e5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 bb 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 fb 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - - qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <10>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi deleted file mode 100755 index ef40a2e7b3e6..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi +++ /dev/null @@ -1,280 +0,0 @@ -&mdss_mdp { - dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { - qcom,mdss-dsi-panel-name = - "Simulator cmd mode DSC 3.75:1 dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,panel-ack-disabled; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 ff 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1e - 15 01 00 00 00 00 02 0b 73 - 15 01 00 00 00 00 02 0c 73 - 15 01 00 00 00 00 02 0e b0 - 15 01 00 00 00 00 02 0f aE - 15 01 00 00 00 00 02 11 b8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5a 00 - 15 01 00 00 00 00 02 5b 01 - 15 01 00 00 00 00 02 5c 80 - 15 01 00 00 00 00 02 5d 81 - 15 01 00 00 00 00 02 5e 00 - 15 01 00 00 00 00 02 5f 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1c - 15 01 00 00 00 00 02 01 0b - 15 01 00 00 00 00 02 02 0c - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0f - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8a - 15 01 00 00 00 00 02 0a 13 - 15 01 00 00 00 00 02 0b 13 - 15 01 00 00 00 00 02 0c 15 - 15 01 00 00 00 00 02 0d 15 - 15 01 00 00 00 00 02 0e 17 - 15 01 00 00 00 00 02 0f 17 - 15 01 00 00 00 00 02 10 1c - 15 01 00 00 00 00 02 11 0b - 15 01 00 00 00 00 02 12 0c - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0f - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8a - 15 01 00 00 00 00 02 1a 13 - 15 01 00 00 00 00 02 1b 13 - 15 01 00 00 00 00 02 1c 15 - 15 01 00 00 00 00 02 1d 15 - 15 01 00 00 00 00 02 1e 17 - 15 01 00 00 00 00 02 1f 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6d - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 e0 00 - 15 01 00 00 00 00 02 dc 21 - 15 01 00 00 00 00 02 dd 22 - 15 01 00 00 00 00 02 de 07 - 15 01 00 00 00 00 02 df 07 - 15 01 00 00 00 00 02 e3 6d - 15 01 00 00 00 00 02 e1 07 - 15 01 00 00 00 00 02 e2 07 - /* UD */ - 15 01 00 00 00 00 02 29 d8 - 15 01 00 00 00 00 02 2a 2a - /* CLK */ - 15 01 00 00 00 00 02 4b 03 - 15 01 00 00 00 00 02 4c 11 - 15 01 00 00 00 00 02 4d 10 - 15 01 00 00 00 00 02 4e 01 - 15 01 00 00 00 00 02 4f 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5b 43 - 15 01 00 00 00 00 02 5c 00 - 15 01 00 00 00 00 02 5f 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7a 80 - 15 01 00 00 00 00 02 7b 91 - 15 01 00 00 00 00 02 7c d8 - 15 01 00 00 00 00 02 7d 60 - 15 01 00 00 00 00 02 7f 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 b3 c0 - 15 01 00 00 00 00 02 b4 00 - 15 01 00 00 00 00 02 b5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0a - 15 01 00 00 00 00 02 94 0a - /* Inversion Type */ - 15 01 00 00 00 00 02 8a 00 - 15 01 00 00 00 00 02 9b ff - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9d b0 - 15 01 00 00 00 00 02 9f 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 ec 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VESA DSC PPS settings - * (1440x2560 slide 16H) - */ - 39 01 00 00 00 00 11 c1 09 - 20 00 10 02 00 02 68 01 bb - 00 0a 06 67 04 c5 - - 39 01 00 00 00 00 03 c2 10 f0 - /* C0h = 0x0(2 Port SDC) - * 0x01(1 PortA FBC) - * 0x02(MTK) 0x03(1 PortA VESA) - */ - 15 01 00 00 00 00 02 c0 03 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3b 03 0a 0a - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 e5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 bb 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 fb 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - - qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <0>; - qcom,mdss-dsi-h-back-porch = <0>; - qcom,mdss-dsi-h-pulse-width = <0>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <0>; - qcom,mdss-dsi-v-front-porch = <0>; - qcom,mdss-dsi-v-pulse-width = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 15 01 00 00 00 00 02 bb 10 - 15 01 00 00 00 00 02 b0 03 - 05 01 00 00 78 00 01 11 - 15 01 00 00 00 00 02 51 ff - 15 01 00 00 00 00 02 53 24 - 15 01 00 00 00 00 02 ff 23 - 15 01 00 00 00 00 02 08 05 - 15 01 00 00 00 00 02 46 90 - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 ff f0 - 15 01 00 00 00 00 02 92 01 - 15 01 00 00 00 00 02 ff 10 - /* enable TE generation */ - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 28 00 01 29]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 10 00 01 28 - 05 01 00 00 40 00 01 10]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi deleted file mode 100755 index 5f4be88fb88f..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -&mdss_mdp { - dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { - qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,cmd-sync-wait-broadcast; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-hor-line-idle = <0 40 256>, - <40 120 128>, - <120 240 64>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,panel-ack-disabled; - qcom,mdss-dsi-qsync-min-refresh-rate = <45>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <28>; - qcom,mdss-dsi-h-back-porch = <4>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <12>; - qcom,mdss-dsi-v-front-porch = <12>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-on-command = - [/* exit sleep mode, wait 0ms */ - 05 01 00 00 00 00 01 29]; - /* Set display on, wait 16ms */ - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 00 00 02 28 00 - 05 01 00 00 00 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_hs_mode"; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <1280>; - qcom,mdss-dsi-panel-height = <1440>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <44>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = - [/* exit sleep mode, wait 0ms */ - 05 01 00 00 00 00 01 29]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 00 00 02 28 00 - 05 01 00 00 00 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_hs_mode"; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <40>; - qcom,mdss-dsi-on-command = - [/* exit sleep mode, wait 0ms */ - 05 01 00 00 00 00 01 29]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 00 00 02 28 00 - 05 01 00 00 00 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi deleted file mode 100755 index 87b4a76a3a96..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ /dev/null @@ -1,327 +0,0 @@ -&mdss_mdp { - dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { - qcom,mdss-dsi-panel-name = - "Sim dual cmd mode DSC 3.75:1 dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,cmd-sync-wait-broadcast; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-hor-line-idle = <0 40 256>, - <40 120 128>, - <120 240 64>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,panel-ack-disabled; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <3840>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <32>; - qcom,mdss-dsc-slice-width = <1080>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <100>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-on-command = [ - /* CMD2_P0 */ - 15 01 00 00 00 00 02 FF 20 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 01 - 15 01 00 00 00 00 02 01 55 - 15 01 00 00 00 00 02 02 45 - 15 01 00 00 00 00 02 05 40 - 15 01 00 00 00 00 02 06 19 - 15 01 00 00 00 00 02 07 1E - 15 01 00 00 00 00 02 0B 73 - 15 01 00 00 00 00 02 0C 73 - 15 01 00 00 00 00 02 0E B0 - 15 01 00 00 00 00 02 0F AE - 15 01 00 00 00 00 02 11 B8 - 15 01 00 00 00 00 02 13 00 - 15 01 00 00 00 00 02 58 80 - 15 01 00 00 00 00 02 59 01 - 15 01 00 00 00 00 02 5A 00 - 15 01 00 00 00 00 02 5B 01 - 15 01 00 00 00 00 02 5C 80 - 15 01 00 00 00 00 02 5D 81 - 15 01 00 00 00 00 02 5E 00 - 15 01 00 00 00 00 02 5F 01 - 15 01 00 00 00 00 02 72 31 - 15 01 00 00 00 00 02 68 03 - /* CMD2_P4 */ - 15 01 00 00 00 00 02 ff 24 - 15 01 00 00 00 00 02 fb 01 - 15 01 00 00 00 00 02 00 1C - 15 01 00 00 00 00 02 01 0B - 15 01 00 00 00 00 02 02 0C - 15 01 00 00 00 00 02 03 01 - 15 01 00 00 00 00 02 04 0F - 15 01 00 00 00 00 02 05 10 - 15 01 00 00 00 00 02 06 10 - 15 01 00 00 00 00 02 07 10 - 15 01 00 00 00 00 02 08 89 - 15 01 00 00 00 00 02 09 8A - 15 01 00 00 00 00 02 0A 13 - 15 01 00 00 00 00 02 0B 13 - 15 01 00 00 00 00 02 0C 15 - 15 01 00 00 00 00 02 0D 15 - 15 01 00 00 00 00 02 0E 17 - 15 01 00 00 00 00 02 0F 17 - 15 01 00 00 00 00 02 10 1C - 15 01 00 00 00 00 02 11 0B - 15 01 00 00 00 00 02 12 0C - 15 01 00 00 00 00 02 13 01 - 15 01 00 00 00 00 02 14 0F - 15 01 00 00 00 00 02 15 10 - 15 01 00 00 00 00 02 16 10 - 15 01 00 00 00 00 02 17 10 - 15 01 00 00 00 00 02 18 89 - 15 01 00 00 00 00 02 19 8A - 15 01 00 00 00 00 02 1A 13 - 15 01 00 00 00 00 02 1B 13 - 15 01 00 00 00 00 02 1C 15 - 15 01 00 00 00 00 02 1D 15 - 15 01 00 00 00 00 02 1E 17 - 15 01 00 00 00 00 02 1F 17 - /* STV */ - 15 01 00 00 00 00 02 20 40 - 15 01 00 00 00 00 02 21 01 - 15 01 00 00 00 00 02 22 00 - 15 01 00 00 00 00 02 23 40 - 15 01 00 00 00 00 02 24 40 - 15 01 00 00 00 00 02 25 6D - 15 01 00 00 00 00 02 26 40 - 15 01 00 00 00 00 02 27 40 - /* Vend */ - 15 01 00 00 00 00 02 E0 00 - 15 01 00 00 00 00 02 DC 21 - 15 01 00 00 00 00 02 DD 22 - 15 01 00 00 00 00 02 DE 07 - 15 01 00 00 00 00 02 DF 07 - 15 01 00 00 00 00 02 E3 6D - 15 01 00 00 00 00 02 E1 07 - 15 01 00 00 00 00 02 E2 07 - /* UD */ - 15 01 00 00 00 00 02 29 D8 - 15 01 00 00 00 00 02 2A 2A - /* CLK */ - 15 01 00 00 00 00 02 4B 03 - 15 01 00 00 00 00 02 4C 11 - 15 01 00 00 00 00 02 4D 10 - 15 01 00 00 00 00 02 4E 01 - 15 01 00 00 00 00 02 4F 01 - 15 01 00 00 00 00 02 50 10 - 15 01 00 00 00 00 02 51 00 - 15 01 00 00 00 00 02 52 80 - 15 01 00 00 00 00 02 53 00 - 15 01 00 00 00 00 02 56 00 - 15 01 00 00 00 00 02 54 07 - 15 01 00 00 00 00 02 58 07 - 15 01 00 00 00 00 02 55 25 - /* Reset XDONB */ - 15 01 00 00 00 00 02 5B 43 - 15 01 00 00 00 00 02 5C 00 - 15 01 00 00 00 00 02 5F 73 - 15 01 00 00 00 00 02 60 73 - 15 01 00 00 00 00 02 63 22 - 15 01 00 00 00 00 02 64 00 - 15 01 00 00 00 00 02 67 08 - 15 01 00 00 00 00 02 68 04 - /* Resolution:1440x2560*/ - 15 01 00 00 00 00 02 72 02 - /* mux */ - 15 01 00 00 00 00 02 7A 80 - 15 01 00 00 00 00 02 7B 91 - 15 01 00 00 00 00 02 7C D8 - 15 01 00 00 00 00 02 7D 60 - 15 01 00 00 00 00 02 7F 15 - 15 01 00 00 00 00 02 75 15 - /* ABOFF */ - 15 01 00 00 00 00 02 B3 C0 - 15 01 00 00 00 00 02 B4 00 - 15 01 00 00 00 00 02 B5 00 - /* Source EQ */ - 15 01 00 00 00 00 02 78 00 - 15 01 00 00 00 00 02 79 00 - 15 01 00 00 00 00 02 80 00 - 15 01 00 00 00 00 02 83 00 - /* FP BP */ - 15 01 00 00 00 00 02 93 0A - 15 01 00 00 00 00 02 94 0A - /* Inversion Type */ - 15 01 00 00 00 00 02 8A 00 - 15 01 00 00 00 00 02 9B FF - /* IMGSWAP =1 @PortSwap=1 */ - 15 01 00 00 00 00 02 9D B0 - 15 01 00 00 00 00 02 9F 63 - 15 01 00 00 00 00 02 98 10 - /* FRM */ - 15 01 00 00 00 00 02 EC 00 - /* CMD1 */ - 15 01 00 00 00 00 02 ff 10 - /* VBP+VSA=,VFP = 10H */ - 15 01 00 00 00 00 04 3B 03 0A 0A - /* FTE on */ - 15 01 00 00 00 00 02 35 00 - /* EN_BK =1(auto black) */ - 15 01 00 00 00 00 02 E5 01 - /* CMD mode(10) VDO mode(03) */ - 15 01 00 00 00 00 02 BB 10 - /* Non Reload MTP */ - 15 01 00 00 00 00 02 FB 01 - /* SlpOut + DispOn */ - 05 01 00 00 78 00 02 11 00 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <2520>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <30>; - qcom,mdss-dsi-h-back-porch = <100>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <7>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <120>; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 11 91 09 20 00 20 02 - 00 03 1c 04 21 00 - 0f 03 19 01 97 - 39 01 00 00 00 00 03 92 10 f0 - 15 01 00 00 00 00 02 90 03 - 15 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 04 - 15 01 00 00 00 00 02 c0 03 - 39 01 00 00 00 00 06 f0 55 aa 52 08 07 - 15 01 00 00 00 00 02 ef 01 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 15 01 00 00 00 00 02 b4 01 - 15 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 01 - 39 01 00 00 00 00 05 ff aa 55 a5 80 - 15 01 00 00 00 00 02 6f 01 - 15 01 00 00 00 00 02 f3 10 - 39 01 00 00 00 00 05 ff aa 55 a5 00 - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <1080>; - qcom,mdss-dsc-slice-width = <1260>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <10>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi deleted file mode 100755 index 3bee9f6f104d..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -&mdss_mdp { - dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { - qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-panel-broadcast-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>; - qcom,panel-ack-disabled; - qcom,mdss-dsi-qsync-min-refresh-rate = <45>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1280>; - qcom,mdss-dsi-panel-height = <1440>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <44>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = - [05 01 00 00 32 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi deleted file mode 100755 index e9d31359ed5b..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -&mdss_mdp { - dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { - qcom,mdss-dsi-panel-name = - "sim hd command mode secondary dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-sec-ctrl-num = <1>; - qcom,dsi-sec-phy-num = <1>; - qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,panel-ack-disabled; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-post-init-delay = <1>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-h-front-porch = <120>; - qcom,mdss-dsi-h-back-porch = <60>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <2>; - qcom,mdss-dsi-v-front-porch = <12>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - - qcom,mdss-dsi-on-command = [ - /* sleep out + delay 120ms */ - 05 01 00 00 78 00 01 11 - /* display on + delay 120ms */ - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 78 00 02 28 00 - 05 01 00 00 78 00 02 10 00 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi deleted file mode 100755 index 5a2ac01716d3..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -&mdss_mdp { - dsi_sim_vid: qcom,mdss_dsi_sim_video { - qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-t-clk-post = <0x04>; - qcom,mdss-dsi-t-clk-pre = <0x1b>; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>; - qcom,panel-ack-disabled; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <640>; - qcom,mdss-dsi-panel-height = <480>; - qcom,mdss-dsi-h-front-porch = <8>; - qcom,mdss-dsi-h-back-porch = <8>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <6>; - qcom,mdss-dsi-v-front-porch = <6>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = - [00 00 00 00 00 00 00 00 00 00 00 00]; - qcom,mdss-dsi-on-command = - [32 01 00 00 00 00 02 00 00]; - qcom,mdss-dsi-off-command = - [22 01 00 00 00 00 02 00 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi deleted file mode 100755 index 6195f8c82a53..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -&mdss_mdp { - dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd { - qcom,mdss-dsi-panel-name = - "sw43404 amoled boe fhd+ panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-pan-physical-width-dimension = <68>; - qcom,mdss-pan-physical-height-dimension = <138>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <160>; - qcom,mdss-dsi-h-back-porch = <72>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 07 01 00 00 00 00 02 01 00 - 0a 01 00 00 00 00 80 11 00 00 89 30 80 - 08 70 04 38 02 1c 02 1c 02 1c 02 00 - 02 0e 00 20 34 29 00 07 00 0C 00 2e - 00 31 18 00 10 F0 03 0C 20 00 06 0B - 0B 33 0E 1C 2A 38 46 54 62 69 70 77 - 79 7B 7D 7E 01 02 01 00 09 40 09 BE - 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 - 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 39 01 00 00 00 00 03 b0 a5 00 - 15 01 00 00 00 00 02 5e 10 - 39 01 00 00 00 00 06 b9 bf 11 40 00 30 - 39 01 00 00 00 00 09 F8 00 08 10 08 2D - 00 00 2D - 15 01 00 00 00 00 02 55 08 - 05 01 00 00 1e 00 02 11 00 - 15 01 00 00 78 00 02 3d 01 - 39 01 00 00 00 00 03 b0 a5 00 - 05 01 00 00 78 00 02 35 00 - 05 01 00 00 3c 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <270>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi deleted file mode 100755 index 032fc39b91bf..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi +++ /dev/null @@ -1,121 +0,0 @@ -&mdss_mdp { - dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd { - qcom,mdss-dsi-panel-name = - "sw43404 amoled cmd mode dsi boe panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - qcom,mdss-dsi-qsync-min-refresh-rate = <55>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2880>; - qcom,mdss-dsi-h-front-porch = <60>; - qcom,mdss-dsi-h-back-porch = <30>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <8>; - qcom,mdss-dsi-v-front-porch = <8>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 03 5c 42 00 - 07 01 00 00 00 00 02 01 00 - 0a 01 00 00 00 00 80 11 00 00 89 30 80 - 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 - 02 68 00 20 9A DB 00 0A 00 0C 00 12 - 00 0E 18 00 10 F0 03 0C 20 00 06 0B - 0B 33 0E 1C 2A 38 46 54 62 69 70 77 - 79 7B 7D 7E 01 02 01 00 09 40 09 BE - 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 - 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 39 01 00 00 00 00 03 b0 a5 00 - 39 01 00 00 00 00 09 F8 00 08 10 08 2D - 00 00 2D - 15 01 00 00 00 00 02 55 08 - 05 01 00 00 1e 00 02 11 00 - 39 01 00 00 00 00 03 b0 a5 00 - 15 01 00 00 00 00 02 e0 18 - 39 01 00 00 00 00 0c c0 00 53 6f 51 50 - 51 34 4f 5a 33 19 - 05 01 00 00 78 00 02 35 00 - 05 01 00 00 3c 00 02 29 00 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-qsync-on-commands = - [15 01 00 00 00 00 02 5a 01]; - qcom,mdss-dsi-qsync-on-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-qsync-off-commands = - [15 01 00 00 00 00 02 5a 00]; - qcom,mdss-dsi-qsync-off-commands-state = - "dsi_lp_mode"; - qcom,mdss-dsi-lp1-command = [ - 05 01 00 00 00 00 02 39 00 - ]; - qcom,mdss-dsi-lp1-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-nolp-command = [ - 05 01 00 00 00 00 02 38 00 - ]; - qcom,mdss-dsi-nolp-command-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <180>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi deleted file mode 100755 index 37c0dfcd7d75..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi +++ /dev/null @@ -1,101 +0,0 @@ -&mdss_mdp { - dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video { - qcom,mdss-dsi-panel-name = - "sw43404 amoled video mode dsi boe panel with DSC"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 - 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <2880>; - qcom,mdss-dsi-h-front-porch = <10>; - qcom,mdss-dsi-h-back-porch = <10>; - qcom,mdss-dsi-h-pulse-width = <12>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <10>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 03 b0 a5 00 - 07 01 00 00 00 00 02 01 00 - 39 01 00 00 00 00 06 b2 00 5d 04 80 49 - 15 01 00 00 00 00 02 3d 10 - 15 01 00 00 00 00 02 36 00 - 15 01 00 00 00 00 02 55 08 - 39 01 00 00 00 00 09 f8 00 08 10 08 2d - 00 00 2d - 39 01 00 00 3c 00 03 51 00 00 - 05 01 00 00 50 00 02 11 00 - 39 01 00 00 00 00 03 b0 34 04 - 39 01 00 00 00 00 05 c1 00 00 00 46 - 39 01 00 00 00 00 03 b0 a5 00 - 0a 01 00 00 00 00 80 11 00 00 89 30 80 - 0B 40 05 A0 02 d0 02 D0 02 D0 02 00 - 02 68 00 20 4e a8 00 0A 00 0C 00 23 - 00 1c 18 00 10 F0 03 0C 20 00 06 0B - 0B 33 0E 1C 2A 38 46 54 62 69 70 77 - 79 7B 7D 7E 01 02 01 00 09 40 09 BE - 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 - 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 39 01 00 00 00 00 03 b0 a5 00 - 15 01 00 00 00 00 02 e0 18 - 39 01 00 00 00 00 0c c0 00 53 6f 51 50 - 51 34 4f 5a 33 19 - 05 01 00 00 78 00 02 29 00 - ]; - qcom,mdss-dsi-off-command = [05 01 00 00 78 00 - 02 28 00 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-lp1-command = [ - 05 01 00 00 00 00 02 39 00 - ]; - qcom,mdss-dsi-lp1-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-nolp-command = [ - 05 01 00 00 00 00 02 38 00 - ]; - qcom,mdss-dsi-nolp-command-state = - "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <180>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi deleted file mode 100755 index 476c34c01d34..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -&mdss_mdp { - dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd { - qcom,mdss-dsi-panel-name = - "td4328 cmd mode dsi truly panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <70>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <5>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-on-command = [ - 29 01 00 00 00 00 02 B0 00 - 29 01 00 00 00 00 04 B3 00 00 06 - 29 01 00 00 00 00 02 B4 00 - 29 01 00 00 00 00 06 B6 33 DB 80 12 00 - 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A - 50 50 - 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 - C8 C8 - 29 01 00 00 00 00 08 BA B5 33 41 64 23 - A0 A0 - 29 01 00 00 00 00 03 BB 14 14 - 29 01 00 00 00 00 03 BC 37 32 - 29 01 00 00 00 00 03 BD 64 32 - 29 01 00 00 00 00 02 BE 04 - 29 01 00 00 00 00 02 C0 00 - 29 01 00 00 00 00 2E C1 04 48 00 00 26 - 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C - 6B 93 4D 22 18 8B 2A 41 00 00 00 00 - 00 00 00 00 00 40 02 22 1B 06 03 00 - 07 FF 00 01 - 29 01 00 00 00 00 18 C2 01 F8 70 08 68 - 08 0C 10 00 08 30 00 00 00 00 00 00 - 20 02 43 00 00 00 - 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 - 00 00 00 00 00 00 04 3A 00 00 00 04 - 44 00 00 01 01 03 28 00 01 00 01 00 - 00 19 00 0C 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 32 00 19 00 5A - 02 32 00 19 00 5A 02 40 00 - 29 01 00 00 00 00 15 C4 70 00 00 00 11 - 11 00 00 00 02 02 31 01 00 00 00 02 - 01 01 01 - 29 01 00 00 00 00 08 C5 08 00 00 00 00 - 70 00 - 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 - 07 54 01 02 01 02 07 07 00 00 07 07 - 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 - 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F - 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 - A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 - 45 4F 5C 71 7B 88 98 A6 BE - 29 01 00 00 00 00 38 C8 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 - 29 01 00 00 00 00 14 C9 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 - 29 01 00 00 00 00 2C CA 1C FC FC FC 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 1C CB FF FF FF FF 0F - 00 08 00 01 00 31 F0 40 08 00 00 00 - 00 00 00 00 00 00 00 00 00 00 - 29 01 00 00 00 00 02 CC 02 - 29 01 00 00 00 00 27 CD 10 80 37 C0 1A - 00 5C 02 19 90 11 88 D8 6C D8 6C 01 - 00 00 00 32 00 32 00 5D 02 32 32 01 - 33 00 33 00 5E 02 32 32 AF - 29 01 00 00 00 00 1A CE 5D 40 49 53 59 - 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF - 04 00 04 04 42 00 69 5A - 29 01 00 00 00 00 03 CF 4A 1D - 29 01 00 00 00 00 12 D0 33 57 D4 31 01 - 10 10 10 19 19 00 00 00 00 00 00 00 - 29 01 00 00 00 00 02 D1 00 - 29 01 00 00 00 00 20 D2 10 00 00 10 75 - 0F 03 25 20 00 00 00 00 00 00 00 00 - 04 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 - 77 BB B3 33 00 00 6D 6E C7 C7 33 BB - F2 FD C6 0B 07 - 29 01 00 00 00 00 08 D4 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 08 D5 03 00 00 02 2B - 02 2B - 29 01 00 00 00 00 02 D6 01 - 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 - 24 80 1F C7 1F 1B 00 0C 07 20 00 00 - 00 00 00 0C 00 1F 00 FC 00 00 AA 67 - 7E 5D 06 00 - 29 01 00 00 00 00 03 D9 20 14 - 29 01 00 00 00 00 05 DD 30 06 23 65 - 29 01 00 00 00 00 05 DE 00 3F FF 50 - 29 01 00 00 00 00 06 E7 00 00 00 46 61 - 29 01 00 00 00 00 02 EA 1F - 29 01 00 00 00 00 04 EE 41 51 00 - 29 01 00 00 00 00 03 F1 00 00 - 39 01 00 00 00 00 05 2A 00 00 04 37 - 39 01 00 00 00 00 05 2B 00 00 08 6F - 39 01 00 00 00 00 01 2C - 29 01 00 00 00 00 02 B0 00 - 39 01 00 00 00 00 02 51 FF - 39 01 00 00 00 00 02 53 0C - 39 01 00 00 00 00 02 55 00 - 15 01 00 00 00 00 02 35 00 - 05 01 00 00 96 00 01 11 - 05 01 00 00 32 00 01 29]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 32 00 02 28 00 - 05 01 00 00 96 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi deleted file mode 100755 index e9b7bac34504..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -&mdss_mdp { - dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video { - qcom,mdss-dsi-panel-name = - "td4328 video mode dsi truly panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-color-order = "rgb_swap_rgb"; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; - qcom,mdss-dsi-lane-map = "lane_map_0123"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-tx-eot-append; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2160>; - qcom,mdss-dsi-h-front-porch = <70>; - qcom,mdss-dsi-h-back-porch = <40>; - qcom,mdss-dsi-h-pulse-width = <16>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <10>; - qcom,mdss-dsi-v-front-porch = <5>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 29 01 00 00 00 00 02 B0 00 - 29 01 00 00 00 00 04 B3 31 00 06 - 29 01 00 00 00 00 02 B4 00 - 29 01 00 00 00 00 06 B6 33 DB 80 12 00 - 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A - 50 50 - 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 - C8 C8 - 29 01 00 00 00 00 08 BA B5 33 41 64 23 - A0 A0 - 29 01 00 00 00 00 03 BB 14 14 - 29 01 00 00 00 00 03 BC 37 32 - 29 01 00 00 00 00 03 BD 64 32 - 29 01 00 00 00 00 02 BE 04 - 29 01 00 00 00 00 02 C0 00 - 29 01 00 00 00 00 2E C1 04 48 00 00 26 - 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C - 6B 93 4D 22 18 8B 2A 41 00 00 00 00 - 00 00 00 00 00 40 02 22 1B 06 03 00 - 07 FF 00 01 - 29 01 00 00 00 00 18 C2 01 F8 70 08 68 - 08 0C 10 00 08 30 00 00 00 00 00 00 - 20 02 43 00 00 00 - 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 - 00 00 00 00 00 00 04 3A 00 00 00 04 - 44 00 00 01 01 03 28 00 01 00 01 00 - 00 19 00 0C 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 32 00 19 00 5A - 02 32 00 19 00 5A 02 40 00 - 29 01 00 00 00 00 15 C4 70 00 00 00 11 - 11 00 00 00 02 02 31 01 00 00 00 02 - 01 01 01 - 29 01 00 00 00 00 08 C5 08 00 00 00 00 - 70 00 - 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 - 07 54 01 02 01 02 07 07 00 00 07 07 - 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 - 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F - 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 - A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 - 45 4F 5C 71 7B 88 98 A6 BE - 29 01 00 00 00 00 38 C8 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 - 29 01 00 00 00 00 14 C9 00 00 00 00 00 - FC 00 00 00 00 00 FC 00 00 00 00 00 - FC 00 - 29 01 00 00 00 00 2C CA 1C FC FC FC 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 1C CB FF FF FF FF 0F - 00 08 00 01 00 31 F0 40 08 00 00 00 - 00 00 00 00 00 00 00 00 00 00 - 29 01 00 00 00 00 02 CC 02 - 29 01 00 00 00 00 27 CD 10 80 37 C0 1A - 00 5C 02 19 90 11 88 D8 6C D8 6C 01 - 00 00 00 32 00 32 00 5D 02 32 32 01 - 33 00 33 00 5E 02 32 32 AF - 29 01 00 00 00 00 1A CE 5D 40 49 53 59 - 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF - 04 00 04 04 42 00 69 5A - 29 01 00 00 00 00 03 CF 4A 1D - 29 01 00 00 00 00 12 D0 33 57 D4 31 01 - 10 10 10 19 19 00 00 00 00 00 00 00 - 29 01 00 00 00 00 02 D1 00 - 29 01 00 00 00 00 20 D2 10 00 00 10 75 - 0F 03 25 20 00 00 00 00 00 00 00 00 - 04 00 00 00 00 00 00 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 - 77 BB B3 33 00 00 6D 6E DB DB 33 BB - F2 FD C6 0B 07 - 29 01 00 00 00 00 08 D4 00 00 00 00 00 - 00 00 - 29 01 00 00 00 00 08 D5 03 00 00 02 40 - 02 40 - 29 01 00 00 00 00 02 D6 01 - 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 - 24 80 1F C7 1F 1B 00 0C 07 20 00 00 - 00 00 00 0C 00 1F 00 FC 00 00 AA 67 - 7E 5D 06 00 - 29 01 00 00 00 00 03 D9 20 14 - 29 01 00 00 00 00 05 DD 30 06 23 65 - 29 01 00 00 00 00 05 DE 00 3F FF 90 - 29 01 00 00 00 00 06 E7 00 00 00 46 61 - 29 01 00 00 00 00 02 EA 1F - 29 01 00 00 00 00 04 EE 41 51 00 - 29 01 00 00 00 00 03 F1 00 00 - 39 01 00 00 00 00 05 2A 00 00 04 37 - 39 01 00 00 00 00 05 2B 00 00 08 6F - 39 01 00 00 00 00 01 2C - 39 01 00 00 00 00 02 51 FF - 39 01 00 00 00 00 02 53 0C - 39 01 00 00 00 00 02 55 00 - 05 01 00 00 96 00 01 11 - 05 01 00 00 32 00 01 29]; - qcom,mdss-dsi-off-command = [ - 05 01 00 00 32 00 02 28 00 - 05 01 00 00 96 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi deleted file mode 100755 index a7d85dfd9194..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -&dsi_sharp_4k_dsc_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - /delete-property/ qcom,platform-en-gpio; -}; - -&dsi_sharp_1080_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; -}; - -&sde_dsi { - /delete-property/ avdd-supply; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi deleted file mode 100755 index fadbce641428..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -#include "kona-sde-display.dtsi" - -&dsi_sw43404_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_4k_dsc_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-en-gpio = <&tlmm 60 0>; -}; - -&dsi_sharp_1080_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_nt35597_truly_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_sec_hd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; -}; - -&sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi deleted file mode 100755 index b81aad8801d0..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -#include "kona-sde-display.dtsi" - -&dsi_sw43404_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_sec_hd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 75 0>; - qcom,platform-sec-reset-gpio = <&tlmm 128 0>; -}; - -&sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi deleted file mode 100755 index 1f6e32ac60f8..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi +++ /dev/null @@ -1,76 +0,0 @@ -#include "kona-sde-display.dtsi" - -&dsi_sw43404_amoled_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,mdss-brightness-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_vid { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,platform-reset-gpio = <&tlmm 75 0>; -}; - -&sde_dsi { - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi deleted file mode 100755 index 3eb83e40a9c0..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "kona-sde-display.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi deleted file mode 100755 index 6257b55c4e1d..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi +++ /dev/null @@ -1,528 +0,0 @@ -#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" -#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" -#include "dsi-panel-sharp-dsc-4k-video.dtsi" -#include "dsi-panel-sharp-1080p-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" -#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" -#include "dsi-panel-sim-cmd.dtsi" -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-sim-dsc375-cmd.dtsi" -#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-cmd.dtsi" -#include "dsi-panel-sim-dualmipi-video.dtsi" -#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" -#include "dsi-panel-sim-sec-hd-cmd.dtsi" -#include - -&tlmm { - display_panel_avdd_default: display_panel_avdd_default { - mux { - pins = "gpio61"; - function = "gpio"; - }; - - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable = <0>; - output-high; - }; - }; -}; - -&soc { - ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; - }; - - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <3300000>; - qcom,supply-max-voltage = <3300000>; - qcom,supply-enable-load = <857000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; - }; - }; - - dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <62000>; - qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "avdd"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - }; - - display_panel_avdd: display_gpio_regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "display_panel_avdd"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 61 0>; - enable-active-high; - regulator-boot-on; - pinctrl-names = "default"; - pinctrl-0 = <&display_panel_avdd_default>; - }; - - sde_dsi: qcom,dsi-display-primary { - compatible = "qcom,dsi-display"; - label = "primary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 66 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; - avdd-supply = <&display_panel_avdd>; - - qcom,mdp = <&mdss_mdp>; - qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>; - }; - - sde_dsi1: qcom,dsi-display-secondary { - compatible = "qcom,dsi-display"; - label = "secondary"; - - qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; - qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, - <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; - - qcom,platform-te-gpio = <&tlmm 67 0>; - qcom,panel-te-source = <1>; - - vddio-supply = <&pm8150_l14>; - vdd-supply = <&pm8150a_l11>; - avdd-supply = <&display_panel_avdd>; - - qcom,mdp = <&mdss_mdp>; - }; - - sde_wb: qcom,wb-display@0 { - compatible = "qcom,wb-display"; - cell-index = <0>; - label = "wb_display"; - }; -}; - -&sde_dp { - qcom,dp-usbpd-detection = <&pm8150b_pdphy>; - qcom,ext-disp = <&ext_disp>; - qcom,dp-aux-switch = <&fsa4480>; - - qcom,usbplug-cc-gpio = <&tlmm 65 0>; - - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&sde_dp_usbplug_cc_active>; - pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; -}; - -&mdss_mdp { - connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>; -}; - -/* PHY TIMINGS REVISION W */ -&dsi_sw43404_amoled_cmd { - qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 180 180 180 1440 180>; - }; - }; -}; - -&dsi_sw43404_amoled_video { - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,dsi-supported-dfps-list = <60 57 55>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; - qcom,mdss-dsi-min-refresh-rate = <55>; - qcom,mdss-dsi-max-refresh-rate = <60>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05 - 05 03 02 04 00 12 15]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sw43404_amoled_fhd_plus_cmd { - qcom,ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 - 05 02 03 04 00 11 14]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 270 270 270 1080 270>; - }; - }; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_1080_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,mdss-dsi-panel-clockrate = <900000000>; - }; - }; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_nt35695b_truly_fhd_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_nt35695b_truly_fhd_video { - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@3 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <540 40 540 40 540 40>; - qcom,partial-update-enabled = "single_roi"; - }; - - timing@4 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <1>; - qcom,panel-roi-alignment = <360 40 360 40 360 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; - -&dsi_sim_vid { - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 0 1>, - <2 0 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_dsc_375_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { /* 1080p */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_dsc_10b_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { /* QHD 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 1080 60fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <1 1 1>, - <2 2 1>, /* dsc merge */ - <2 1 1>; /* 3d mux */ - qcom,default-topology-index = <0>; - }; - - timing@2 { /* QHD 90fps */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 - 09 06 02 04 00 18 17]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_vid { - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 0 2>, - <1 0 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_dual_sim_dsc_375_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { /* qhd */ - qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 - 07 05 02 04 00 18 17]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@1 { /* 4k */ - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 - 08 05 02 04 00 19 18]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - - timing@2 { /* 5k */ - qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12 - 14 0e 02 04 00 37 22]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sim_sec_hd_cmd { - qcom,ulps-enabled; - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 - 08 08 05 02 04 00 19 17]; - qcom,display-topology = <1 0 1>; - qcom,default-topology-index = <0>; - qcom,panel-roi-alignment = <720 40 720 40 720 40>; - qcom,partial-update-enabled = "single_roi"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi deleted file mode 100755 index e6bda66f50ac..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -&soc { - mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { - compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; - label = "MDSS DSI 0 PLL"; - cell-index = <0>; - #clock-cells = <1>; - reg = <0xae94900 0x260>, - <0xae94400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - gdsc-supply = <&mdss_core_gdsc>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { - compatible = "qcom,mdss_dsi_pll_7nm_v4_1"; - label = "MDSS DSI 1 PLL"; - cell-index = <1>; - #clock-cells = <1>; - reg = <0xae96900 0x260>, - <0xae96400 0x800>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "gdsc_base"; - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - gdsc-supply = <&mdss_core_gdsc>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dp_pll: qcom,mdss_dp_pll@c011000 { - compatible = "qcom,mdss_dp_pll_7nm"; - label = "MDSS DP PLL"; - cell-index = <0>; - #clock-cells = <1>; - - reg = <0x088ea000 0x200>, - <0x088eaa00 0x200>, - <0x088ea200 0x200>, - <0x088ea600 0x200>, - <0xaf03000 0x8>; - reg-names = "pll_base", "phy_base", "ln_tx0_base", - "ln_tx1_base", "gdsc_base"; - - clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "iface_clk", "ref_clk_src", - "gcc_iface", "pipe_clk"; - clock-rate = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi deleted file mode 100755 index d6a849eb4925..000000000000 --- a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi +++ /dev/null @@ -1,688 +0,0 @@ -#include - -&soc { - mdss_mdp: qcom,mdss_mdp@ae00000 { - compatible = "qcom,sde-kms"; - reg = <0x0ae00000 0x84208>, - <0x0aeb0000 0x2008>, - <0x0aeac000 0x214>, - <0x0ae8f000 0x02c>, - <0x0af50000 0x038>; - reg-names = "mdp_phys", - "vbif_phys", - "regdma_phys", - "sid_phys", - "swfuse_phys"; - - clocks = - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_DISP_HF_AXI_CLK>, - <&clock_gcc GCC_DISP_SF_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, - <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", - "iface_clk", "core_clk", "vsync_clk", - "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; - clock-max-rate = <0 0 0 0 460000000 19200000 460000000 - 460000000>; - - mmcx-supply = <&VDD_MMCX_LEVEL>; - - /* interrupt config */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - #power-domain-cells = <0>; - - /* hw blocks */ - qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; - - qcom,sde-ctl-off = <0x2000 0x2200 0x2400 - 0x2600 0x2800 0x2a00>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; - - qcom,sde-mixer-off = <0x45000 0x46000 0x47000 - 0x48000 0x49000 0x4a000>; - qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "primary", "none", - "none", "none", "none"; - - qcom,sde-mixer-cwb-pref = "none", "none", "cwb", - "cwb", "cwb", "cwb"; - - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-top-size = <0x80>; - qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; - qcom,sde-dspp-size = <0x1800>; - - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-top-size = <0x1c>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-dest-scaler-size = <0x800>; - - qcom,sde-wb-off = <0x66000>; - qcom,sde-wb-size = <0x2c8>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - - qcom,sde-intf-off = <0x6b000 0x6b800 - 0x6c000 0x6c800>; - qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; - - qcom,sde-pp-off = <0x71000 0x71800 - 0x72000 0x72800 0x73000 0x73800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; - qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; - - qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; - qcom,sde-merge-3d-size = <0x100>; - - qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; - - qcom,sde-cdm-off = <0x7a200>; - qcom,sde-cdm-size = <0x224>; - - qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; - qcom,sde-dsc-size = <0x140>; - - qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 - 0x30e0 0x30e0 0x30e0>; - qcom,sde-dither-version = <0x00010000>; - qcom,sde-dither-size = <0x20>; - - qcom,sde-sspp-type = "vig", "vig", "vig", "vig", - "dma", "dma", "dma", "dma"; - - qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 - 0x25000 0x27000 0x29000 0x2b000>; - qcom,sde-sspp-src-size = <0x1f8>; - - qcom,sde-sspp-xin-id = <0 4 8 12 - 1 5 9 13>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; - qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - - qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; - - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000 - 4400000 4400000 - 4400000 4400000 - 4400000 4400000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000 - 5300000 5300000 - 5300000 5300000 - 5300000 5300000>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = - <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, - <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; - qcom,sde-sspp-csc-off = <0x1a00>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-qseed-type = "qseedv3lite"; - qcom,sde-sspp-qseed-off = <0xa00>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <4096>; - qcom,sde-wb-linewidth = <4096>; - qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x3>; - qcom,sde-ubwc-version = <0x400>; - qcom,sde-ubwc-swizzle = <0x6>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x1>; - qcom,sde-macrotile-mode = <0x1>; - qcom,sde-smart-panel-align-mode = <0xc>; - qcom,sde-panic-per-pipe; - qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; - qcom,sde-has-idle-pc; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-max-bw-low-kbps = <13700000>; - qcom,sde-max-bw-high-kbps = <16600000>; - qcom,sde-min-core-ib-kbps = <2400000>; - qcom,sde-min-llcc-ib-kbps = <800000>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <0>; - qcom,sde-dspp-ltm-version = <0x00010000>; - /* offsets are based off dspp 0 and dspp 1 */ - qcom,sde-dspp-ltm-off = <0x2a000 0x28100>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-vbif-off = <0>; - qcom,sde-vbif-size = <0x1040>; - qcom,sde-vbif-id = <0>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; - - /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x000000ff 0x0000ffff - 0x00000000 0x00000000 0x0000ffff>; - - qcom,sde-safe-lut-linear = <0 0xfff0>; - qcom,sde-safe-lut-macrotile = <0 0xff00>; - /* same as safe-lut-macrotile */ - qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; - qcom,sde-safe-lut-nrt = <0 0xffff>; - qcom,sde-safe-lut-cwb = <0 0x3ff>; - - qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; - qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; - qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; - qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; - qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-dma-latency = <300>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - - qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - qcom,sde-secure-sid-mask = <0x4000821>; - - qcom,sde-sspp-vig-blocks { - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - qcom,sde-vig-inverse-pma; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00030001>; - qcom,sde-dspp-hsic = <0x800 0x00010007>; - qcom,sde-dspp-memcolor = <0x880 0x00010007>; - qcom,sde-dspp-hist = <0x800 0x00010007>; - qcom,sde-dspp-sixzone= <0x900 0x00010007>; - qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040001>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; - qcom,sde-dspp-dither = <0x82c 0x00010007>; - }; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "mmcx"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - smmu_sde_unsec: qcom,smmu_sde_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&apps_smmu 0x820 0x402>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-earlymap; /* for cont-splash */ - }; - - smmu_sde_sec: qcom,smmu_sde_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&apps_smmu 0x821 0x400>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; - qcom,iommu-faults = "non-fatal"; - qcom,iommu-vmid = <0xa>; - }; - - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "mdss_sde"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - }; - - qcom,sde-reg-bus { - qcom,msm-bus,name = "mdss_reg"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>, - <1 590 0 150000>, - <1 590 0 300000>; - }; - }; - - sde_dp: qcom,dp_display@ae90000 { - cell-index = <0>; - compatible = "qcom,dp-display"; - - vdda-1p2-supply = <&pm8150_l9>; - vdda-0p9-supply = <&pm8150_l18>; - - reg = <0xae90000 0x0dc>, - <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02000 0x1a0>, - <0x780000 0x621c>, - <0x88ea040 0x10>, - <0x88e8000 0x20>, - <0x0aee1000 0x034>, - <0xae91400 0x094>; - /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ - reg-names = "dp_ahb", "dp_aux", "dp_link", - "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", - "usb3_dp_com", "hdcp_physical", "dp_p1"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_pipe_clk", "link_clk", "link_iface_clk", - "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "pixel1_parent", - "strm0_pixel_clk", "strm1_pixel_clk"; - - qcom,phy-version = <0x420>; - qcom,aux-cfg0-settings = [20 00]; - qcom,aux-cfg1-settings = [24 13]; - qcom,aux-cfg2-settings = [28 A4]; - qcom,aux-cfg3-settings = [2c 00]; - qcom,aux-cfg4-settings = [30 0a]; - qcom,aux-cfg5-settings = [34 26]; - qcom,aux-cfg6-settings = [38 0a]; - qcom,aux-cfg7-settings = [3c 03]; - qcom,aux-cfg8-settings = [40 b7]; - qcom,aux-cfg9-settings = [44 03]; - - qcom,max-pclk-frequency-khz = <675000>; - - qcom,mst-enable; - qcom,widebus-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,max-dp-dsc-blks = <2>; - qcom,max-dp-dsc-input-width-pixs = <2048>; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <33000>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <912000>; - qcom,supply-max-voltage = <912000>; - qcom,supply-enable-load = <126000>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - sde_rscc: qcom,sde_rscc@af20000 { - cell-index = <0>; - compatible = "qcom,sde-rsc"; - reg = <0xaf20000 0x3c50>, - <0xaf30000 0x3fd4>; - reg-names = "drv", "wrapper"; - qcom,sde-rsc-version = <3>; - - qcom,sde-dram-channels = <2>; - - vdd-supply = <&mdss_core_gdsc>; - clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, - <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; - clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; - - /* data and reg bus scale settings */ - qcom,sde-data-bus { - qcom,msm-bus,name = "disp_rsc_mnoc_llcc"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <20003 20513 0 0>, <20004 20513 0 0>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>, - <20003 20513 0 6400000>, <20004 20513 0 6400000>; - }; - - qcom,sde-ebi-bus { - qcom,msm-bus,name = "disp_rsc_ebi"; - qcom,msm-bus,active-only; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <20000 20512 0 0>, - <20000 20512 0 6400000>, - <20000 20512 0 6400000>; - }; - }; - - mdss_rotator: qcom,mdss_rotator@aea8800 { - compatible = "qcom,sde_rotator"; - reg = <0x0ae00000 0xac000>, - <0x0aeb8000 0x3000>; - reg-names = "mdp_phys", - "rot_vbif_phys"; - status = "disabled"; - - #list-cells = <1>; - - qcom,mdss-rot-mode = <1>; - qcom,mdss-highest-bank-bit = <0x3>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_rotator"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <25 512 0 0>, - <25 512 0 6400000>, - <25 512 0 6400000>; - - rot-vdd-supply = <&mdss_core_gdsc>; - qcom,supply-names = "rot-vdd"; - - clocks = - <&clock_gcc GCC_DISP_AHB_CLK>, - <&clock_gcc GCC_DISP_SF_AXI_CLK>, - <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, - <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", - "iface_clk", "rot_clk"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <2 0>; - - power-domains = <&mdss_mdp>; - - /* Offline rotator QoS setting */ - qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; - qcom,mdss-rot-vbif-memtype = <3 3>; - qcom,mdss-rot-cdp-setting = <1 1>; - qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; - qcom,mdss-rot-danger-lut = <0x0 0x0>; - qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; - - qcom,mdss-default-ot-rd-limit = <32>; - qcom,mdss-default-ot-wr-limit = <32>; - - qcom,mdss-sbuf-headroom = <20>; - - /* reg bus scale settings */ - rot_reg: qcom,rot-reg-bus { - qcom,msm-bus,name = "mdss_rot_reg"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 590 0 0>, - <1 590 0 76800>; - }; - - smmu_rot_unsec: qcom,smmu_rot_unsec_cb { - compatible = "qcom,smmu_sde_rot_unsec"; - iommus = <&apps_smmu 0x215C 0x0400>; - qcom,iommu-dma = "disabled"; - }; - }; - - mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-0"; - cell-index = <0>; - reg = <0xae94000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <4 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <26700>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; - label = "dsi-ctrl-1"; - cell-index = <1>; - reg = <0xae96000 0x400>, - <0xaf08000 0x4>; - reg-names = "dsi_ctrl", "disp_cc_base"; - interrupt-parent = <&mdss_mdp>; - interrupts = <5 0>; - vdda-1p2-supply = <&pm8150_l9>; - refgen-supply = <&refgen>; - clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; - clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk"; - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <26700>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { - compatible = "qcom,dsi-phy-v4.1"; - label = "dsi-phy-0"; - cell-index = <0>; - reg = <0xae94400 0x760>; - reg-names = "dsi_phy"; - vdda-0p9-supply = <&pm8150_l5>; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <46000>; - qcom,supply-disable-load = <0>; - }; - }; - }; - - mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 { - compatible = "qcom,dsi-phy-v4.1"; - label = "dsi-phy-1"; - cell-index = <1>; - reg = <0xae96400 0x760>; - reg-names = "dsi_phy"; - vdda-0p9-supply = <&pm8150_l5>; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 0a 0a - 00 00 8a 8a]; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <46000>; - qcom,supply-disable-load = <0>; - }; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi new file mode 100755 index 000000000000..02f1cee08a1a --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi @@ -0,0 +1,480 @@ +&mdss_mdp { + dsi_nt36672e_fhd_plus_90hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_90hz_video { + qcom,mdss-dsi-panel-name = + "nt36672e 90Hz fhd plus video mode panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750 + 39800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2408>; + qcom,mdss-dsi-h-front-porch = <76>; + qcom,mdss-dsi-h-back-porch = <68>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <46>; + qcom,mdss-dsi-v-pulse-width = <10>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 C0 03 + 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7 + 39 01 00 00 00 00 03 C2 1B A0 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 66 + 39 01 00 00 00 00 02 06 40 + 39 01 00 00 00 00 02 07 38 + 39 01 00 00 00 00 02 18 66 + 39 01 00 00 00 00 02 1B 01 + 39 01 00 00 00 00 02 5C 90 + 39 01 00 00 00 00 02 5E AA + 39 01 00 00 00 00 02 69 91 + + 39 01 00 00 00 00 02 89 0D + 39 01 00 00 00 00 02 8A 0D + 39 01 00 00 00 00 02 8D 0D + 39 01 00 00 00 00 02 8E 0D + 39 01 00 00 00 00 02 8F 0D + 39 01 00 00 00 00 02 91 0D + + 39 01 00 00 00 00 02 95 D1 + 39 01 00 00 00 00 02 96 D1 + 39 01 00 00 00 00 02 F2 65 + 39 01 00 00 00 00 02 F3 64 + 39 01 00 00 00 00 02 F4 65 + 39 01 00 00 00 00 02 F5 64 + 39 01 00 00 00 00 02 F6 65 + 39 01 00 00 00 00 02 F7 64 + 39 01 00 00 00 00 02 F8 65 + 39 01 00 00 00 00 02 F9 64 + + 39 01 00 00 00 00 02 FF 24 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 0F + 39 01 00 00 00 00 02 03 0C + 39 01 00 00 00 00 02 05 1D + 39 01 00 00 00 00 02 08 2F + 39 01 00 00 00 00 02 09 2E + 39 01 00 00 00 00 02 0A 2D + 39 01 00 00 00 00 02 0B 2C + 39 01 00 00 00 00 02 11 17 + 39 01 00 00 00 00 02 12 13 + 39 01 00 00 00 00 02 13 15 + 39 01 00 00 00 00 02 15 14 + 39 01 00 00 00 00 02 16 16 + 39 01 00 00 00 00 02 17 18 + 39 01 00 00 00 00 02 1B 01 + 39 01 00 00 00 00 02 1D 1D + 39 01 00 00 00 00 02 20 2F + 39 01 00 00 00 00 02 21 2E + 39 01 00 00 00 00 02 22 2D + 39 01 00 00 00 00 02 23 2C + 39 01 00 00 00 00 02 29 17 + 39 01 00 00 00 00 02 2A 13 + 39 01 00 00 00 00 02 2B 15 + 39 01 00 00 00 00 02 2F 14 + 39 01 00 00 00 00 02 30 16 + 39 01 00 00 00 00 02 31 18 + 39 01 00 00 00 00 02 32 04 + 39 01 00 00 00 00 02 34 10 + 39 01 00 00 00 00 02 35 1F + 39 01 00 00 00 00 02 36 1F + 39 01 00 00 00 00 02 4D 19 + 39 01 00 00 00 00 02 4E 45 + 39 01 00 00 00 00 02 4F 45 + 39 01 00 00 00 00 02 53 45 + 39 01 00 00 00 00 02 71 30 + 39 01 00 00 00 00 02 79 11 + 39 01 00 00 00 00 02 7A 82 + 39 01 00 00 00 00 02 7B 94 + 39 01 00 00 00 00 02 7D 04 + 39 01 00 00 00 00 02 80 04 + 39 01 00 00 00 00 02 81 04 + 39 01 00 00 00 00 02 82 13 + 39 01 00 00 00 00 02 84 31 + 39 01 00 00 00 00 02 85 00 + 39 01 00 00 00 00 02 86 00 + 39 01 00 00 00 00 02 87 00 + 39 01 00 00 00 00 02 90 13 + 39 01 00 00 00 00 02 92 31 + 39 01 00 00 00 00 02 93 00 + 39 01 00 00 00 00 02 94 00 + 39 01 00 00 00 00 02 95 00 + 39 01 00 00 00 00 02 9C F4 + 39 01 00 00 00 00 02 9D 01 + 39 01 00 00 00 00 02 A0 14 + 39 01 00 00 00 00 02 A2 14 + 39 01 00 00 00 00 02 A3 02 + 39 01 00 00 00 00 02 A4 04 + 39 01 00 00 00 00 02 A5 04 + 39 01 00 00 00 00 02 C4 40 + 39 01 00 00 00 00 02 C6 C0 + 39 01 00 00 00 00 02 C9 00 + 39 01 00 00 00 00 02 D9 80 + 39 01 00 00 00 00 02 E9 02 + + 39 01 00 00 00 00 02 FF 25 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 0F 1B + 39 01 00 00 00 00 02 19 E4 + 39 01 00 00 00 00 02 21 40 + 39 01 00 00 00 00 02 66 D8 + 39 01 00 00 00 00 02 68 50 + 39 01 00 00 00 00 02 69 10 + 39 01 00 00 00 00 02 6B 00 + 39 01 00 00 00 00 02 6D 0D + 39 01 00 00 00 00 02 6E 48 + 39 01 00 00 00 00 02 72 41 + 39 01 00 00 00 00 02 73 4A + 39 01 00 00 00 00 02 74 D0 + 39 01 00 00 00 00 02 77 62 + 39 01 00 00 00 00 02 79 7F + 39 01 00 00 00 00 02 7D 40 + 39 01 00 00 00 00 02 7F 00 + 39 01 00 00 00 00 02 80 04 + 39 01 00 00 00 00 02 84 0D + 39 01 00 00 00 00 02 CF 80 + 39 01 00 00 00 00 02 D6 80 + 39 01 00 00 00 00 02 D7 80 + 39 01 00 00 00 00 02 EF 20 + 39 01 00 00 00 00 02 F0 84 + + 39 01 00 00 00 00 02 FF 26 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 15 04 + 39 01 00 00 00 00 02 81 14 + 39 01 00 00 00 00 02 83 02 + 39 01 00 00 00 00 02 84 03 + 39 01 00 00 00 00 02 85 01 + 39 01 00 00 00 00 02 86 03 + 39 01 00 00 00 00 02 87 01 + 39 01 00 00 00 00 02 88 06 + 39 01 00 00 00 00 02 8A 1A + 39 01 00 00 00 00 02 8B 11 + 39 01 00 00 00 00 02 8C 24 + 39 01 00 00 00 00 02 8E 42 + 39 01 00 00 00 00 02 8F 11 + 39 01 00 00 00 00 02 90 11 + 39 01 00 00 00 00 02 91 11 + 39 01 00 00 00 00 02 9A 81 + 39 01 00 00 00 00 02 9B 03 + 39 01 00 00 00 00 02 9C 00 + 39 01 00 00 00 00 02 9D 00 + 39 01 00 00 00 00 02 9E 00 + + 39 01 00 00 00 00 02 FF 27 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 01 68 + 39 01 00 00 00 00 02 20 81 + 39 01 00 00 00 00 02 21 EA + 39 01 00 00 00 00 02 25 82 + 39 01 00 00 00 00 02 26 1F + 39 01 00 00 00 00 02 6E 00 + 39 01 00 00 00 00 02 6F 00 + 39 01 00 00 00 00 02 70 00 + 39 01 00 00 00 00 02 71 00 + 39 01 00 00 00 00 02 72 00 + 39 01 00 00 00 00 02 75 00 + 39 01 00 00 00 00 02 76 00 + 39 01 00 00 00 00 02 77 00 + 39 01 00 00 00 00 02 7D 09 + 39 01 00 00 00 00 02 7E 67 + 39 01 00 00 00 00 02 80 23 + 39 01 00 00 00 00 02 82 09 + 39 01 00 00 00 00 02 83 67 + 39 01 00 00 00 00 02 88 01 + 39 01 00 00 00 00 02 89 10 + 39 01 00 00 00 00 02 A5 10 + 39 01 00 00 00 00 02 A6 23 + 39 01 00 00 00 00 02 A7 01 + 39 01 00 00 00 00 02 B6 40 + 39 01 00 00 00 00 02 E3 02 + 39 01 00 00 00 00 02 E4 E0 + 39 01 00 00 00 00 02 E5 01 + 39 01 00 00 00 00 02 E6 70 + 39 01 00 00 00 00 02 E9 03 + 39 01 00 00 00 00 02 EA 2F + 39 01 00 00 00 00 02 EB 01 + 39 01 00 00 00 00 02 EC 98 + + 39 01 00 00 00 00 02 FF 2A + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 00 91 + 39 01 00 00 00 00 02 03 20 + 39 01 00 00 00 00 02 07 5A + 39 01 00 00 00 00 02 0A 70 + 39 01 00 00 00 00 02 0D 40 + 39 01 00 00 00 00 02 0E 02 + 39 01 00 00 00 00 02 11 F0 + 39 01 00 00 00 00 02 15 0F + 39 01 00 00 00 00 02 16 65 + 39 01 00 00 00 00 02 19 0F + 39 01 00 00 00 00 02 1A 39 + 39 01 00 00 00 00 02 1B 14 + 39 01 00 00 00 00 02 1D 36 + 39 01 00 00 00 00 02 1E 4F + 39 01 00 00 00 00 02 1F 4F + 39 01 00 00 00 00 02 20 4F + 39 01 00 00 00 00 02 28 E4 + 39 01 00 00 00 00 02 29 17 + 39 01 00 00 00 00 02 2A F5 + 39 01 00 00 00 00 02 2D 06 + 39 01 00 00 00 00 02 2F 04 + 39 01 00 00 00 00 02 30 54 + 39 01 00 00 00 00 02 33 04 + 39 01 00 00 00 00 02 34 E6 + 39 01 00 00 00 00 02 35 32 + 39 01 00 00 00 00 02 36 02 + 39 01 00 00 00 00 02 37 E1 + 39 01 00 00 00 00 02 38 36 + 39 01 00 00 00 00 02 39 FE + 39 01 00 00 00 00 02 3A 14 + 39 01 00 00 00 00 02 46 40 + 39 01 00 00 00 00 02 47 02 + 39 01 00 00 00 00 02 4A F0 + 39 01 00 00 00 00 02 4E 0F + 39 01 00 00 00 00 02 4F 65 + 39 01 00 00 00 00 02 52 0F + 39 01 00 00 00 00 02 53 39 + 39 01 00 00 00 00 02 54 14 + 39 01 00 00 00 00 02 56 36 + 39 01 00 00 00 00 02 57 7E + 39 01 00 00 00 00 02 58 7E + 39 01 00 00 00 00 02 59 7E + 39 01 00 00 00 00 02 60 80 + 39 01 00 00 00 00 02 61 C9 + 39 01 00 00 00 00 02 62 03 + 39 01 00 00 00 00 02 63 FB + 39 01 00 00 00 00 02 64 03 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 66 01 + 39 01 00 00 00 00 02 67 04 + 39 01 00 00 00 00 02 68 91 + 39 01 00 00 00 00 02 6A 19 + 39 01 00 00 00 00 02 6B CB + 39 01 00 00 00 00 02 6C 20 + 39 01 00 00 00 00 02 6D E5 + 39 01 00 00 00 00 02 6E C8 + 39 01 00 00 00 00 02 6F 22 + 39 01 00 00 00 00 02 70 E3 + 39 01 00 00 00 00 02 71 04 + 39 01 00 00 00 00 02 7A 07 + 39 01 00 00 00 00 02 7B 40 + 39 01 00 00 00 00 02 7D 01 + 39 01 00 00 00 00 02 7F 2C + 39 01 00 00 00 00 02 83 0F + 39 01 00 00 00 00 02 84 65 + 39 01 00 00 00 00 02 87 0F + 39 01 00 00 00 00 02 88 39 + 39 01 00 00 00 00 02 89 14 + 39 01 00 00 00 00 02 8B 36 + 39 01 00 00 00 00 02 8C 39 + 39 01 00 00 00 00 02 8D 39 + 39 01 00 00 00 00 02 8E 39 + 39 01 00 00 00 00 02 95 80 + 39 01 00 00 00 00 02 96 FD + 39 01 00 00 00 00 02 97 14 + 39 01 00 00 00 00 02 98 B3 + 39 01 00 00 00 00 02 99 01 + 39 01 00 00 00 00 02 9A 08 + 39 01 00 00 00 00 02 9B 02 + 39 01 00 00 00 00 02 9C 4C + 39 01 00 00 00 00 02 9D BC + 39 01 00 00 00 00 02 9F AC + 39 01 00 00 00 00 02 A0 FF + 39 01 00 00 00 00 02 A2 44 + 39 01 00 00 00 00 02 A3 78 + 39 01 00 00 00 00 02 A4 F8 + 39 01 00 00 00 00 02 A5 4A + 39 01 00 00 00 00 02 A6 72 + 39 01 00 00 00 00 02 A7 4C + + 39 01 00 00 00 00 02 FF 2C + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 00 02 + 39 01 00 00 00 00 02 01 02 + 39 01 00 00 00 00 02 02 02 + 39 01 00 00 00 00 02 03 16 + 39 01 00 00 00 00 02 04 16 + 39 01 00 00 00 00 02 05 16 + 39 01 00 00 00 00 02 0D 1F + 39 01 00 00 00 00 02 0E 1F + 39 01 00 00 00 00 02 16 1B + 39 01 00 00 00 00 02 17 4B + 39 01 00 00 00 00 02 18 4B + 39 01 00 00 00 00 02 19 4B + 39 01 00 00 00 00 02 2A 03 + 39 01 00 00 00 00 02 4D 16 + 39 01 00 00 00 00 02 4E 02 + 39 01 00 00 00 00 02 4F 2F + 39 01 00 00 00 00 02 53 02 + 39 01 00 00 00 00 02 54 02 + 39 01 00 00 00 00 02 55 02 + 39 01 00 00 00 00 02 56 0E + 39 01 00 00 00 00 02 58 0E + 39 01 00 00 00 00 02 59 0E + 39 01 00 00 00 00 02 61 1F + 39 01 00 00 00 00 02 62 1F + 39 01 00 00 00 00 02 6A 14 + 39 01 00 00 00 00 02 6B 34 + 39 01 00 00 00 00 02 6C 34 + 39 01 00 00 00 00 02 6D 34 + 39 01 00 00 00 00 02 7E 03 + 39 01 00 00 00 00 02 9D 0E + 39 01 00 00 00 00 02 9E 02 + 39 01 00 00 00 00 02 9F 02 + + 39 01 00 00 00 00 02 FF 20 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 C6 00 + 39 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 02 C8 00 + 39 01 00 00 00 00 02 C9 00 + 39 01 00 00 00 00 02 CA 00 + + 39 01 00 00 00 00 02 CB 00 + 39 01 00 00 00 00 02 CC 00 + 39 01 00 00 00 00 02 CD 00 + 39 01 00 00 00 00 02 CE 00 + 39 01 00 00 00 00 02 CF 00 + + 39 01 00 00 00 00 02 D0 00 + 39 01 00 00 00 00 02 D1 00 + 39 01 00 00 00 00 02 D2 00 + 39 01 00 00 00 00 02 D3 00 + 39 01 00 00 00 00 02 D4 00 + + 39 01 00 00 00 00 02 D5 00 + 39 01 00 00 00 00 02 D6 00 + 39 01 00 00 00 00 02 D7 00 + 39 01 00 00 00 00 02 D8 00 + 39 01 00 00 00 00 02 D9 00 + + 39 01 00 00 00 00 02 DA 00 + 39 01 00 00 00 00 02 DB 00 + 39 01 00 00 00 00 02 DC 00 + 39 01 00 00 00 00 02 DD 00 + 39 01 00 00 00 00 02 DE 00 + + 39 01 00 00 00 00 02 DF 00 + 39 01 00 00 00 00 02 E0 00 + 39 01 00 00 00 00 02 E1 00 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 E3 00 + + 39 01 00 00 00 00 02 E4 00 + 39 01 00 00 00 00 02 E5 00 + 39 01 00 00 00 00 02 E6 00 + 39 01 00 00 00 00 02 E7 00 + 39 01 00 00 00 00 02 E8 00 + 39 01 00 00 00 00 02 E9 00 + + + 39 01 00 00 00 00 02 FF 21 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3 + 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E + 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F + 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1 + 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28 + 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63 + 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00 + 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3 + 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26 + 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61 + 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00 + + 39 01 00 00 00 00 02 FF E0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 35 82 + 39 01 00 00 00 00 02 85 32 + + 39 01 00 00 00 00 02 FF F0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 1C 01 + 39 01 00 00 00 00 02 33 01 + 39 01 00 00 00 00 02 5A 00 + + 39 01 00 00 00 00 02 FF D0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 02 54 02 + + 39 01 00 00 00 00 02 FF C0 + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 9C 11 + 39 01 00 00 00 00 02 9D 11 + + 39 01 00 00 00 00 02 FF 2B + 39 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 B7 0A + 39 01 00 00 00 00 02 B8 1C + 39 01 00 00 00 00 02 C0 01 + + 39 01 00 00 00 00 02 FF 10 + 39 01 00 00 00 00 02 35 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 28 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 32 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts new file mode 100755 index 000000000000..baad62db1c7a --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts new file mode 100755 index 000000000000..9c3ad4e97588 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi new file mode 100755 index 000000000000..d8410e7a2bb5 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi @@ -0,0 +1 @@ +#include "bengal-idp-nopmi.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts new file mode 100755 index 000000000000..cc64dfa02fa3 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi new file mode 100755 index 000000000000..6e1d96cc0193 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi @@ -0,0 +1,24 @@ +#include "khaje-pm7250b.dtsi" + +&led_flash_rear { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&led_flash_rear_aux2 { + /delete-property/ flash-source; + /delete-property/ torch-source; + /delete-property/ switch-source; +}; + +&sde_dsi { + /delete-property/ lab-supply; + /delete-property/ ibb-supply; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts new file mode 100755 index 000000000000..01afb9709965 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,board-id = <34 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi new file mode 100755 index 000000000000..eef3e49bcece --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi @@ -0,0 +1 @@ +#include "bengal-idp.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi new file mode 100755 index 000000000000..594e2a5d2406 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi @@ -0,0 +1,3 @@ +/*update the 7250b as per khaje*/ +/*#include "pm7250b.dtsi"*/ + diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts new file mode 100755 index 000000000000..4cdbe3dce003 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje QRD"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi new file mode 100755 index 000000000000..18133e27f395 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi @@ -0,0 +1 @@ +#include "khaje-pm7250b.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts new file mode 100755 index 000000000000..df4c7c1504b0 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE QRD"; + compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi new file mode 100755 index 000000000000..52f2f4c5d4b9 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi @@ -0,0 +1 @@ +#include "bengal-qrd-nopmi.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje.dts b/arch/arm64/boot/dts/vendor/qcom/khaje.dts new file mode 100755 index 000000000000..b522b78fea1b --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khaje.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje SoC"; + compatible = "qcom,khaje"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi new file mode 100755 index 000000000000..06715382c2b9 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi @@ -0,0 +1,3152 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\ + opp-hz = /bits/ 64 ;\ + opp-supported-hw = ;} + +#define DDR_TYPE_LPDDR3 5 +#define DDR_TYPE_LPDDR4X 7 + +/ { + model = "Qualcomm Technologies, Inc. Khaje SoC"; + compatible = "qcom,khaje"; + qcom,msm-id = <518 0x10000>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + swr0 = &swr0; + swr1 = &swr1; + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 7>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 1 7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_region@45700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_region@45e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x45e00000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_mem: smem_region@46000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + removed_mem: removed_region@60000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x60000000 0x0 0x3900000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions@51a00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x51a00000 0x0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@53800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x53800000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: ipa_fw_region@55600000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x55600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@55610000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x55610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@55615000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x55615000 0x0 0x2000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@46200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x46200000 0x0 0x1e00000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + soc: soc { }; +}; + +#include "bengal-coresight.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical", "slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x360>; + status = "ok"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-bengal", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 197 + IRQ_TYPE_EDGE_RISING>; + reg = <0x45f01b8 0x1000>, + <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */ + qca,bt-vdd-io-supply = <&L9A>; /* IO */ + qca,bt-vdd-core-supply = <&L17A>; /* RFA */ + qca,bt-vdd-pa-supply = <&L23A>; /* CH0 */ + qca,bt-vdd-xtal-supply = <&L16A>; /* XO */ + + qca,bt-vdd-io-voltage-level = <1700000 1900000>; + qca,bt-vdd-core-voltage-level = <1304000 1304000>; + qca,bt-vdd-pa-voltage-level = <3000000 3312000>; + qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bee000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x2000>; + }; + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + arm64_cpu_erp { + compatible = "arm,arm64-cpu-erp"; + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + poll-delay-ms = <5000>; + }; + + l2cache_pmu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,l2cache-pmu"; + ranges; + + cluster0@f111000 { + cluster-id = <0>; + interrupts = ; + reg = <0xf111000 0x1000>; + }; + + cluster1@f011000 { + cluster-id = <1>; + interrupts = ; + reg = <0xf011000 0x1000>; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom_seecom: qseecom@61800000 { + compatible = "qcom,qseecom"; + reg = <0x61800000 0x2100000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + ; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc QSEECOM_CE1_CLK>, + <&rpmcc QSEECOM_CE1_CLK>, + <&rpmcc QSEECOM_CE1_CLK>, + <&rpmcc QSEECOM_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@61800000 { + compatible = "qcom,smcinvoke"; + reg = <0x61800000 0x2100000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@1b53000 { + compatible = "qcom,msm-rng"; + reg = <0x1b53000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , /* No vote */ + ; /* 75 MHz */ + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc QCEDEV_CE1_CLK>, + <&rpmcc QCEDEV_CE1_CLK>, + <&rpmcc QCEDEV_CE1_CLK>, + <&rpmcc QCEDEV_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0086 0x0011>, + <&apps_smmu 0x0096 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x92 0>, + <&apps_smmu 0x98 0x1>, + <&apps_smmu 0x9F 0>; + qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x93 0>, + <&apps_smmu 0x9C 0x1>, + <&apps_smmu 0x9E 0>; + qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc QCRYPTO_CE1_CLK>, + <&rpmcc QCRYPTO_CE1_CLK>, + <&rpmcc QCRYPTO_CE1_CLK>, + <&rpmcc QCRYPTO_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0084 0x0011>, + <&apps_smmu 0x0094 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + eud: qcom,msm-eud@1610000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1610000 0x2000>, + <0x1612000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + qcom,eud-clock-vote-req; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + qcom,msm-gladiator-v2@f100000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0xf100000 0xdc00>; + reg-names = "gladiator_base"; + interrupts = ; + clock-names = "atb_clk"; + clocks = <&rpmcc RPM_QDSS_CLK>; + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 + 0x0f0a80b0 0x0f0b80b0>; + qcom,config-arr = <0x0f0880b8 0x0f0980b8 + 0x0f0a80b8 0x0f0b80b8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x0f1d141c 0x0f1d1420 + 0x0f1d1424 0x0f1d1428 + 0x0f1d142c 0x0f1d1430>; + qcom,config-reg = <0x0f1d1434>; + }; + + qcom,lpass@ab00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xab00000 0x00100>; + + vdd_lpi_cx-supply = <&L3A_LEVEL>; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&L2A_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + + clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,mas-crypto = <&mas_crypto_c0>; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,minidump-id = <5>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc 0 282 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom,turing@b300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xb300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,mas-crypto = <&mas_crypto_c0>; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,minidump-id = <7>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from turing */ + interrupts-extended = <&intc 0 265 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c101_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c102_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c103_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0xeb>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_icache100 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x64>; + }; + + l1_icache101 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x65>; + }; + + l1_icache102 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x66>; + }; + + l1_icache103 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache101 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache102 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache103 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + + l2_tlb100 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x124>; + }; + + l2_tlb101 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x125>; + }; + + l2_tlb102 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb103 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x127>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe"; + reg = <0x4744000 0x1000>, <0x4745000 0x1000>, + <0x4748000 0x8000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; + + interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 19 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <78 512 0 0>, <1 606 0 0>, + /* 400 KB/s*/ + <78 512 1046 1600>, + <1 606 1600 1600>, + /* 20 MB/s */ + <78 512 20480 80000>, + <1 606 80000 80000>, + /* 25 MB/s */ + <78 512 25600 250000>, + <1 606 50000 133320>, + /* 50 MB/s */ + <78 512 51200 250000>, + <1 606 65000 133320>, + /* 100 MB/s */ + <78 512 102400 250000>, + <1 606 65000 133320>, + /* 200 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* 400 MB/s */ + <78 512 204800 800000>, + <1 606 200000 300000>, + /* Max. bandwidth */ + <78 512 1338562 4096000>, + <1 606 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <26 26>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>; + qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* Add support for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>; + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 3200>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 250000>, + <1 608 80000 133320>, + /* 25 MB/s */ + <81 512 65360 250000>, + <1 608 100000 133320>, + /* 50 MB/s */ + <81 512 130718 250000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 250000>, + <1 608 150000 133320>, + /* 200 MB/s */ + <81 512 261438 800000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <26 26>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; + + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + status = "disabled"; + }; + + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xdb8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>, <0x4810000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <26 26>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + + thermal_zones: thermal-zones {}; + + tsens0:tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0x04410000 0x8>, + <0x04411000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + tsens-reinit-wa; + #thermal-sensor-cells = <1>; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-bengal"; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + qcom,vm-nav-path; + }; + + gcc: qcom,gcc@1400000 { + compatible = "qcom,bengal-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: qcom,dispcc@5f00000 { + compatible = "qcom,bengal-dispcc", "syscon"; + reg = <0x05f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "cfg_ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: qcom,gpucc@5990000 { + compatible = "qcom,bengal-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mccc_debug: syscon@447d200 { + compatible = "syscon"; + reg = <0x447d200 0x100>; + }; + + cpucc_debug: syscon@f11101c { + compatible = "syscon"; + reg = <0xf11101c 0x4>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,bengal-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,mccc = <&mccc_debug>; + qcom,cpucc = <&cpucc_debug>; + clock-names = "xo_clk_src"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw"; + reg = <0xf521000 0x1000>, <0xf523000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,no-accumulative-counter; + qcom,max-lut-entries = <12>; + #freq-domain-cells = <2>; + }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,bengal-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C01 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C02 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C03 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C04 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C05 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C06 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 28>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <100>; + qcom,qos-maxhold-ms = <20>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + stm_debug_fuse: stm@20f0 { + reg = <0x20f0 0x4>; + }; + + feat_conf5: feat_conf5@6018 { + reg = <0x6018 0x4>; + }; + + feat_conf10: feat_conf10@602c { + reg = <0x602c 0x4>; + }; + + adsp_variant: adsp_variant@6011 { + reg = <0x6011 0x1>; + bits = <3 1>; + }; + + gpu_speed_bin: gpu_speed_bin@6006 { + reg = <0x6006 0x2>; + bits = <5 8>; + }; + + gpu_gaming_bin: gpu_gaming_bin@602d { + reg = <0x602d 0x1>; + bits = <5 1>; + }; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1A0 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + vdd-cx-mx-supply = <&L8A>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L17A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + + qcom,venus@5ab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ab0000 0x20000>; + + vdd-supply = <&gcc_venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,mas-crypto = <&mas_crypto_c0>; + + qcom,core-freq = <240000000>; + qcom,ahb-freq = <240000000>; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xe008>; + }; + + pil_modem: qcom,mss@6080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x6080000 0x100>; + + clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,mas-crypto = <&mas_crypto_c0>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + qcom,sequential-fw-load; + + qcom,msm-bus,name = "pil-modem"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + + /* Inputs from mss */ + interrupts-extended = <&intc 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */ + BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */ + BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */ + BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */ + BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */ + BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */ + BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */ + BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */ + BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */ + BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */ + BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */ + }; + + suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY_DDR( 0, 8, 0xA0); /* 0 MB/s */ + BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */ + BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */ + BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */ + BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */ + BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */ + BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */ + BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */ + BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */ + BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */ + BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */ + BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw-ddr"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw-ddr"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devbw-ddr"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 864000 MHZ_TO_MBPS(200, 8) >, + < 1305600 MHZ_TO_MBPS(451, 8) >, + < 1804800 MHZ_TO_MBPS(768, 8) >; + }; + + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 864000 MHZ_TO_MBPS( 300, 8) >, + < 1305600 MHZ_TO_MBPS( 547, 8) >, + < 1420000 MHZ_TO_MBPS( 768, 8) >, + < 1804800 MHZ_TO_MBPS(1017, 8) >; + }; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 614400 MHZ_TO_MBPS( 200, 8) >, + < 1305600 MHZ_TO_MBPS( 451, 8) >, + < 1804800 MHZ_TO_MBPS( 768, 8) >; + }; + + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 614400 MHZ_TO_MBPS( 300, 8) >, + < 1017600 MHZ_TO_MBPS( 451, 8) >, + < 1420000 MHZ_TO_MBPS( 547, 8) >, + < 1804800 MHZ_TO_MBPS( 768, 8) >; + }; + }; + }; + + cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat { + compatible = "qcom,devbw-ddr"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devbw-ddr"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + + cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x24>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 1056000 MHZ_TO_MBPS(200, 8) >, + < 1401600 MHZ_TO_MBPS(451, 8) >, + < 1804800 MHZ_TO_MBPS(768, 8) >, + < 2016000 MHZ_TO_MBPS(931, 8) >; + }; + + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 451, 8) >, + < 1401600 MHZ_TO_MBPS(1017, 8) >, + < 1804800 MHZ_TO_MBPS(1555, 8) >, + < 2016000 MHZ_TO_MBPS(1804, 8) >; + }; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 652800 MHZ_TO_MBPS( 200, 8) >, + < 1056000 MHZ_TO_MBPS( 451, 8) >, + < 1401600 MHZ_TO_MBPS( 547, 8) >, + < 1536000 MHZ_TO_MBPS( 768, 8) >, + < 2016000 MHZ_TO_MBPS( 931, 8) >; + }; + + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 300, 8) >, + < 1056000 MHZ_TO_MBPS( 547, 8) >, + < 1401680 MHZ_TO_MBPS( 768, 8) >, + < 1804800 MHZ_TO_MBPS(1017, 8) >, + < 2016000 MHZ_TO_MBPS(1804, 8) >; + }; + }; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@0x5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x34000>, + <0x5804000 0x28000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-endp-delay-wa; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,skip-ieob-mask-wa; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core_clk"; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + /* SVS2 */ + , + , + , + /* SVS */ + , + , + , + /* NOMINAL */ + , + , + , + /* TURBO */ + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x0140 0x0>; + qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>; + /* modem tables in IMEM */ + qcom,iommu-dma = "fastmap"; + qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; + qcom,iommu-geometry = <0 0xB0000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x0141 0x0>; + /* ipa-uc ram */ + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x0142 0x0>; + qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + qcom,demux { + compatible = "qcom,demux"; + }; + +tpdm_turing_llm: tpdm@8861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8861000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing_llm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_turing_llm_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing_llm>; + }; + }; + }; + + /delete-node/ tpdm@8a58000; + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_west_out_tpda11: endpoint { + remote-endpoint = + <&tpda11_in_tpdm_west>; + }; + }; + }; + + tpdm_spdm: tpdm@800f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x0800f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_spdm_out_tpda13: endpoint { + remote-endpoint = + <&tpda13_in_tpdm_spdm>; + }; + }; + }; + + /delete-node/ funnel@8861000; + funnel_turing: funnel@8863000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x8863000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_turing_out_tpda5: endpoint { + remote-endpoint = + <&tpda5_in_funnel_turing>; + source = <&tpdm_turing>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing>; + source = <&turing_etm0>; + }; + }; + + port@2 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@3 { + reg = <1>; + funnel_turing_in_tpdm_turing_llm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_llm_out_funnel_turing>; + }; + }; + + port@4 { + reg = <2>; + funnel_turing_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing>; + }; + }; + }; + }; + + /delete-node/ tpda@8004000; + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <0 32>, + <1 32>, + <5 32>, + <11 32>, + <12 32>, + <15 32>; + qcom,cmb-elem-size = <7 32>, + <8 32>, + <10 32>, + <15 64>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda0_in_tpdm_dl_ct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_ct_out_tpda0>; + }; + }; + + port@2 { + reg = <1>; + tpda1_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda1>; + }; + }; + + port@3 { + reg = <5>; + tpda5_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda5>; + }; + }; + + port@4 { + reg = <7>; + tpda7_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda7>; + }; + }; + + port@5 { + reg = <8>; + tpda8_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda8>; + }; + }; + + port@6 { + reg = <10>; + tpda10_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda10>; + }; + }; + + port@7 { + reg = <11>; + tpda11_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda11>; + }; + }; + + port@8 { + reg = <12>; + tpda12_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda12>; + }; + }; + + port@9 { + reg = <13>; + tpda13_in_tpdm_spdm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_spdm_out_tpda13>; + }; + }; + + port@10 { + reg = <15>; + tpda15_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda15>; + }; + }; + + }; + }; + + /delete-node/ cti@8867000; + cti_turing_q6: cti@8862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb966>; + reg = <0x8862000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing-q6"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; + +#include "bengal-gdsc.dtsi" +#include "bengal-usb.dtsi" +#include "bengal-ion.dtsi" +#include "bengal-bus.dtsi" +#include "bengal-vidc.dtsi" +#include "pm6125.dtsi" + +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +#include "msm-arm-smmu-bengal.dtsi" +#include "pm6125-rpm-regulator.dtsi" +#include "bengal-regulator.dtsi" +#include "bengal-pm.dtsi" +#include "bengal-pinctrl.dtsi" +#include "bengal-qupv3.dtsi" +#include "bengal-gpu.dtsi" +#include "bengal-audio.dtsi" +#include "bengal-sde-pll.dtsi" +#include "bengal-sde.dtsi" + +&qupv3_se1_i2c { + status = "ok"; + #include "pm8008.dtsi" +}; + +&pm8008_8 { + /* PM8008 IRQ STAT */ + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active &pm8008_interrupt>; +}; + +&pm8008_regulators { + vdd_l1_l2-supply = <&S6A>; +}; + +&L1P { + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <100000>; +}; + +&L2P { + regulator-max-microvolt = <1056000>; + qcom,min-dropout-voltage = <100000>; +}; + +&L3P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L4P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L5P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L6P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L7P { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&qupv3_se4_2uart { + status = "ok"; +}; + +&qupv3_se3_4uart { + status = "ok"; +}; + +&pm6125_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio4"; + bias-high-impedance; + }; + }; + +}; + +&spmi_bus { + qcom,pm6125@0 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, + <&pm6125_vadc ADC_GPIO2_PU2>; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pm6125_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>; + + /* Channel nodes */ + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; + qcom,clock-freq-threshold = <300000000>; +}; + +#include "bengal-thermal.dtsi" +#include "camera/bengal-camera.dtsi" +#include "msm-rdbg.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi index 92af60e7c31d..6ef7b79e37e3 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi @@ -38,6 +38,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <3>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3230000 0x0>; @@ -82,6 +83,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <2>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3210000 0x0>; @@ -121,6 +123,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <1>; qcom,mipi-sdw-block-packing-mode = <0>; swrm-io-base = <0x3250000 0x0>; diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi index 6a45603c96ff..bc96ee834022 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi @@ -41,6 +41,9 @@ &qupv3_se1_i2c { status = "ok"; + qcom,clk-freq-out = <100000>; + #address-cells = <1>; + #size-cells = <0>; lt9611: lt,lt9611@2b { compatible = "lt,lt9611uxc"; reg = <0x2b>; diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi index 6db79a1e942e..016273cfd222 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi @@ -213,6 +213,89 @@ }; }; + qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { + qupv3_se13_default_cts: + qupv3_se13_default_cts { + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_default_rtsrx: + qupv3_se13_default_rtsrx { + mux { + pins = "gpio37", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio37", "gpio39"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_default_tx: + qupv3_se13_default_tx { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_ctsrx: qupv3_se13_ctsrx { + mux { + pins = "gpio36", "gpio39"; + function = "qup13"; + }; + + config { + pins = "gpio36", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_rts: qupv3_se13_rts { + mux { + pins = "gpio37"; + function = "qup13"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_tx: qupv3_se13_tx { + mux { + pins = "gpio38"; + function = "qup13"; + }; + + config { + pins = "gpio38"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { qupv3_se12_2uart_active: qupv3_se12_2uart_active { mux { @@ -261,6 +344,7 @@ }; }; + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { qupv3_se17_ctsrx: qupv3_se17_ctsrx { mux { @@ -2242,7 +2326,7 @@ config { pins = "gpio94"; bias-disable; /* No PULL */ - drive-strength = <4>; /* 4 MA */ + drive-strength = <8>; /* 8 MA */ }; }; @@ -2256,7 +2340,7 @@ config { pins = "gpio94"; bias-pull-down; /* PULL DOWN */ - drive-strength = <4>; /* 4 MA */ + drive-strength = <8>; /* 8 MA */ }; }; @@ -2438,7 +2522,7 @@ config { pins = "gpio93"; bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ + drive-strength = <8>; /* 8 MA */ }; }; @@ -2452,7 +2536,7 @@ config { pins = "gpio93"; bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ + drive-strength = <8>; /* 8 MA */ output-low; }; }; @@ -2515,6 +2599,64 @@ }; }; + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 2 */ + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 2 */ + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 2 */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 2 */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + cam_sensor_active_3: cam_sensor_active_3 { /* RESET 3 */ mux { diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi index a33644875f25..0317c96ad987 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi @@ -486,6 +486,27 @@ qcom,change-sampling-rate; status = "disabled"; }; + qupv3_se13_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se13_default_cts>, + <&qupv3_se13_default_rtsrx>, <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 39 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + }; /* I2C */ qupv3_se8_i2c: i2c@a80000 { diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi index c34d57b25f58..7d325134e8a9 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi @@ -14,6 +14,16 @@ status = "ok"; }; +&qupv3_se13_4uart { + status = "ok"; + qrc:qrc@100 { + compatible = "qcom,qrc-uart"; + status = "ok"; + qcom,qrc-reset-gpio = <&tlmm 114 0>; + qcom,qrc-boot-gpio = <&tlmm 109 0>; + }; +}; + &pm8150l_gpios { lt9611_rst_pin_out { lt9611_rst_pin_out_default: lt9611_rst_pin_out_default { diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi index 602fad881340..6f2fd424cf60 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi @@ -1005,7 +1005,6 @@ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; - cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; /* Morpheus has to be HIGH */ status = "ok"; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/kona.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi index 4de49f7f5bb5..58d5a1a8ed68 100755 --- a/arch/arm64/boot/dts/vendor/qcom/kona.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi @@ -4865,6 +4865,7 @@ reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 20 0>; qcom,bt-en-gpio = <&tlmm 21 0>; + qcom,sw-ctrl-gpio = <&tlmm 124 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; @@ -5110,20 +5111,25 @@ qfprom: qfprom@780000 { compatible = "qcom,qfprom"; - reg = <0x00784000 0x3000>; + reg = <0x00780000 0x5000>; #address-cells = <1>; #size-cells = <1>; read-only; ranges; - gpu_lm_efuse: gpu_lm_efuse@5c8 { - reg = <0x5c8 0x4>; + gpu_lm_efuse: gpu_lm_efuse@45c8 { + reg = <0x45c8 0x4>; }; - gpu_speed_bin: gpu_speed_bin@19b { - reg = <0x19b 0x1>; + gpu_speed_bin: gpu_speed_bin@419b { + reg = <0x419b 0x1>; bits = <5 3>; }; + + thermal_speed_bin: thermal-speed-bin@1a2 { + reg = <0x1a2 0x1>; + bits = <7 1>; + }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi index ab9c30c385eb..030f274442a7 100755 --- a/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi @@ -37,6 +37,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <3>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3230000 0x0>; @@ -86,6 +87,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <2>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3210000 0x0>; @@ -129,6 +131,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <1>; qcom,mipi-sdw-block-packing-mode = <0>; swrm-io-base = <0x3250000 0x0>; diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi index 5349c384e75f..1664a4d29729 100755 --- a/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi @@ -221,7 +221,7 @@ qcom,gpu-freq = <650000000>; qcom,bus-freq = <10>; qcom,bus-min = <8>; - qcom,bus-max = <12>; + qcom,bus-max = <10>; }; /* NOM */ @@ -230,7 +230,7 @@ qcom,gpu-freq = <565000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; - qcom,bus-max = <11>; + qcom,bus-max = <10>; }; /* SVS_L1 */ @@ -301,7 +301,7 @@ qcom,gpu-freq = <650000000>; qcom,bus-freq = <10>; qcom,bus-min = <8>; - qcom,bus-max = <12>; + qcom,bus-max = <10>; }; /* NOM */ @@ -310,7 +310,7 @@ qcom,gpu-freq = <565000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; - qcom,bus-max = <11>; + qcom,bus-max = <10>; }; /* SVS_L1 */ @@ -372,7 +372,7 @@ qcom,gpu-freq = <650000000>; qcom,bus-freq = <10>; qcom,bus-min = <8>; - qcom,bus-max = <12>; + qcom,bus-max = <10>; }; /* NOM */ @@ -381,7 +381,7 @@ qcom,gpu-freq = <565000000>; qcom,bus-freq = <9>; qcom,bus-min = <8>; - qcom,bus-max = <11>; + qcom,bus-max = <10>; }; /* SVS_L1 */ diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi index 75ded597b40d..19fc3118e175 100755 --- a/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi @@ -88,11 +88,11 @@ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; - qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000 - 2700000 2700000>; + qcom,sde-max-per-pipe-bw-kbps = <3200000 3200000 + 3200000 3200000>; - qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000 - 2700000 2700000>; + qcom,sde-max-per-pipe-bw-high-kbps = <3200000 3200000 + 3200000 3200000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, @@ -117,8 +117,8 @@ qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; qcom,sde-has-idle-pc; - qcom,sde-max-bw-low-kbps = <4200000>; - qcom,sde-max-bw-high-kbps = <5100000>; + qcom,sde-max-bw-low-kbps = <4400000>; + qcom,sde-max-bw-high-kbps = <5900000>; qcom,sde-min-core-ib-kbps = <2500000>; qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <1600000>; @@ -276,18 +276,18 @@ "camera_concurrency", "cwb_concurrency"; qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>; - qcom,sde-limit-values = <0x1 2700000>, - <0x11 2700000>, - <0x9 2700000>, - <0x19 2700000>, - <0x2 2700000>, - <0x12 2700000>, - <0xa 2700000>, - <0x1a 2700000>, - <0x4 5100000>, - <0x14 5100000>, + qcom,sde-limit-values = <0x1 3200000>, + <0x11 3200000>, + <0x9 3200000>, + <0x19 3200000>, + <0x2 3200000>, + <0x12 3200000>, + <0xa 3200000>, + <0x1a 3200000>, + <0x4 5900000>, + <0x14 5900000>, <0xc 4400000>, - <0x1c 4200000>; + <0x1c 4400000>; }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi index e829c98fc8fa..cc536ca6f2a8 100755 --- a/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi @@ -1149,6 +1149,182 @@ }; }; + mdm-core-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + modem_core_0_trip0: modem-core-0-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_core_0_trip1: modem-core-0-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_core_0_trip2: modem-core-0-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_tj1_cdev { + trip = <&modem_core_0_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + modem_tj2_cdev { + trip = <&modem_core_0_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + modem_tj3_cdev { + trip = <&modem_core_0_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-core-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + modem_core_1_trip0: modem-core-1-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_core_1_trip1: modem-core-1-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_core_1_trip2: modem-core-1-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_tj1_cdev { + trip = <&modem_core_1_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + modem_tj2_cdev { + trip = <&modem_core_1_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + modem_tj3_cdev { + trip = <&modem_core_1_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-vec-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + modem_vec_trip0: modem-vec-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_vec_trip1: modem-vec-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_vec_trip2: modem-vec-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_tj1_cdev { + trip = <&modem_vec_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + modem_tj2_cdev { + trip = <&modem_vec_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + modem_tj3_cdev { + trip = <&modem_vec_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-scl-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + modem_scl_trip0: modem-scl-trip0 { + temperature = <95000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_scl_trip1: modem-scl-trip1 { + temperature = <105000>; + hysteresis = <15000>; + type = "passive"; + }; + + modem_scl_trip2: modem-scl-trip2 { + temperature = <115000>; + hysteresis = <15000>; + type = "passive"; + }; + }; + + cooling-maps { + modem_tj1_cdev { + trip = <&modem_scl_trip0>; + cooling-device = <&modem_tj 1 1>; + }; + + modem_tj2_cdev { + trip = <&modem_scl_trip1>; + cooling-device = <&modem_tj 2 2>; + }; + + modem_tj3_cdev { + trip = <&modem_scl_trip2>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + min-temp-0-lowf { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi index e262e3b1ac87..8475f0c2a239 100755 --- a/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi @@ -37,6 +37,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <3>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3230000 0x0>; @@ -81,6 +82,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <2>; qcom,mipi-sdw-block-packing-mode = <1>; swrm-io-base = <0x3210000 0x0>; @@ -120,6 +122,7 @@ "lpass_audio_hw_vote"; clocks = <&lpass_core_hw_vote 0>, <&lpass_audio_hw_vote 0>; + qcom,swr-master-version = <0x01050001>; qcom,swr_master_id = <1>; qcom,mipi-sdw-block-packing-mode = <0>; swrm-io-base = <0x3250000 0x0>; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi index b72cd436d71b..4bd8513aa130 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi @@ -308,12 +308,6 @@ qcom,scratch-buf-support; }; - msm_cam_smmu_cb2: msm_cam_smmu_cb2 { - compatible = "qcom,msm-cam-smmu-cb"; - label = "vfe_secure"; - qcom,secure-context; - }; - msm_cam_smmu_cb3: msm_cam_smmu_cb3 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x1c00 0x00>; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi index 26d3c8b2f525..aa7d410429ab 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi @@ -4,26 +4,34 @@ compatible = "qcom,kgsl-busmon"; }; + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + + opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */ + + opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */ + + opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. 297 MHz */ + + opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */ + + opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. 557 MHz */ + + opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. 595 MHz */ + + opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. 672 MHz */ + + opp-739 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. 739 MHz */ + }; + /* Bus governor */ gpubw: qcom,gpubw { compatible = "qcom,devbw"; governor = "bw_vbif"; qcom,src-dst-ports = <26 512>; - /* - * Need to configure 2x Clock as BIMC - * Internally Divides by 2 for Gen1 DDR PHY. - */ + operating-points-v2 = <&gpu_bw_tbl>; qcom,active-only; - qcom,bw-tbl = - < 0 >, /* Off */ - < 769 >, /* 1. DDR:100.80 MHz BIMC: 201.60 MHz */ - < 1611 >, /* 2. DDR:211.20 MHz BIMC: 422.40 MHz */ - < 2270 >, /* 3. DDR:297.60 MHz BIMC: 595.20 MHz */ - < 2929 >, /* 4. DDR:384.00 MHz BIMC: 768.00 MHz */ - < 4248 >, /* 5. DDR:556.80 MHz BIMC: 1113.60 MHz */ - < 4541 >, /* 6. DDR:595.20 MHz BIMC: 1190.40 MHz */ - < 5126 >, /* 7. DDR:672.00 MHz BIMC: 1344.00 MHz */ - < 5639 >; /* 8. DDR:739.20 MHz BIMC: 1478.40 MHz */ }; msm_gpu: qcom,kgsl-3d0@1c00000 { @@ -158,7 +166,6 @@ * The gpu can only program a single context bank * at this fixed offset. */ - qcom,protect = <0xa000 0x1000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_GFX_TCU_CLK>, <&gcc GCC_GTCU_AHB_CLK>, @@ -169,6 +176,7 @@ gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; iommus = <&gfx_iommu 0>; + qcom,iommu-dma = "disabled"; qcom,gpu-offset = <0xa000>; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi index 235c653460bb..0f2e80ed924a 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi @@ -1,5 +1,4 @@ #include "msm8937-mdss.dtsi" -#include &mdss_dsi { vdda-supply = <&pm8937_l2>; vddio-supply = <&pm8937_l6>; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi index 6fe1977fc829..7135a3d04986 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi @@ -1,5 +1,30 @@ #include +&apsscc { + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; +}; + &soc { qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; @@ -188,28 +213,7 @@ trip = <&cpu_trip>; cooling-device = <&CPU0 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu1_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU1 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu2_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU2 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu3_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU3 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; + THERMAL_NO_LIMIT>; }; }; }; @@ -254,8 +258,7 @@ cpu0_cdev { trip = <&apc1_cpu0_trip>; cooling-device = - <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu0_isolate 1 1>; }; }; }; @@ -277,8 +280,7 @@ cpu1_cdev { trip = <&apc1_cpu1_trip>; cooling-device = - <&CPU1 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu1_isolate 1 1>; }; }; }; @@ -300,8 +302,7 @@ cpu2_cdev { trip = <&apc1_cpu2_trip>; cooling-device = - <&CPU2 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu2_isolate 1 1>; }; }; }; @@ -323,8 +324,7 @@ cpu3_cdev { trip = <&apc1_cpu3_trip>; cooling-device = - <&CPU3 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu3_isolate 1 1>; }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi index 362c1368fa6d..982a9f6f2f31 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi @@ -60,6 +60,9 @@ <&apps_iommu 0x807 0x00>, <&apps_iommu 0x808 0x27>, <&apps_iommu 0x811 0x20>; + qcom,iommu-dma-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0xfff>; virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>; @@ -71,18 +74,24 @@ iommus = <&apps_iommu 0x900 0x00>, <&apps_iommu 0x90a 0x04>, <&apps_iommu 0x909 0x22>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x12c00000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x241>; virtual-addr-pool = <0x4b000000 0x12c00000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ }; secure_pixel_cb { compatible = "qcom,msm-vidc,context-bank"; label = "venus_sec_pixel"; iommus = <&apps_iommu 0x90c 0x20>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x106>; virtual-addr-pool = <0x25800000 0x25800000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ }; secure_non_pixel_cb { @@ -92,9 +101,12 @@ <&apps_iommu 0x907 0x08>, <&apps_iommu 0x908 0x20>, <&apps_iommu 0x90d 0x20>; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x480>; virtual-addr-pool = <0x1000000 0x24800000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ }; venus_bus_ddr { @@ -102,7 +114,7 @@ label = "venus-ddr"; qcom,bus-master = ; qcom,bus-slave = ; - qcom,bus-governor = "venus-ddr-gov"; + qcom,mode = "venus-ddr"; qcom,bus-range-kbps = <1000 917000>; }; @@ -111,7 +123,7 @@ label = "venus-arm9-ddr"; qcom,bus-master = ; qcom,bus-slave = ; - qcom,bus-governor = "performance"; + qcom,mode = "performance"; qcom,bus-range-kbps = <1 1>; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi index 5b573ce94fe8..8628a7b36c85 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi @@ -1,6 +1,7 @@ #include "skeleton64.dtsi" #include -#include +#include +#include #include #include #include @@ -20,18 +21,6 @@ }; aliases { - /* smdtty devices */ - smd1 = &smdtty_apps_fm; - smd2 = &smdtty_apps_riva_bt_acl; - smd3 = &smdtty_apps_riva_bt_cmd; - smd4 = &smdtty_mbalbridge; - smd5 = &smdtty_apps_riva_ant_cmd; - smd6 = &smdtty_apps_riva_ant_data; - smd7 = &smdtty_data1; - smd8 = &smdtty_data4; - smd11 = &smdtty_data11; - smd21 = &smdtty_data21; - smd36 = &smdtty_loopback; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ sdhc2 = &sdhc_2; /* SDC2 for SD card */ spi3 = &spi_3; @@ -444,7 +433,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0xff00>; + interrupts = <1 7 IRQ_TYPE_LEVEL_HIGH>; }; slim_msm: slim@c140000 { @@ -561,7 +550,7 @@ }; rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8917"; + compatible = "qcom,rpmcc-qm215"; #clock-cells = <1>; }; @@ -578,19 +567,25 @@ #reset-cells = <1>; }; + cpu_debug: syscon@0b01101c { + compatible = "syscon"; + reg = <0x0b01101c 0x4>; + }; + debugcc: qcom,cc-debug { compatible = "qcom,msm8917-debugcc"; reg = <0x1874000 0x4>, <0xb01101c 0x8>; reg-names = "cc_base", "meas"; qcom,gcc = <&gcc>; + qcom,cpu = <&cpu_debug>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo_clk_src"; #clock-cells = <1>; }; gcc_mdss: qcom,gcc-mdss@1800000 { - compatible = "qcom,gcc-mdss-8917"; + compatible = "qcom,gcc-mdss-qm215"; reg = <0x1800000 0x80000>; clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>; @@ -598,13 +593,16 @@ #clock-cells = <1>; }; - clock_cpu: qcom,cpu-clock-8939@b111050 { - compatible = "qcom,cpu-clock-8917"; - reg = <0xb011050 0x8>, + apsscc: qcom,clock-cpu@b011050 { + compatible = "qcom,cpu-clock-qm215"; + reg = <0xb011050 0x8>, + <0xb016000 0x34>, <0x00a412c 0x8>; - reg-names = "apcs-c1-rcg-base", "efuse"; - qcom,num-cluster; - vdd-c1-supply = <&apc_vreg_corner>; + reg-names = "apcs-c1-rcg-base", + "apcs_pll", "efuse"; + cpu-vdd-supply = <&apc_vreg_corner>; + vdd_dig_ao-supply = <&pm8916_s1_level_ao>; + vdd_hf_pll-supply = <&pm8916_l7_ao>; clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GPLL0_AO_OUT_MAIN>; clock-names = "xo_ao", "gpll0_ao" ; @@ -641,14 +639,10 @@ msm_cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; - /* TODO - * clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", - * "cpu3_clk"; - * clocks = <&clock_cpu clk_a53_bc_clk>, - * <&clock_cpu clk_a53_bc_clk>, - * <&clock_cpu clk_a53_bc_clk>, - * <&clock_cpu clk_a53_bc_clk>; - */ + clock-names = "cpu0_clk"; + clocks = <&apsscc APCS_MUX_C1_CLK>; + + qcom,governor-per-policy; qcom,cpufreq-table = < 960000 >, @@ -863,7 +857,7 @@ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; @@ -881,7 +875,7 @@ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; @@ -950,7 +944,7 @@ <0x200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = ; + interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; @@ -1194,6 +1188,26 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "DIAG"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "DIAG_CNTL"; + }; + + qcom,diag_cmd { + qcom,smd-channels = "DIAG_CMD"; + }; + + qcom,diag_dci { + qcom,smd-channels = "DIAG_2"; + }; + + qcom.diag_dci_cmd { + qcom,smd-channels = "DIAG_2_CMD"; + }; }; adsp { @@ -1202,6 +1216,7 @@ qcom,ipc = <&apcs 0 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; + mbox-names = "adsp_smem"; label = "adsp"; qcom,smd-channels = "IPCRTR"; @@ -1209,6 +1224,18 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "DIAG"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "DIAG_CNTL"; + }; + + qcom,apr_tal_rpmsg { + qcom,smd-channels = "apr_audio_svc"; + }; }; wcnss { @@ -1224,6 +1251,14 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "APPS_RIVA_DATA"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "APPS_RIVA_CTRL"; + }; }; rpm { @@ -1240,63 +1275,39 @@ }; - qcom,smdtty { - compatible = "qcom,smdtty"; - - smdtty_apps_fm: qcom,smdtty-apps-fm { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_FM"; - }; - - smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; - }; - - smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; - }; - - smdtty_mbalbridge: qcom,smdtty-mbalbridge { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "MBALBRIDGE"; - }; - - smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; - }; - - smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; - }; + qcom,smsm { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; - smdtty_data1: qcom,smdtty-data1 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA1"; - }; + qcom,ipc-1 = <&apcs 0 13>; + qcom,ipc-2 = <&apcs 0 9>; + qcom,ipc-3 = <&apcs 0 19>; - smdtty_data4: qcom,smdtty-data4 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA4"; + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; }; - smdtty_data11: qcom,smdtty-data11 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA11"; + modem_smsm: modem@1 { + reg = <1>; + interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; - smdtty_data21: qcom,smdtty-data21 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA21"; + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; - smdtty_loopback: smdtty-loopback { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "LOOPBACK"; - qcom,smdtty-dev-name = "LOOPBACK_TTY"; + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -1304,39 +1315,89 @@ compatible = "qcom,smdpkt"; qcom,smdpkt-data5-cntl { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA5_CNTL"; qcom,smdpkt-dev-name = "smdcntl0"; }; qcom,smdpkt-data22 { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA22"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA22"; qcom,smdpkt-dev-name = "smd22"; }; qcom,smdpkt-data40-cntl { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA40_CNTL"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA40_CNTL"; qcom,smdpkt-dev-name = "smdcntl8"; }; qcom,smdpkt-data2 { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA2"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA2"; qcom,smdpkt-dev-name = "at_mdm0"; }; qcom,smdpkt-apr-apps2 { - qcom,smdpkt-remote = "adsp"; - qcom,smdpkt-port-name = "apr_apps2"; + qcom,smdpkt-edge = "adsp"; + qcom,smdpkt-ch-name = "apr_apps2"; qcom,smdpkt-dev-name = "apr_apps2"; }; - qcom,smdpkt-loopback { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "LOOPBACK"; - qcom,smdpkt-dev-name = "smd_pkt_loopback"; + qcom,smdpkt-apps-riva-bt-acl { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL"; + qcom,smdpkt-dev-name = "smd2"; + qcom,smdpkt-fragmented-read; + }; + + qcom,smdpkt-apps-riva-bt-cmd { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD"; + qcom,smdpkt-dev-name = "smd3"; + qcom,smdpkt-fragmented-read; + }; + + qcom,smdpkt-mbalbridge { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "MBALBRIDGE"; + qcom,smdpkt-dev-name = "smd4"; + }; + + qcom,smdpkt-apps-riva-ant-cmd { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD"; + qcom,smdpkt-dev-name = "smd5"; + }; + + qcom,smdpkt-apps-riva-ant-data { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA"; + qcom,smdpkt-dev-name = "smd6"; + }; + + qcom,smdpkt-data1 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA1"; + qcom,smdpkt-dev-name = "smd7"; + }; + + qcom,smdpkt-data4 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA4"; + qcom,smdpkt-dev-name = "smd8"; + }; + + qcom,smdpkt-data11 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA11"; + qcom,smdpkt-dev-name = "smd11"; + }; + + qcom,smdpkt-data21 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA21"; + qcom,smdpkt-dev-name = "smd21"; }; }; @@ -1348,11 +1409,20 @@ bam_dmux: qcom,bam_dmux@4044000 { compatible = "qcom,bam_dmux"; reg = <0x4044000 0x19000>; - interrupts = ; qcom,rx-ring-size = <32>; qcom,max-rx-mtu = <4096>; qcom,fast-shutdown; qcom,no-cpu-affinity; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pwrctrl", "pwrctrlack"; + + interrupts-extended = + <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, + <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "dmux", "ctrl", "ack"; }; sdcc1_ice: sdcc1ice@7803000 { @@ -1539,7 +1609,7 @@ qcom,ssctl-instance-id = <0x12>; qcom,qdsp6v56-1-8-inrush-current; qcom,reset-clk; - + qcom,iommu-vmid = <0xF>; /* VMID_MSS_MSA */ /* Inputs from mss */ /* TBD */ interrupts-extended = <&modem_smp2p_in 0 0>, @@ -1834,7 +1904,8 @@ "wlan_tx_status", "alarms_txctl", "alarms_tactl", "pronto_mcu_base"; - interrupts = <0 145 0 0 146 0>; + interrupts = <0 145 IRQ_TYPE_EDGE_RISING>, + <0 146 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>; @@ -1881,6 +1952,9 @@ clock-names = "xo", "rf_clk"; + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state"; + qcom,has-autodetect-xo; qcom,is-pronto-v3; qcom,has-pronto-hw; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi index 2b852e0d18a0..8dd711d075f9 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi @@ -1,3 +1,4 @@ +#include #include "msm-audio-lpass.dtsi" #include "msm8953-wsa881x.dtsi" @@ -7,10 +8,10 @@ }; &soc { - qcom,msm-audio-apr { + audio_apr: qcom,msm-audio-apr { compatible = "qcom,msm-audio-apr"; - msm_audio_apr_dummy { - compatible = "qcom,msm-audio-apr-dummy"; + q6core: q6core { + compatible = "qcom,q6core-audio"; }; }; @@ -81,37 +82,25 @@ <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_mi2s5>, - /* TBD - * &sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, - * <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, - */ <&bt_sco_rx>, <&bt_sco_tx>, <&int_fm_rx>, <&int_fm_tx>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, - <&incall_music_rx>, <&incall_music_2_rx>; - /* TBD - * <&proxy_rx>, <&proxy_tx>; - */ + <&incall_music_rx>, <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>; asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6", - "msm-dai-q6-dev.16384", "msmdai-q6-dev.16385", - "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", - "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", - "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", - "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770"; - /* TBD - * "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195"; - */ + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195"; asoc-codec = <&stub_codec>, <&msm_digital_codec>, <&pmic_analog_codec>; @@ -154,6 +143,8 @@ status = "okay"; compatible = "qcom,wsa881x-i2c-codec"; reg = <0x0f>; + clock-names = "wsa_mclk"; + clocks = <&wsa881x_analog_clk 0>; qcom,wsa-analog-vi-gpio = <&wsa881x_analog_vi_gpio>; qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; qcom,wsa-analog-reset-gpio = @@ -188,6 +179,14 @@ pinctrl-1 = <&wsa_reset_off>; }; + wsa881x_analog_clk: wsa_ana_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,codec-lpass-clk-id = <0x300>; + #clock-cells = <1>; + }; + ext_codec: sound-9335 { status = "disabled"; compatible = "qcom,msm8952-audio-slim-codec"; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi index 76bf80723d8a..16120ab7c082 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi @@ -306,25 +306,22 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x400 0x00>, <&apps_iommu 0x2400 0x00>; + qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>; label = "vfe"; qcom,scratch-buf-support; }; - msm_cam_smmu_cb2: msm_cam_smmu_cb2 { - compatible = "qcom,msm-cam-smmu-cb"; - label = "vfe_secure"; - qcom,secure-context; - }; - msm_cam_smmu_cb3: msm_cam_smmu_cb3 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x1c00 0x00>; + qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>; label = "cpp"; }; msm_cam_smmu_cb4: msm_cam_smmu_cb4 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x1800 0x00>; + qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>; label = "jpeg_enc0"; }; }; @@ -397,6 +394,8 @@ <106 512 0 0>; qcom,msm-bus-vector-dyn-vote; qcom,micro-reset; + qcom,src-clock-rates = <133333333 160000000 200000000 + 266666667 308570000 320000000 360000000>; qcom,cpp-fw-payload-info { qcom,stripe-base = <156>; qcom,plane-base = <141>; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi index 0571cc1abd0d..6183246a7763 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi @@ -4,28 +4,42 @@ compatible = "qcom,kgsl-busmon"; }; + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + + opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */ + + opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */ + + opp-278 { opp-hz = /bits/ 64 < 2124 >; }; /* 3. 278 MHz */ + + opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */ + + opp-537 { opp-hz = /bits/ 64 < 4101 >; }; /* 5. 537 MHz */ + + opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 6. 557 MHz */ + + opp-700 { opp-hz = /bits/ 64 < 5346 >; }; /* 7. 700 MHz */ + + opp-748 { opp-hz = /bits/ 64 < 5712 >; }; /* 8. 748 MHz */ + + opp-806 { opp-hz = /bits/ 64 < 6152 >; }; /* 9. 806 MHz */ + + opp-922 { opp-hz = /bits/ 64 < 7031 >; }; /* 10. 922 MHz */ + }; + gpubw: qcom,gpubw { compatible = "qcom,devbw"; governor = "bw_vbif"; qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; /* * active-only flag is used while registering the bus * governor.It helps release the bus vote when the CPU * subsystem is inactiv3 */ qcom,active-only; - qcom,bw-tbl = - < 0 >, /* off */ - < 769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */ - < 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */ - < 2124 >, /* 3. DDR:278.40 MHz BIMC: 139.20 MHz */ - < 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */ - < 4101 >, /* 5. DDR:537.60 MHz BIMC: 268.80 MHz */ - < 4248 >, /* 6. DDR:556.80 MHz BIMC: 278.40 MHz */ - < 5346 >, /* 7. DDR:662.40 MHz BIMC: 331.20 MHz */ - < 5712 >, /* 8. DDR:748.80 MHz BIMC: 374.40 MHz */ - < 6152 >, /* 9. DDR:806.40 MHz BIMC: 403.20 MHz */ - < 7031 >; /* 10. DDR:921.60 MHz BIMC: 460.80 MHz */ }; msm_gpu: qcom,kgsl-3d0@1c00000 { @@ -214,8 +228,6 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x1c40000 0x10000>; - qcom,protect = <0x40000 0x10000>; - qcom,micro-mmu-control = <0x6000>; clocks = <&gcc GCC_OXILI_AHB_CLK>, <&gcc GCC_BIMC_GFX_CLK>; @@ -228,6 +240,7 @@ compatible = "qcom,smmu-kgsl-cb"; label = "gfx3d_user"; iommus = <&kgsl_smmu 0>; + qcom,iommu-dma = "disabled"; qcom,gpu-offset = <0x48000>; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi index 85cd896b6014..0b4f974c344d 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi @@ -1,6 +1,15 @@ #include "msm8937-interposer-sdm439.dtsi" #include "sdm429-cpu.dtsi" +&clock_cpu { + qcom,cpu-isolation { + /delete-node/ cpu4-isolate; + /delete-node/ cpu5-isolate; + /delete-node/ cpu6-isolate; + /delete-node/ cpu7-isolate; + }; +}; + &soc { /delete-node/ etm@619c000; /delete-node/ etm@619d000; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi index 2342d00ac070..59b8a28287ce 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi @@ -174,11 +174,17 @@ smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { compatible = "qcom,smmu_mdp_unsec"; iommus = <&apps_iommu 0x2800 0>; /* For NS ctx bank */ + qcom,iommu-dma-addr-pool = <0x08000000 0xF8000000>; + qcom,iommu-earlymap; /* for cont-splash */ + }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { compatible = "qcom,smmu_mdp_sec"; iommus = <&apps_iommu 0x2801 0>; /* For SEC Ctx Bank */ + qcom,iommu-dma-addr-pool = <0x08000000 0xF8000000>; + qcom,secure-context-bank; + qcom,iommu-vmid = <0x11>; /*VMID_CP_SEC_DISPLAY*/ }; mdss_fb0: qcom,mdss_fb_primary { @@ -228,13 +234,12 @@ clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>; - /* TODO - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>, - * <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>; - */ + <&gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk"; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi index b1b405618bc5..28788978ace0 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi @@ -1,5 +1,50 @@ #include +&clock_cpu { + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; + &soc { qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; @@ -238,56 +283,14 @@ trip = <&cpu_trip>; cooling-device = <&CPU0 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu1_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU1 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu2_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU2 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu3_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU3 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; + THERMAL_NO_LIMIT>; }; cpu4_cdev { trip = <&cpu_trip>; cooling-device = <&CPU4 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu5_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU5 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu6_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU6 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; - }; - - cpu7_cdev { - trip = <&cpu_trip>; - cooling-device = - <&CPU7 THERMAL_NO_LIMIT - (THERMAL_MAX_LIMIT-1)>; + THERMAL_NO_LIMIT>; }; }; }; @@ -310,8 +313,7 @@ cpu0_cdev { trip = <&apc1_cpu0_trip>; cooling-device = - <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu0_isolate 1 1>; }; }; }; @@ -334,8 +336,7 @@ cpu1_cdev { trip = <&apc1_cpu1_trip>; cooling-device = - <&CPU1 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu1_isolate 1 1>; }; }; }; @@ -358,8 +359,7 @@ cpu2_cdev { trip = <&apc1_cpu2_trip>; cooling-device = - <&CPU2 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu2_isolate 1 1>; }; }; }; @@ -382,8 +382,7 @@ cpu3_cdev { trip = <&apc1_cpu3_trip>; cooling-device = - <&CPU3 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu3_isolate 1 1>; }; }; }; @@ -406,29 +405,25 @@ cpu4_cdev { trip = <&cpuss0_step_trip>; cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu4_isolate 1 1>; }; cpu5_cdev { trip = <&cpuss0_step_trip>; cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu5_isolate 1 1>; }; cpu6_cdev { trip = <&cpuss0_step_trip>; cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu6_isolate 1 1>; }; cpu7_cdev { trip = <&cpuss0_step_trip>; cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&cpu7_isolate 1 1>; }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi index 5cb28189b1ff..fe387d302a0e 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi @@ -60,6 +60,9 @@ <&apps_iommu 0x807 0x00>, <&apps_iommu 0x808 0x27>, <&apps_iommu 0x811 0x20>; + qcom,iommu-dma-addr-pool = <0x5dc00000 0x7f000000 + 0xdcc00000 0x1000000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0xfff>; virtual-addr-pool = <0x5dc00000 0x7f000000 0xdcc00000 0x1000000>; @@ -71,18 +74,24 @@ iommus = <&apps_iommu 0x900 0x00>, <&apps_iommu 0x90a 0x04>, <&apps_iommu 0x909 0x22>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x12c00000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x241>; virtual-addr-pool = <0x4b000000 0x12c00000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ }; secure_pixel_cb { compatible = "qcom,msm-vidc,context-bank"; label = "venus_sec_pixel"; iommus = <&apps_iommu 0x90c 0x20>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x106>; virtual-addr-pool = <0x25800000 0x25800000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ }; secure_non_pixel_cb { @@ -92,9 +101,12 @@ <&apps_iommu 0x907 0x08>, <&apps_iommu 0x908 0x20>, <&apps_iommu 0x90d 0x20>; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; buffer-types = <0x480>; virtual-addr-pool = <0x1000000 0x24800000>; qcom,secure-context-bank; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ }; /* Buses */ @@ -103,7 +115,7 @@ label = "venus-ddr"; qcom,bus-master = ; qcom,bus-slave = ; - qcom,bus-governor = "venus-ddr-gov"; + qcom,mode = "venus-ddr"; qcom,bus-range-kbps = <1000 917000>; }; @@ -112,7 +124,7 @@ label = "venus-arm9-ddr"; qcom,bus-master = ; qcom,bus-slave = ; - qcom,bus-governor = "performance"; + qcom,mode = "performance"; qcom,bus-range-kbps = <1 1>; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi index 5bdb157d8500..577fa3149542 100755 --- a/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi @@ -4,7 +4,7 @@ #include #include #include -#include +#include #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} @@ -24,7 +24,7 @@ compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { @@ -34,7 +34,7 @@ dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,avb"; + fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; }; @@ -122,18 +122,6 @@ }; aliases { - /* smdtty devices */ - smd1 = &smdtty_apps_fm; - smd2 = &smdtty_apps_riva_bt_acl; - smd3 = &smdtty_apps_riva_bt_cmd; - smd4 = &smdtty_mbalbridge; - smd5 = &smdtty_apps_riva_ant_cmd; - smd6 = &smdtty_apps_riva_ant_data; - smd7 = &smdtty_data1; - smd8 = &smdtty_data4; - smd11 = &smdtty_data11; - smd21 = &smdtty_data21; - smd36 = &smdtty_loopback; i2c2 = &i2c_2; i2c5 = &i2c_5; spi3 = &spi_3; @@ -311,7 +299,7 @@ cpu-pmu { compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0xff00>; + interrupts = <1 7 IRQ_TYPE_LEVEL_HIGH>; }; qcom,sps { @@ -580,15 +568,14 @@ }; rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8937"; + compatible = "qcom,rpmcc-sdm439"; #clock-cells = <1>; }; gcc: qcom,gcc@1800000 { - compatible = "qcom,gcc-msm8937", "syscon"; + compatible = "qcom,gcc-sdm439", "syscon"; reg = <0x1800000 0x80000>; - <0x00a6018 0x00004>; - reg-names = "cc_base", "gpu-bin"; + reg-names = "cc_base"; qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>; vdd_cx-supply = <&pm8937_s2_level>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; @@ -611,10 +598,10 @@ gcc_mdss: qcom,gcc-mdss@1800000 { compatible = "qcom,gcc-mdss-msm8937"; reg = <0x1800000 0x80000>; - clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; + clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_1_CLK>, + <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; @@ -931,13 +918,13 @@ /* TODO * clocks = <&clock_cpu clk_cci_clk/>; */ - governor = "cpufreq"; + governor = "performance"; freq-tbl-khz = < 400000 >, < 533333 >; }; - ddr_bw_opp_table: generic-bw-opp-table { + ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 100, 8); /* 769 MB/s */ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ @@ -953,7 +940,7 @@ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; @@ -971,7 +958,7 @@ cpu_cpu_ddr_latfloor: qcom,cpu-cpu-ddr-latfloor { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; @@ -1164,7 +1151,7 @@ <0x200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = ; + interrupts = ; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <1>; @@ -1473,6 +1460,26 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "DIAG"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "DIAG_CNTL"; + }; + + qcom,diag_cmd { + qcom,smd-channels = "DIAG_CMD"; + }; + + qcom,diag_dci { + qcom,smd-channels = "DIAG_2"; + }; + + qcom.diag_dci_cmd { + qcom,smd-channels = "DIAG_2_CMD"; + }; }; adsp { @@ -1481,6 +1488,7 @@ qcom,ipc = <&apcs 0 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; + mbox-names = "adsp_smem"; label = "adsp"; qcom,smd-channels = "IPCRTR"; @@ -1488,6 +1496,18 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "DIAG"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "DIAG_CNTL"; + }; + + qcom,apr_tal_rpmsg { + qcom,smd-channels = "apr_audio_svc"; + }; }; wcnss { @@ -1503,6 +1523,14 @@ qcom,net-id = <1>; qcom,low-latency; }; + + qcom,diag { + qcom,smd-channels = "APPS_RIVA_DATA"; + }; + + qcom,diag_cntl { + qcom,smd-channels = "APPS_RIVA_CTRL"; + }; }; rpm { @@ -1519,63 +1547,39 @@ }; }; - qcom,smdtty { - compatible = "qcom,smdtty"; - - smdtty_apps_fm: qcom,smdtty-apps-fm { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_FM"; - }; - - smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_BT_ACL"; - }; - - smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_BT_CMD"; - }; - - smdtty_mbalbridge: qcom,smdtty-mbalbridge { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "MBALBRIDGE"; - }; - - smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD"; - }; - - smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data { - qcom,smdtty-remote = "wcnss"; - qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA"; - }; + qcom,smsm { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; - smdtty_data1: qcom,smdtty-data1 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA1"; - }; + qcom,ipc-1 = <&apcs 0 13>; + qcom,ipc-2 = <&apcs 0 9>; + qcom,ipc-3 = <&apcs 0 19>; - smdtty_data4: qcom,smdtty-data4 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA4"; + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; }; - smdtty_data11: qcom,smdtty-data11 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA11"; + modem_smsm: modem@1 { + reg = <1>; + interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; - smdtty_data21: qcom,smdtty-data21 { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "DATA21"; + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; - smdtty_loopback: smdtty-loopback { - qcom,smdtty-remote = "modem"; - qcom,smdtty-port-name = "LOOPBACK"; - qcom,smdtty-dev-name = "LOOPBACK_TTY"; + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; }; }; @@ -1583,39 +1587,89 @@ compatible = "qcom,smdpkt"; qcom,smdpkt-data5-cntl { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA5_CNTL"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA5_CNTL"; qcom,smdpkt-dev-name = "smdcntl0"; }; qcom,smdpkt-data22 { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA22"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA22"; qcom,smdpkt-dev-name = "smd22"; }; qcom,smdpkt-data40-cntl { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA40_CNTL"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA40_CNTL"; qcom,smdpkt-dev-name = "smdcntl8"; }; qcom,smdpkt-data2 { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "DATA2"; + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA2"; qcom,smdpkt-dev-name = "at_mdm0"; }; qcom,smdpkt-apr-apps2 { - qcom,smdpkt-remote = "adsp"; - qcom,smdpkt-port-name = "apr_apps2"; + qcom,smdpkt-edge = "adsp"; + qcom,smdpkt-ch-name = "apr_apps2"; qcom,smdpkt-dev-name = "apr_apps2"; }; - qcom,smdpkt-loopback { - qcom,smdpkt-remote = "modem"; - qcom,smdpkt-port-name = "LOOPBACK"; - qcom,smdpkt-dev-name = "smd_pkt_loopback"; + qcom,smdpkt-apps-riva-bt-acl { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL"; + qcom,smdpkt-dev-name = "smd2"; + qcom,smdpkt-fragmented-read; + }; + + qcom,smdpkt-apps-riva-bt-cmd { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD"; + qcom,smdpkt-dev-name = "smd3"; + qcom,smdpkt-fragmented-read; + }; + + qcom,smdpkt-mbalbridge { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "MBALBRIDGE"; + qcom,smdpkt-dev-name = "smd4"; + }; + + qcom,smdpkt-apps-riva-ant-cmd { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD"; + qcom,smdpkt-dev-name = "smd5"; + }; + + qcom,smdpkt-apps-riva-ant-data { + qcom,smdpkt-edge = "wcnss"; + qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA"; + qcom,smdpkt-dev-name = "smd6"; + }; + + qcom,smdpkt-data1 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA1"; + qcom,smdpkt-dev-name = "smd7"; + }; + + qcom,smdpkt-data4 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA4"; + qcom,smdpkt-dev-name = "smd8"; + }; + + qcom,smdpkt-data11 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA11"; + qcom,smdpkt-dev-name = "smd11"; + }; + + qcom,smdpkt-data21 { + qcom,smdpkt-edge = "modem"; + qcom,smdpkt-ch-name = "DATA21"; + qcom,smdpkt-dev-name = "smd21"; }; }; @@ -2071,7 +2125,8 @@ "wlan_tx_status", "alarms_txctl", "alarms_tactl", "pronto_mcu_base"; - interrupts = <0 145 0 0 146 0>; + interrupts = <0 145 IRQ_TYPE_EDGE_RISING>, + <0 146 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq"; qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>; @@ -2121,6 +2176,9 @@ qcom,snoc-wcnss-clock-freq = <200000000>; + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state"; + qcom,has-autodetect-xo; qcom,is-pronto-v3; qcom,has-pronto-hw; @@ -2131,11 +2189,20 @@ bam_dmux: qcom,bam_dmux@4044000 { compatible = "qcom,bam_dmux"; reg = <0x4044000 0x19000>; - interrupts = <0 162 1>; qcom,rx-ring-size = <32>; qcom,max-rx-mtu = <4096>; qcom,fast-shutdown; qcom,no-cpu-affinity; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pwrctrl", "pwrctrlack"; + + interrupts-extended = + <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, + <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "dmux", "ctrl", "ack"; }; ssc_sensors: qcom,msm-ssc-sensors { diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi index 45cc99acaf38..f10c0094586d 100755 --- a/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi @@ -1,9 +1,13 @@ +#include +#include + &spmi_bus { - qcom,pm8916@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <1>; + pm8916_0: pm8916@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; pm8916_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; @@ -13,8 +17,8 @@ pm8916_pon: qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; reg = <0x800 0x100>; - interrupts = <0x0 0x8 0x0>, - <0x0 0x8 0x1>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; interrupt-names = "kpdpwr", "resin"; qcom,pon-dbc-delay = <15625>; qcom,system-reset; @@ -38,77 +42,35 @@ }; }; - pm8916_mpps: mpps { + pm8916_gpios: pinctrl@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; gpio-controller; #gpio-cells = <2>; - #address-cells = <1>; - #size-cells = <1>; - label = "pm8916-mpp"; - - mpp@a000 { - reg = <0xa000 0x100>; - qcom,pin-num = <1>; - }; - - mpp@a100 { - reg = <0xa100 0x100>; - qcom,pin-num = <2>; - }; - - mpp@a200 { - reg = <0xa200 0x100>; - qcom,pin-num = <3>; - }; - - mpp@a300 { - reg = <0xa300 0x100>; - qcom,pin-num = <4>; - }; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8916_gpio1", "pm8916_gpio2", + "pm8916_gpio3", "pm8916_gpio4"; }; - pm8916_gpios: gpios { + pm8916_mpps: mpps@a000 { + compatible = "qcom,pm8916-mpp"; + reg = <0xa000 0x400>; gpio-controller; #gpio-cells = <2>; - #address-cells = <1>; - #size-cells = <1>; - label = "pm8916-gpio"; - - gpio@c000 { - reg = <0xc000 0x100>; - qcom,pin-num = <1>; - }; - - gpio@c100 { - reg = <0xc100 0x100>; - qcom,pin-num = <2>; - }; - - gpio@c200 { - reg = <0xc200 0x100>; - qcom,pin-num = <3>; - }; - - gpio@c300 { - reg = <0xc300 0x100>; - qcom,pin-num = <4>; - }; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8916_mpp1", "pm8916_mpp2", + "pm8916_mpp3", "pm8916_mpp4"; }; pm8916_rtc: qcom,pm8916_rtc { - compatible = "qcom,qpnp-rtc"; - #address-cells = <1>; - #size-cells = <1>; - qcom,qpnp-rtc-write = <0>; - qcom,qpnp-rtc-alarm-pwrup = <0>; - - qcom,pm8916_rtc_rw@6000 { - reg = <0x6000 0x100>; - }; - - qcom,pm8916_rtc_alarm@6100 { - reg = <0x6100 0x100>; - interrupts = <0x0 0x61 0x1>; - }; + compatible = "qcom,pm8916-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; pm8916_vadc: vadc@3100 { @@ -116,12 +78,13 @@ reg = <0x3100 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x31 0x0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eoc-int-en-set"; qcom,adc-bit-resolution = <15>; qcom,adc-vdd-reference = <1800>; qcom,vadc-poll-eoc; qcom,pmic-revid = <&pm8916_revid>; + #thermal-sensor-cells = <1>; chan@8 { label = "die_temp"; @@ -160,23 +123,25 @@ pm8916_tz: qcom,temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400 0x100>; - interrupts = <0x0 0x24 0x0>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; label = "pm8916_tz"; qcom,channel-num = <8>; qcom,threshold-set = <0>; qcom,temp_alarm-vadc = <&pm8916_vadc>; + #thermal-sensor-cells = <0>; }; pm8916_adc_tm: vadc@3400 { + compatible = "qcom,adc-tm-rev2"; reg = <0x3400 0x100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x34 0x0>, - <0x0 0x34 0x3>, - <0x0 0x34 0x4>; - interrupt-names = "eoc-int-en-set", - "high-thr-en-set", - "low-thr-en-set"; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set", + "high-thr-en-set", + "low-thr-en-set"; qcom,adc-bit-resolution = <15>; qcom,adc-vdd-reference = <1800>; qcom,adc_tm-vadc = <&pm8916_vadc>; @@ -184,9 +149,12 @@ }; pm8916_chg: qcom,charger { + compatible = "qcom,qpnp-linear-charger"; #address-cells = <1>; #size-cells = <1>; + #cooling-cells = <2>; + qcom,v-cutoff-mv = <3400>; qcom,vddmax-mv = <4200>; qcom,vddsafe-mv = <4200>; qcom,vinmin-mv = <4308>; @@ -201,6 +169,7 @@ qcom,batt-hot-percentage = <25>; qcom,batt-cold-percentage = <80>; qcom,tchg-mins = <232>; + qcom,resume-soc = <99>; qcom,chg-vadc = <&pm8916_vadc>; qcom,chg-adc_tm = <&pm8916_adc_tm>; @@ -208,32 +177,34 @@ qcom,chgr@1000 { reg = <0x1000 0x100>; - interrupts = <0x0 0x10 0x7>, - <0x0 0x10 0x6>, - <0x0 0x10 0x5>, - <0x0 0x10 0x0>; - interrupt-names = "chg-done", - "chg-failed", - "fast-chg-on", - "vbat-det-lo"; + interrupts = + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "chg-done", + "chg-failed", + "fast-chg-on", + "vbat-det-lo"; }; qcom,bat-if@1200 { reg = <0x1200 0x100>; - interrupts = <0x0 0x12 0x1>, - <0x0 0x12 0x0>; - interrupt-names = "bat-temp-ok", - "batt-pres"; + interrupts = <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "bat-temp-ok", + "batt-pres"; }; qcom,usb-chgpth@1300 { reg = <0x1300 0x100>; - interrupts = <0 0x13 0x4>, - <0 0x13 0x2>, - <0 0x13 0x1>; - interrupt-names = "usb-over-temp", - "chg-gone", - "usbin-valid"; + interrupts = + <0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0 0x13 0x2 IRQ_TYPE_EDGE_RISING>, + <0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb-over-temp", + "chg-gone", + "usbin-valid"; }; qcom,chg-misc@1600 { @@ -242,6 +213,7 @@ }; pm8916_bms: qcom,vmbms { + compatible = "qcom,qpnp-vm-bms"; #address-cells = <1>; #size-cells = <1>; status = "disabled"; @@ -266,7 +238,6 @@ qcom,force-s3-on-suspend; qcom,force-s2-in-charging; qcom,report-charger-eoc; - qcom,resume-soc = <99>; qcom,batt-pres-status@1208 { reg = <0x1208 0x1>; @@ -278,12 +249,12 @@ qcom,vm-bms@4000 { reg = <0x4000 0x100>; - interrupts = <0x0 0x40 0x0>, - <0x0 0x40 0x1>, - <0x0 0x40 0x2>, - <0x0 0x40 0x3>, - <0x0 0x40 0x4>, - <0x0 0x40 0x5>; + interrupts = <0x0 0x40 0x0 IRQ_TYPE_NONE>, + <0x0 0x40 0x1 IRQ_TYPE_NONE>, + <0x0 0x40 0x2 IRQ_TYPE_NONE>, + <0x0 0x40 0x3 IRQ_TYPE_NONE>, + <0x0 0x40 0x4 IRQ_TYPE_NONE>, + <0x0 0x40 0x5 IRQ_TYPE_NONE>; interrupt-names = "leave_cv", "enter_cv", @@ -295,192 +266,24 @@ }; pm8916_leds: qcom,leds@a100 { + compatible = "qcom,leds-qpnp"; reg = <0xa100 0x100>; label = "mpp"; }; }; - qcom,pm8916@1 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <1>; - - regulator@1400 { - regulator-name = "8916_s1"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1700 0x300>; - status = "disabled"; - - qcom,ctl@1700 { - reg = <0x1700 0x100>; - }; - - qcom,ps@1800 { - reg = <0x1800 0x100>; - }; - - qcom,freq@1900 { - reg = <0x1900 0x100>; - }; - }; - - regulator@1a00 { - regulator-name = "8916_s3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1a00 0x300>; - status = "disabled"; - - qcom,ctl@1a00 { - reg = <0x1a00 0x100>; - }; - - qcom,ps@1b00 { - reg = <0x1b00 0x100>; - }; - - qcom,freq@1c00 { - reg = <0x1c00 0x100>; - }; - }; - - regulator@1d00 { - regulator-name = "8916_s4"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1d00 0x300>; - status = "disabled"; - - qcom,ctl@1d00 { - reg = <0x1d00 0x100>; - }; - - qcom,ps@1e00 { - reg = <0x1e00 0x100>; - }; - - qcom,freq@1f00 { - reg = <0x1f00 0x100>; - }; - - }; - - regulator@4000 { - regulator-name = "8916_l1"; - reg = <0x4000 0x100>; - status = "disabled"; - }; - - regulator@4100 { - regulator-name = "8916_l2"; - reg = <0x4100 0x100>; - status = "disabled"; - }; - - regulator@4200 { - regulator-name = "8916_l3"; - reg = <0x4200 0x100>; - status = "disabled"; - }; - - regulator@4300 { - regulator-name = "8916_l4"; - reg = <0x4300 0x100>; - status = "disabled"; - }; - - regulator@4400 { - regulator-name = "8916_l5"; - reg = <0x4400 0x100>; - status = "disabled"; - }; - - regulator@4500 { - regulator-name = "8916_l6"; - reg = <0x4500 0x100>; - status = "disabled"; - }; - - regulator@4600 { - regulator-name = "8916_l7"; - reg = <0x4600 0x100>; - status = "disabled"; - }; - - regulator@4700 { - regulator-name = "8916_l8"; - reg = <0x4700 0x100>; - status = "disabled"; - }; - - regulator@4800 { - regulator-name = "8916_l9"; - reg = <0x4800 0x100>; - status = "disabled"; - }; - - regulator@4900 { - regulator-name = "8916_l10"; - reg = <0x4900 0x100>; - status = "disabled"; - }; - - regulator@4a00 { - regulator-name = "8916_l11"; - reg = <0x4a00 0x100>; - status = "disabled"; - }; - - regulator@4b00 { - regulator-name = "8916_l12"; - reg = <0x4b00 0x100>; - status = "disabled"; - }; - - regulator@4c00 { - regulator-name = "8916_l13"; - reg = <0x4c00 0x100>; - status = "disabled"; - }; - - regulator@4d00 { - regulator-name = "8916_l14"; - reg = <0x4d00 0x100>; - status = "disabled"; - }; - - regulator@4e00 { - regulator-name = "8916_l15"; - reg = <0x4e00 0x100>; - status = "disabled"; - }; - - regulator@4f00 { - regulator-name = "8916_l16"; - reg = <0x4f00 0x100>; - status = "disabled"; - }; - - regulator@5000 { - regulator-name = "8916_l17"; - reg = <0x5000 0x100>; - status = "disabled"; - }; - - regulator@5100 { - regulator-name = "8916_l18"; - reg = <0x5100 0x100>; - status = "disabled"; - }; + pm8916_1: pm8916@1 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; pm8916_pwm: qcom,pwms@bc00 { compatible = "qcom,pwm-lpg"; reg = <0xbc00 0x100>; - reg-names = "qpnp-lpg-channel-base"; - qcom,channel-id = <0>; - qcom,supported-sizes = <6>, <9>; + reg-names = "lpg-base"; #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; }; pm8916_vib: qcom,vibrator@c000 { @@ -491,16 +294,17 @@ }; pm8916_tombak_dig: msm8x16_wcd_codec@f000 { + compatible = "qcom,msm8x16_wcd_codec"; reg = <0xf000 0x100>; interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0>, - <0x1 0xf0 0x1>, - <0x1 0xf0 0x2>, - <0x1 0xf0 0x3>, - <0x1 0xf0 0x4>, - <0x1 0xf0 0x5>, - <0x1 0xf0 0x6>, - <0x1 0xf0 0x7>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>; interrupt-names = "spk_cnp_int", "spk_clip_int", "spk_ocp_int", @@ -538,17 +342,19 @@ "cdc-vdda-cp"; qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + qcom,subsys-name = "modem"; }; pm8916_tombak_analog: msm8x16_wcd_codec@f100 { + compatible = "qcom,msm8x16_wcd_codec"; reg = <0xf100 0x100>; interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf1 0x0>, - <0x1 0xf1 0x1>, - <0x1 0xf1 0x2>, - <0x1 0xf1 0x3>, - <0x1 0xf1 0x4>, - <0x1 0xf1 0x5>; + interrupts = <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; interrupt-names = "ear_ocp_int", "hphr_ocp_int", "hphl_ocp_det", @@ -556,18 +362,5 @@ "hphr_cnp_int", "hphl_cnp_int"; }; - - pm8916_bcm: qpnp-buck-current-monitor@1800 { - reg = <0x1800 0x100>; - interrupts = <1 0x18 0>, <1 0x18 1>; - interrupt-names = "iwarning", "icritical"; - qcom,enable-current-monitor; - qcom,icrit-init-threshold-pc = <90>; - qcom,iwarn-init-threshold-pc = <70>; - qcom,icrit-polling-delay-msec = <1000>; - qcom,iwarn-polling-delay-msec = <2000>; - - status = "disabled"; - }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi index d81ac710471d..05a07ecfdedd 100755 --- a/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi @@ -283,21 +283,8 @@ }; pm8953_rtc: qcom,pm8953_rtc { - spmi-dev-container; - compatible = "qcom,qpnp-rtc"; - #address-cells = <1>; - #size-cells = <1>; - qcom,qpnp-rtc-write = <0>; - qcom,qpnp-rtc-alarm-pwrup = <0>; - - qcom,pm8953_rtc_rw@6000 { - reg = <0x6000 0x100>; - }; - - qcom,pm8953_rtc_alarm@6100 { - reg = <0x6100 0x100>; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; + compatible = "qcom,pm8916-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; pm8953_typec: qcom,pm8953_typec@bf00 { @@ -333,6 +320,7 @@ reg = <0xbc00 0x100>; reg-names = "lpg-base"; #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; }; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi index 05859267a9ee..ce76e9010dfc 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi @@ -5,14 +5,8 @@ qcom,smmu-sid-mask = /bits/ 64 <0xf>; }; -&soc { - qcom,msm-audio-apr { - compatible = "qcom,msm-audio-apr"; - msm_audio_apr_dummy { - compatible = "qcom,msm-audio-apr-dummy"; - }; - }; +&soc { qcom,avtimer@c0a300c { compatible = "qcom,avtimer"; reg = <0x0c0a300c 0x4>, @@ -21,6 +15,13 @@ qcom,clk-div = <27>; }; + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + q6core: q6core { + compatible = "qcom,q6core-audio"; + }; + }; + int_codec: sound { status = "okay"; compatible = "qcom,msm8952-audio-codec"; @@ -76,8 +77,6 @@ <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_mi2s5>, - <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, - <&sb_3_rx>, <&sb_3_tx>, <&sb_4_rx>, <&sb_4_tx>, <&bt_sco_rx>, <&bt_sco_tx>, <&int_fm_rx>, <&int_fm_tx>, <&afe_pcm_rx>, <&afe_pcm_tx>, @@ -90,10 +89,6 @@ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6", - "msm-dai-q6-dev.16384", "msmdai-q6-dev.16385", - "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", - "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", - "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293", "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi index aad0017ec22c..9169b3b8ff3a 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi @@ -15,7 +15,7 @@ reg = <0x1b34000 0x1000>, <0x1b00030 0x4>; reg-names = "csiphy", "csiphy_clk_mux"; - interrupts = <0 78 0>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "csiphy"; clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, @@ -38,7 +38,7 @@ reg = <0x1b35000 0x1000>, <0x1b00038 0x4>; reg-names = "csiphy", "csiphy_clk_mux"; - interrupts = <0 79 0>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "csiphy"; clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, @@ -60,7 +60,7 @@ compatible = "qcom,csid-v3.4.3", "qcom,csid"; reg = <0x1b30000 0x400>; reg-names = "csid"; - interrupts = <0 51 0>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1088000>; qcom,mipi-csi-vdd-supply = <&pm8916_l2>; @@ -304,25 +304,22 @@ compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x400 0x00>, <&apps_iommu 0x2400 0x00>; + qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>; label = "vfe"; qcom,scratch-buf-support; }; - msm_cam_smmu_cb2: msm_cam_smmu_cb2 { - compatible = "qcom,msm-cam-smmu-cb"; - label = "vfe_secure"; - qcom,secure-context; - }; - msm_cam_smmu_cb3: msm_cam_smmu_cb3 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x1c00 0x00>; + qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>; label = "cpp"; }; msm_cam_smmu_cb4: msm_cam_smmu_cb4 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_iommu 0x1800 0x00>; + qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>; label = "jpeg_enc0"; }; }; @@ -395,6 +392,8 @@ <106 512 0 0>; qcom,msm-bus-vector-dyn-vote; qcom,micro-reset; + qcom,src-clock-rates = <133333333 160000000 200000000 + 266666667 308570000 320000000 360000000>; qcom,cpp-fw-payload-info { qcom,stripe-base = <156>; qcom,plane-base = <141>; diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi index fa08b0f866d5..2433e885a68b 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi @@ -5,6 +5,7 @@ /* add rpm-smd node again */ rpm_bus: qcom,rpm-smd { + interrupts = ; compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; rpm-channel-type = <15>; /* SMD_APPS_RPM */ @@ -36,10 +37,6 @@ }; }; - qcom,cpu-clock-8939@b111050 { - /delete-property/ vdd-c1-supply; - }; - qcom,gcc@1800000 { /delete-property/ vdd_cx-supply; /delete-property/ vdd_hf_dig-supply; @@ -194,10 +191,6 @@ }; }; -&clock_cpu { - vdd-c1-supply = <&apc_vreg_corner>; -}; - &gcc { vdd_cx-supply = <&pm8916_s1_level>; vdd_hf_dig-supply = <&pm8916_s1_level_ao>; diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi index ab48a9ed54ca..56910403b318 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi @@ -1,4 +1,5 @@ #include +#include &blsp1_uart2 { status = "ok"; @@ -28,6 +29,12 @@ status = "ok"; }; +&pm8916_vadc { + batt_therm { + qcom,scale-fn-type = ; + }; +}; + &soc { gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215.dts b/arch/arm64/boot/dts/vendor/qcom/qm215.dts index 7d6f0477ba6d..e6ddd75b5202 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215.dts +++ b/arch/arm64/boot/dts/vendor/qcom/qm215.dts @@ -2,8 +2,7 @@ #include "qm215.dtsi" #include "qm215-pm8916.dtsi" -/* TBD */ -/* #include "qm215-audio.dtsi" */ +#include "qm215-audio.dtsi" / { model = "Qualcomm Technologies, Inc. QM215"; diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi index 93e1afcb9326..baddee565cf6 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi @@ -23,10 +23,6 @@ }; }; -&rpmcc { - compatible = "qcom,rpmcc-qm215"; -}; - &gcc { compatible = "qcom,gcc-qm215", "syscon"; }; @@ -35,6 +31,16 @@ compatible = "qcom,qm215-debugcc"; }; +&msm_cpufreq { + /delete-property/qcom,cpufreq-table; + qcom,cpufreq-table = + < 960000 >, + < 1094400 >, + < 1209600 >, + < 1248000 >, + < 1305600 >; +}; + /* GPU overrides */ &msm_gpu { diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi b/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi index 3cfa38c0c168..e2089e05554c 100755 --- a/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi @@ -8,3 +8,761 @@ }; #include "kona-v2.1-gpu.dtsi" + +&soc { + qcom-thermal-qfprom { + compatible = "qcom,thermal-qfprom-device"; + nvmem-cells = <&thermal_speed_bin>; + nvmem-cell-names = "thermal_speed_bin"; + qcom,thermal-qfprom-bit-values = <0x1>; + qcom,thermal-zone-enable-list = "gpuss-max-iot-step", + "cpu-0-0-iot-step", + "cpu-0-1-iot-step", + "cpu-0-2-iot-step", + "cpu-0-3-iot-step", + "cpu-1-0-iot-step", + "cpu-1-1-iot-step", + "cpu-1-2-iot-step", + "cpu-1-3-iot-step", + "cpu-1-4-iot-step", + "cpu-1-5-iot-step", + "cpu-1-6-iot-step", + "cpu-1-7-iot-step", + "cwlan-iot-step", + "video-iot-step", + "ddr-iot-step", + "q6-hvx-iot-step", + "camera-iot-step", + "cmpss-iot-step", + "npu-iot-step"; + qcom,thermal-zone-disable-list = "gpuss-max-step", + "cpu-0-0-step", + "cpu-0-1-step", + "cpu-0-2-step", + "cpu-0-3-step", + "cpu-1-0-step", + "cpu-1-1-step", + "cpu-1-2-step", + "cpu-1-3-step", + "cpu-1-4-step", + "cpu-1-5-step", + "cpu-1-6-step", + "cpu-1-7-step", + "cwlan-step", + "video-step", + "ddr-step", + "q6-hvx-step", + "camera-step", + "cmpss-step", + "npu-step"; + }; +}; + +&thermal_zones { + gpuss-max-iot-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + + trips { + gpu_iot_trip0: gpu-trip0 { + temperature = <110000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpu_iot_trip0>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + pop-mem-step { + status = "disabled"; + }; + + cpu-0-0-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpu00_iot_config: cpu00-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_iot_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + }; + }; + + cpu-0-1-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpu01_iot_config: cpu01-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_iot_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + }; + }; + + cpu-0-2-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpu02_iot_config: cpu02-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_iot_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + }; + }; + + cpu-0-3-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpu03_iot_config: cpu03-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_iot_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpu-1-0-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_10_iot_config: cpufreq-10-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu10_iot_config: cpu10-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_10_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu10_cdev { + trip = <&cpu10_iot_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-1-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_11_iot_config: cpufreq-11-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu11_iot_config: cpu11-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_11_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu11_cdev { + trip = <&cpu11_iot_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-2-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_12_iot_config: cpufreq-12-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu12_iot_config: cpu12-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_12_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu12_cdev { + trip = <&cpu12_iot_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-3-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_13_iot_config: cpufreq-13-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu13_iot_config: cpu13-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_13_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu13_cdev { + trip = <&cpu13_iot_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpu-1-4-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_14_iot_config: cpufreq-14-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu14_iot_config: cpu14-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_14_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu14_cdev { + trip = <&cpu14_iot_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + }; + }; + + cpu-1-5-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_15_iot_config: cpufreq-15-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu15_iot_config: cpu15-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_15_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu15_cdev { + trip = <&cpu15_iot_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + }; + }; + + cpu-1-6-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_16_iot_config: cpufreq-16-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu16_iot_config: cpu16-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_16_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu16_cdev { + trip = <&cpu16_iot_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + }; + }; + + cpu-1-7-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cpufreq_17_iot_config: cpufreq-17-config { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + + cpu17_iot_config: cpu17-config { + temperature = <122000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpufreq_cdev { + trip = <&cpufreq_17_iot_config>; + cooling-device = <&cpu7_notify 1 1>; + }; + + cpu17_cdev { + trip = <&cpu17_iot_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cwlan-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cwlan_iot_trip0: cwlan-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&cwlan_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&cwlan_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&cwlan_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&cwlan_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&cwlan_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + video-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + video_iot_trip0: video-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&video_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&video_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&video_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&video_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&video_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + ddr-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + ddr_iot_trip0: ddr-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&ddr_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&ddr_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&ddr_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&ddr_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&ddr_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + q6-hvx-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + q6_hvx_iot_trip0: q6-hvx-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&q6_hvx_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&q6_hvx_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&q6_hvx_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&q6_hvx_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&q6_hvx_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + camera-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + camera_iot_trip0: camera-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&camera_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&camera_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&camera_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&camera_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&camera_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + cmpss-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + cmpss_iot_trip0: cmpss-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&cmpss_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&cmpss_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&cmpss_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&cmpss_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&cmpss_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + npu-iot-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + disable-thermal-zone; + trips { + npu_iot_trip0: npu-trip0 { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&npu_iot_trip0>; + cooling-device = <&msm_cdsp_rm 3 3>; + }; + + gpu-cdev { + trip = <&npu_iot_trip0>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + + modem-pa-cdev { + trip = <&npu_iot_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&npu_iot_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + + npu_cdev { + trip = <&npu_iot_trip0>; + cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi index d1749dc7e02c..944023aa267f 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi @@ -31,25 +31,21 @@ reg = <0x100>; enable-method = "psci"; cpu-release-addr = <0x0 0x90000000>; - efficiency = <1024>; + capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0>; next-level-cache = <&L2_1>; #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; - /* A53 L2 dump not supported */ - qcom,dump-size = <0x0>; }; L1_I_100: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; }; L1_D_100: l1-dcache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; }; }; @@ -59,18 +55,16 @@ reg = <0x101>; enable-method = "psci"; cpu-release-addr = <0x0 0x90000000>; - efficiency = <1024>; + capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0>; next-level-cache = <&L2_1>; #cooling-cells = <2>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; }; L1_D_101: l1-dcache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; }; }; @@ -80,18 +74,16 @@ reg = <0x102>; enable-method = "psci"; cpu-release-addr = <0x0 0x90000000>; - efficiency = <1024>; + capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0>; next-level-cache = <&L2_1>; #cooling-cells = <2>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; }; L1_D_102: l1-dcache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; }; }; @@ -101,18 +93,16 @@ reg = <0x103>; enable-method = "psci"; cpu-release-addr = <0x0 0x90000000>; - efficiency = <1024>; + capacity-dmips-mhz = <1024>; sched-energy-costs = <&CPU_COST_0>; next-level-cache = <&L2_1>; #cooling-cells = <2>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x8800>; }; L1_D_103: l1-dcache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x9000>; }; }; @@ -122,13 +112,13 @@ CPU_COST_0: core-cost0 { busy-cost-data = < - 960000 159 - 1305600 207 - 1497600 256 - 1708800 327 - 1804800 343 - 1958400 445 - 2016000 470 + 488 159 + 663 207 + 761 256 + 868 327 + 917 343 + 995 445 + 1024 470 >; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi index 6c42cd19eaf9..b43a72e6d3de 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi @@ -105,13 +105,7 @@ }; &gcc { - compatible = "qcom,gcc-sdm429"; - reg = <0x1800000 0x80000>, - <0xb016000 0x00040>; - reg-names = "cc_base", "apcs_c1_base"; vdd_cx-supply = <&pm8953_s2_level>; - vdd_hf_dig-supply = <&pm8953_s2_level_ao>; - vdd_hf_pll-supply = <&pm8953_l7_ao>; }; &debugcc { @@ -199,6 +193,29 @@ < 533333333 3>; #clock-cells = <1>; + + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; }; /* Disable secure_mem node */ @@ -218,13 +235,11 @@ }; &gcc_mdss { - compatible = "qcom,gcc-mdss-sdm429"; - /* TODO - * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; - */ + compatible = "qcom,gcc-mdss-sdm439"; + clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi index 3f0e9e2944f7..45af372f64f7 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi @@ -74,7 +74,7 @@ }; &pm8953_1 { - pmic_analog_codec: analog-codec@f000 { + pmic_analog_codec: anlg-cdc@f000 { status = "okay"; compatible = "qcom,pmic-analog-codec"; reg = <0xf000 0x200>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi index 6e93d68567b6..2702749eb3b0 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi @@ -191,7 +191,7 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; - qcom,led-flash-src = ; + qcom,led-flash-src = <&led_flash0>; qcom,eeprom-src = <&eeprom0>; qcom,actuator-src = <&actuator0>; cam_vana-supply = <&pm8953_l22>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi index 6e93d68567b6..2314fbd4bb67 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi @@ -15,6 +15,7 @@ qcom,cam-vreg-min-voltage = <2850000>; qcom,cam-vreg-max-voltage = <2850000>; qcom,cam-vreg-op-mode = <80000>; + status = "disabled"; }; actuator1: qcom,actuator@1 { @@ -27,6 +28,7 @@ qcom,cam-vreg-min-voltage = <2850000>; qcom,cam-vreg-max-voltage = <2850000>; qcom,cam-vreg-op-mode = <80000>; + status = "disabled"; }; eeprom0: qcom,eeprom@0 { @@ -60,7 +62,7 @@ qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_VANA"; - status = "ok"; + status = "disabled"; clocks = <&gcc MCLK0_CLK_SRC>, <&gcc GCC_CAMSS_MCLK0_CLK>; clock-names = "cam_src_clk", "cam_clk"; @@ -140,7 +142,7 @@ "sensor_cam_mclk"; qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>; qcom,cam-power-seq-delay = <1 1 1 30 30 5>; - status = "ok"; + status = "disabled"; clocks = <&gcc MCLK2_CLK_SRC>, <&gcc GCC_CAMSS_MCLK2_CLK>; clock-names = "cam_src_clk", "cam_clk"; @@ -177,7 +179,7 @@ qcom,gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2", "CAM_STANDBY2"; - status = "ok"; + status = "disabled"; clocks = <&gcc MCLK2_CLK_SRC>, <&gcc GCC_CAMSS_MCLK2_CLK>; clock-names = "cam_src_clk", "cam_clk"; @@ -191,7 +193,7 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; - qcom,led-flash-src = ; + qcom,led-flash-src = <&led_flash0>; qcom,eeprom-src = <&eeprom0>; qcom,actuator-src = <&actuator0>; cam_vana-supply = <&pm8953_l22>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi index 7883909d6632..77371e336e81 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi @@ -15,6 +15,7 @@ qcom,cam-vreg-min-voltage = <2850000>; qcom,cam-vreg-max-voltage = <2850000>; qcom,cam-vreg-op-mode = <80000>; + status = "disabled"; }; actuator1: qcom,actuator@1 { @@ -27,6 +28,7 @@ qcom,cam-vreg-min-voltage = <2850000>; qcom,cam-vreg-max-voltage = <2850000>; qcom,cam-vreg-op-mode = <80000>; + status = "disabled"; }; eeprom0: qcom,eeprom@0 { @@ -60,7 +62,7 @@ qcom,gpio-req-tbl-label = "CAMIF_MCLK0", "CAM_RESET0", "CAM_VANA"; - status = "ok"; + status = "disabled"; clocks = <&gcc MCLK0_CLK_SRC>, <&gcc GCC_CAMSS_MCLK0_CLK>; clock-names = "cam_src_clk", "cam_clk"; @@ -141,7 +143,7 @@ "sensor_cam_mclk"; qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>; qcom,cam-power-seq-delay = <1 1 1 30 30 5>; - status = "ok"; + status = "disabled"; clocks = <&gcc MCLK2_CLK_SRC>, <&gcc GCC_CAMSS_MCLK2_CLK>; clock-names = "cam_src_clk", "cam_clk"; @@ -155,7 +157,7 @@ qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; qcom,mount-angle = <90>; - qcom,led-flash-src = ; + qcom,led-flash-src = <&led_flash0>; qcom,eeprom-src = <&eeprom0>; qcom,actuator-src = <&actuator0>; cam_vana-supply = <&pm8953_l22>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi index 6b55c24388ab..1c1ac4013ee8 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi @@ -617,10 +617,24 @@ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; interrupt-parent = <&tlmm>; interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; + smb1355_charger: qcom,smb1355-charger@1000 { + status = "ok"; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + }; +}; + +&smb1355_0 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default + &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; smb1355_charger_0: qcom,smb1355-charger@1000 { - status ="ok"; - /delete-property/ io-channels; - /delete-property/ io-channels-names; + status = "ok"; qcom,parallel-mode = <1>; qcom,disable-ctm; qcom,hw-die-temp-mitigation; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi index ab4b1a6c76ae..f59965850079 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi @@ -2,6 +2,17 @@ &pmi632_charger { dpdm-supply = <&usb_otg>; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,thermal-mitigation + = <3000000 2500000 2000000 1500000 + 1000000 500000>; }; &usb_otg { @@ -14,6 +25,17 @@ qcom,ps-hold-shutdown-disable; }; +&soc { + led_flash0: qcom,camera-flash { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-type = <1>; + qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>; + qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>; + qcom,switch-source = <&pmi632_switch0>; + }; +}; + / { mtp_batterydata: qcom,battery-data { qcom,batt-id-range-pct = <15>; @@ -24,10 +46,9 @@ &pmi632_qg { qcom,battery-data = <&mtp_batterydata>; -}; - -&pmi632_charger { - qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; }; &pmi632_vadc { diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi index f2bdd8441cd1..ddcaeb339055 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi @@ -346,12 +346,6 @@ #include "smb1355.dtsi" }; -&pmi632_vadc { - chan@4a { - qcom,scale-function = <22>; - }; -}; - &pmi632_gpios { smb_en { smb_en_default: smb_en_default { @@ -402,10 +396,24 @@ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; interrupt-parent = <&tlmm>; interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; + smb1355_charger: qcom,smb1355-charger@1000 { + status = "ok"; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + }; +}; + +&smb1355_0 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default + &smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; smb1355_charger_0: qcom,smb1355-charger@1000 { - status ="ok"; - /delete-property/ io-channels; - /delete-property/ io-channels-names; + status = "ok"; qcom,parallel-mode = <1>; qcom,disable-ctm; qcom,hw-die-temp-mitigation; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi index bc5ac4c23e94..1d069cdb49ee 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi @@ -2,7 +2,7 @@ #include "sdm439-pm8953.dtsi" #include "sdm439-pmi632.dtsi" #include "sdm439-audio.dtsi" - +#include / { model = "Qualcomm Technologies, Inc. SDM439"; compatible = "qcom,sdm439"; @@ -65,8 +65,8 @@ < 1459200 >; }; - /delete-node/ generic-bw-opp-table; - generic_bw_opp_table: generic-bw-opp-table { + /delete-node/ ddr-bw-opp-table; + ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 101, 8); /* 769 MB/s */ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */ @@ -84,21 +84,21 @@ /delete-node/ qcom,cpu-cpu-ddr-bw; cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; - operating-points-v2 = <&generic_bw_opp_table>; + operating-points-v2 = <&ddr_bw_opp_table>; }; - /delete-node/ qcom,cpu0-cpu-ddr-latfloor; - cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + /delete-node/ qcom,cpu-cpu-ddr-latfloor; + cpu_cpu_ddr_latfloor: qcom,cpu-cpu-ddr-latfloor { compatible = "qcom,devbw"; - governor = "cpufreq"; + governor = "performance"; qcom,src-dst-ports = ; qcom,active-only; - operating-points-v2 = <&generic_bw_opp_table>; + operating-points-v2 = <&ddr_bw_opp_table>; }; /delete-node/ qcom,cci; @@ -108,7 +108,7 @@ /* TODO * clocks = <&clock_cpu clk_cci_clk>; */ - governor = "cpufreq"; + governor = "performance"; freq-tbl-khz = < 400000 >, < 400000 >, @@ -155,13 +155,13 @@ CPU_COST_0: core-cost0 { busy-cost-data = < - 800000 137 - 1305600 207 - 1497600 256 - 1708800 327 - 1804800 343 - 1958400 445 - 2016000 470 + 406 137 + 663 207 + 761 256 + 868 327 + 917 343 + 995 445 + 1024 470 >; idle-cost-data = < 100 80 60 40 @@ -170,11 +170,11 @@ CPU_COST_1: core-cost1 { busy-cost-data = < - 768000 43 - 998400 56 - 1171200 71 - 1305600 89 - 1459200 120 + 355 43 + 461 56 + 541 71 + 603 89 + 674 120 >; }; }; @@ -324,28 +324,15 @@ }; &gcc { - compatible = "qcom,gcc-sdm439"; - reg = <0x1800000 0x80000>, - <0xb016000 0x00040>, - <0xb116000 0x00040>, - <0x00a6018 0x00004>; - reg-names = "cc_base", "apcs_c1_base", - "apcs_c0_base", "efuse"; vdd_cx-supply = <&pm8953_s2_level>; - vdd_sr2_dig-supply = <&pm8953_s2_level_ao>; - vdd_sr2_pll-supply = <&pm8953_l7_ao>; - vdd_hf_dig-supply = <&pm8953_s2_level_ao>; - vdd_hf_pll-supply = <&pm8953_l7_ao>; }; &gcc_mdss { compatible = "qcom,gcc-mdss-sdm439"; - /* TODO - * clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, - * <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, - * <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, - * <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; - */ + clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>; clock-names = "pclk0_src", "byte0_src", "pclk1_src", "byte1_src"; #clock-cells = <1>; @@ -380,6 +367,19 @@ 0x1a96000 0x1a96000 0x300 0x1a96400 0x1a96400 0x400 0x193e000 0x193e000 0x30>; + + clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>, + <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>, + <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>, + <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>; + + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", + "ext_pixel1_clk"; + }; &mdss_dsi0 { @@ -404,20 +404,31 @@ /delete-property/ qcom,platform-lane-config; }; -/* GPU Overrides*/ -&gpubw { - /delete-property/qcom,bw-tbl; - qcom,bw-tbl = - < 0 >, /* off */ - < 769 >, /* 1. DDR:100.80 MHz BIMC: 50.40 MHz */ - < 1611 >, /* 2. DDR:211.20 MHz BIMC: 105.60 MHz */ - < 2273 >, /* 3. DDR:297.60 MHz BIMC: 148.80 MHz */ - < 2929 >, /* 4. DDR:384.00 MHz BIMC: 192.00 MHz */ - < 4248 >, /* 5. DDR:556.80 MHz BIMC: 278.40 MHz */ - < 5346 >, /* 6. DDR:662.40 MHz BIMC: 331.20 MHz */ - < 5712 >, /* 7. DDR:748.80 MHz BIMC: 374.40 MHz */ - < 6150 >, /* 8. DDR:796.80 MHz BIMC: 398.40 MHz */ - < 7105 >; /* 9. DDR:931.20 MHz BIMC: 465.60 MHz */ +/* GPU Overrides */ +&soc { + /delete-node/ gpu-bw-tbl; + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + + opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */ + + opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */ + + opp-298 { opp-hz = /bits/ 64 < 2273 >; }; /* 3. 298 MHz */ + + opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */ + + opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. 557 MHz */ + + opp-700 { opp-hz = /bits/ 64 < 5346 >; }; /* 6. 700 MHz */ + + opp-748 { opp-hz = /bits/ 64 < 5712 >; }; /* 7. 748 MHz */ + + opp-806 { opp-hz = /bits/ 64 < 6150 >; }; /* 8. 806 MHz */ + + opp-931 { opp-hz = /bits/ 64 < 7105 >; }; /* 9. 931 MHz */ + }; }; &msm_gpu { diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi index d6008ef195e7..e38f9351f239 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi @@ -494,6 +494,10 @@ snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; dr_mode = "host"; + linux,sysdev_is_parent; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + usb-core-id = <1>; }; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi index 931619fdb3f7..0389edcadb92 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi @@ -10,6 +10,9 @@ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; + + #list-cells = <1>; + vdd-supply = <&gdsc_mdss>; /* Bus Scale Settings */ @@ -580,6 +583,8 @@ reg-names = "mdp_phys", "rot_vbif_phys"; + #list-cells = <1>; + qcom,mdss-rot-mode = <1>; qcom,mdss-highest-bank-bit = <0x1>; @@ -607,6 +612,7 @@ interrupt-parent = <&mdss_mdp>; interrupts = <2 0>; + qcom,mdss-rot-parent = <&mdss_mdp 0>; /* VBIF QoS remapper settings*/ qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>; qcom,mdss-rot-xin-id = <14 15>; diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi index 00d9058c9ef1..6bcf1feb4955 100755 --- a/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi @@ -14,7 +14,6 @@ qcom,hfi = "venus"; qcom,hfi-version = "3xx"; qcom,firmware-name = "venus"; - qcom,never-unload-fw; qcom,sw-power-collapse; qcom,max-secure-instances = <5>; qcom,reg-presets = diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi index a75e19fc6607..f244a0dcf44f 100755 --- a/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi @@ -42,3 +42,46 @@ smb1355: qcom,smb1355@c { }; }; }; + +smb1355_0: qcom,smb1355@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1355_0"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + status = "disabled"; + + smb1355_revid_0: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb1355_charger_0: qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <&smb1355_revid_0>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb1355_0>; + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi new file mode 100755 index 000000000000..59b0bbfcc206 --- /dev/null +++ b/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi @@ -0,0 +1,34 @@ +#include +#include + +smb1394: qcom,smb1394@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x6 0x26 0x27>; + status = "disabled"; + + smb1394_div2_cp_primary: qcom,div2_cp_pry { + compatible = "qcom,smb1394-div2-cp-primary"; + #io-channel-cells = <1>; + interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>, + <0x26 0x3 IRQ_TYPE_EDGE_RISING>, + <0x26 0x5 IRQ_TYPE_EDGE_RISING>, + <0x26 0x7 IRQ_TYPE_EDGE_RISING>, + <0x27 0x5 IRQ_TYPE_EDGE_RISING>, + <0x27 0x6 IRQ_TYPE_EDGE_RISING>, + <0x27 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "temp-shdwn", + "div2-irev", + "usbin-uv", + "usbin-ov", + "div2-ilim", + "div2-win-uv", + "div2-win-ov"; + qcom,div2-cp-min-ilim-ua = <1000000>; + status = "disabled"; + }; +};