ARM64: dts: vendor: Update devicetree to LA.UM.9.12.r1-12000-SMxx50.0

Signed-off-by: UtsavBalar1231 <utsavbalar1231@gmail.com>

arch/arm64/boot/dts/vendor/.gitignore

@@ -0,0 +1,2 @@
+# Ignore camera directory
+qcom/camera

arch/arm64/boot/dts/vendor/bindings/arm/msm/msm.txt

@@ -59,6 +59,9 @@ SoCs:
 - BENGAL
   compatible = "qcom,bengal"
 
+- KHAJE
+  compatible = "qcom,khaje"
+
 - SCUBA
   compatible = "qcom,scuba"
 
@@ -247,6 +250,8 @@ compatible = "qcom,bengal-qrd"
 compatible = "qcom,bengal-idp"
 compatible = "qcom,bengalp"
 compatible = "qcom,bengalp-idp"
+compatible = "qcom,khaje-idp"
+compatible = "qcom,khaje-qrd"
 compatible = "qcom,scuba-rumi"
 compatible = "qcom,scuba-idp"
 compatible = "qcom,scuba-qrd"

arch/arm64/boot/dts/vendor/bindings/bt-fm/fm.txt

@@ -0,0 +1,29 @@
+Qti radio iris device
+
+-FM RX playback with no RDS
+
+   FM samples is filtered by external RF chips at baseband, then send to Riva-FM core through serial link.
+   FM signal is demodulated then audio L/R samples are stored inside memory.
+   FM Rx received samples data is connected to external audio codec.
+
+-Audio playback to FM TX
+
+  Used to play audio source  to FM TX.
+  FM TX module will read the audio samples from memory then modulated samples will be send through serial interface to external RF chip.
+
+-RX playback with RDS
+
+  FM Rx receive audio data along with RDS.
+
+-FM TX with RDS
+
+  Used to send RDS messages to external FM receiver.
+
+Required Properties:
+- compatible: "qcom,iris_fm"
+
+Example:
+        qcom,iris-fm {
+                compatible = "qcom,iris_fm";
+        };
+

arch/arm64/boot/dts/vendor/bindings/clock/qcom,debugcc.txt

@@ -6,7 +6,8 @@ Required properties :
 		"qcom,bengal-debugcc", "qcom,lagoon-debugcc"
 		"qcom,sdm660-debugcc" "qcom,sdm429w-debugcc"
 		"qcom,msm8937-debugcc" "qcom,msm8917-debugcc"
-		"qcom,sdm429w-debugcc "or "qcom,qm215-debugcc".
+		"qcom,sdm429w-debugcc", "qcom,qm215-debugcc"
+		or "qcom,sdm450-debugcc", "qcom,khaje-debugcc".
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
 - qcom,camcc: phandle to the Camera CC device node.

arch/arm64/boot/dts/vendor/bindings/clock/qcom,dispcc.txt

@@ -9,7 +9,8 @@ Required properties :
 		"qcom,lito-dispcc"
 		"qcom,bengal-dispcc"
 		"qcom,lagoon-dispcc"
-		"qcom,scuba-dispcc".
+		"qcom,scuba-dispcc"
+		"qcom,khaje-dispcc".
 - reg : shall contain base register location and length.
 - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf
 of the clocks.

arch/arm64/boot/dts/vendor/bindings/clock/qcom,gcc.txt

@@ -31,12 +31,12 @@ Required properties :
 			"qcom,gcc-msm8917"
 			"qcom,gcc-msm8937"
 			"qcom,gcc-sdm429w"
+			"qcom,gcc-sdm450"
 			"qcom,gcc-mdss-msm8937"
-			"qcom,gcc-mdss-8917"
+			"qcom,gcc-mdss-qm215"
 			"qcom,gcc-mdss-sdm429w"
-			"qcom,gcc-mdss-sdm429"
 			"qcom,gcc-mdss-sdm439"
-			"qcom,gcc-mdss-sdm429w"
+			"qcom,khaje-gcc"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1

arch/arm64/boot/dts/vendor/bindings/clock/qcom,gpucc.txt

@@ -9,7 +9,8 @@ Required properties :
 		"qcom,lagoon-gpucc",
 		"qcom,gpu-sdm660",
 		"qcom,gpucc-sdm660",
-		"qcom,gpucc-sdm630".
+		"qcom,gpucc-sdm630",
+		"qcom,khaje-gpucc".
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.

arch/arm64/boot/dts/vendor/bindings/clock/qcom,rpmcc.txt

@@ -18,9 +18,9 @@ Required properties :
 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
 			"qcom,rpmcc-bengal", "qcom,rpmcc"
 			"qcom,rpmcc-sdm660", "qcom,rpmcc"
-			"qcom,rpmcc-msm8937", "qcom,rpmcc"
-			"qcom,rpmcc-msm8917", "qcom,rpmcc"
+			"qcom,rpmcc-sdm439", "qcom,rpmcc"
 			"qcom,rpmcc-qm215", "qcom,rpmcc"
+			"qcom,rpmcc-sdm450", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 

arch/arm64/boot/dts/vendor/bindings/clock/qcom,sdm-cpucc.txt

@@ -0,0 +1,96 @@
+Qualcomm Technologies, Inc. SDM CPU clock driver
+---------------------------------------------------
+
+It is the clock controller driver which provides higher frequency
+clocks and allows CPU frequency scaling on sdm based platforms.
+
+Required properties:
+- compatible:	Shall contain following:
+		"qcom,cpu-clock-sdm", "qcom,cpu-clock-qm215",
+		"qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429"
+- clocks:	Phandle to the clock device.
+- clock-names:	Names of the used clocks. Shall contain following:
+		"xo_ao", "gpll0_ao"
+- reg:	Shall contain base register offset and size.
+- reg-names:	Names of the bases for the above registers. Shall contain following:
+		"apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"
+- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.
+- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.
+- cpu-vdd-supply:	The regulator powering the APSS C1 RCG and APSS CCI RCG.
+- qcom,speedX-bin-vY-Z:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
+			Format: <freq uV>
+			This represents the max frequency possible for each possible
+			power configuration for a CPU that's binned as speed bin X,
+			speed bin revision Y. Version can be between [0-3]. Z
+			is the mux id c1 or cci.
+- #clock-cells:	Shall contain 1.
+
+Example:
+	clock_cpu: qcom,clock-cpu@0b011050 {
+		compatible = "qcom,cpu-clock-sdm";
+		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+			<&gcc GPLL0_AO_OUT_MAIN>;
+		clock-names = "xo_ao", "gpll0_ao" ;
+		reg =   <0xb011050 0x8>,
+			<0xb1d1050 0x8>,
+			<0xb016000 0x34>,
+			<0x00a412c 0x8>;
+		reg-names = "apcs-c1-rcg-base",
+			"apcs-cci-rcg-base", "apcs_pll", "efuse";
+		cpu-vdd-supply = <&apc_vreg_corner>;
+		vdd_dig_ao-supply = <&L12A_AO;
+		vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;
+		qcom,speed0-bin-v0-c1 =
+			<          0 0>,
+			<  960000000 1>,
+			< 1305600000 1>,
+			< 1497600000 2>,
+			< 1708800000 3>,
+			< 1958400000 5>;
+
+		qcom,speed0-bin-v0-cci =
+			<          0 0>,
+			<  400000000 1>,
+			<  533333333 3>;
+
+		qcom,speed1-bin-v0-c1 =
+			<          0 0>,
+			<  960000000 1>,
+			< 1305600000 1>,
+			< 1497600000 2>,
+			< 1708800000 3>,
+			< 1804800000 5>;
+
+		qcom,speed1-bin-v0-cci =
+			<          0 0>,
+			<  400000000 1>,
+			<  533333333 3>;
+
+		qcom,speed4-bin-v0-c1 =
+			<          0 0>,
+			<  960000000 1>,
+			< 1305600000 1>,
+			< 1497600000 2>,
+			< 1708800000 3>,
+			< 1958400000 5>,
+			< 2016000000 6>;
+
+		qcom,speed4-bin-v0-cci =
+			<          0 0>,
+			<  400000000 1>,
+			<  533333333 3>;
+
+		qcom,speed5-bin-v0-c1 =
+			<          0 0>,
+			<  960000000 1>,
+			< 1305600000 1>,
+			< 1497600000 2>,
+			< 1708800000 3>;
+
+		qcom,speed5-bin-v0-cci =
+			<          0 0>,
+			<  400000000 1>,
+			<  533333333 3>;
+
+		#clock-cells = <1>;
+	};

arch/arm64/boot/dts/vendor/bindings/cnss/cnss-wlan.txt

@@ -82,6 +82,7 @@ Optional properties:
   - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO
                    enable to resolve PMU power up issues. Provide BT GPIO using
                    this config param.
+  - qcom,sw-ctrl-gpio: Switch control GPIO for device power control
 
 Example: