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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/projects/tt_um_mattvenn_double_inverter/commit_id.json b/projects/tt_um_mattvenn_double_inverter/commit_id.json new file mode 100644 index 0000000..4d37a54 --- /dev/null +++ b/projects/tt_um_mattvenn_double_inverter/commit_id.json @@ -0,0 +1,8 @@ +{ + "app": "custom_gds action", + "repo": "https://github.com/mattvenn/tt09-analog-double-inverter", + "commit": "1d0833dd1355f46c3dc192f3e39e7e7694615d10", + "workflow_url": "https://github.com/mattvenn/tt09-analog-double-inverter/actions/runs/11105297810", + "sort_id": 1727687830514, + "analog": true +} \ No newline at end of file diff --git a/projects/tt_um_mattvenn_double_inverter/docs/info.md b/projects/tt_um_mattvenn_double_inverter/docs/info.md new file mode 100644 index 0000000..309fd96 --- /dev/null +++ b/projects/tt_um_mattvenn_double_inverter/docs/info.md @@ -0,0 +1,22 @@ + + +## How it works + +A pair of inverters, a large one after a small one. + +## How to test + +Put a signal into the input pin, and observe the output. It should match polarity. + +The rise time of the output was simulated at less than 4ns. + +## External hardware + +Signal generator, oscilloscope. diff --git a/projects/tt_um_mattvenn_double_inverter/info.yaml b/projects/tt_um_mattvenn_double_inverter/info.yaml new file mode 100644 index 0000000..569c792 --- /dev/null +++ b/projects/tt_um_mattvenn_double_inverter/info.yaml @@ -0,0 +1,65 @@ +# Tiny Tapeout project information +project: + title: "Analog double inverter" # Project title + author: "Matt Venn" # Your name + discord: "mattvenn" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) + description: "A pair of inverters wired between 2 analog pins" # One line description of what your project does + language: "Analog" # other examples include Verilog, Amaranth, VHDL, etc + clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) + + # How many tiles your design occupies? A single tile is about 167x108 uM. + tiles: "1x2" # Valid values for analog projects: 1x2, 2x2 + + # How many analog pins does your project use? + analog_pins: 2 # Valid values: 0 to 6 + uses_3v3: false # Set to true if your project uses 3.3V (VAPWR) in addition to 1.8V (VDPWR) + + # Your top module name must start with "tt_um_". Make it unique by including your github username: + top_module: "tt_um_mattvenn_double_inverter" + + # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: + source_files: + - "project.v" + +# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. +pinout: + # Inputs + ui[0]: "" + ui[1]: "" + ui[2]: "" + ui[3]: "" + ui[4]: "" + ui[5]: "" + ui[6]: "" + ui[7]: "" + + # Outputs + uo[0]: "" + uo[1]: "" + uo[2]: "" + uo[3]: "" + uo[4]: "" + uo[5]: "" + uo[6]: "" + uo[7]: "" + + # Bidirectional pins + uio[0]: "" + uio[1]: "" + uio[2]: "" + uio[3]: "" + uio[4]: "" + uio[5]: "" + uio[6]: "" + uio[7]: "" + + # Analog pins - make sure to also set "analog_pins" above, else the pins won't be connected + ua[0]: "output" + ua[1]: "input" + ua[2]: "" + ua[3]: "" + ua[4]: "" + ua[5]: "" + +# Do not change! +yaml_version: 6 diff --git a/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.gds b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.gds new file mode 100644 index 0000000..27effc4 Binary files /dev/null and b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.gds differ diff --git a/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.lef b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.lef new file mode 100644 index 0000000..30e439e --- /dev/null +++ b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.lef @@ -0,0 +1,526 @@ +MACRO tt_um_mattvenn_double_inverter + CLASS BLOCK ; + FOREIGN tt_um_mattvenn_double_inverter ; + ORIGIN 0.000 0.000 ; + SIZE 161.000 BY 225.760 ; + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 143.830 224.760 144.130 225.760 ; + END + END clk + PIN ena + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 146.590 224.760 146.890 225.760 ; + END + END ena + PIN rst_n + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 141.070 224.760 141.370 225.760 ; + END + END rst_n + PIN ua[0] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNADIFFAREA 6.890000 ; + PORT + LAYER met4 ; + RECT 151.810 0.000 152.710 1.000 ; + END + END ua[0] + PIN ua[1] + DIRECTION INOUT ; + USE SIGNAL ; + ANTENNAGATEAREA 0.300000 ; + PORT + LAYER met4 ; + RECT 132.490 0.000 133.390 1.000 ; + END + END ua[1] + PIN ua[2] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 113.170 0.000 114.070 1.000 ; + END + END ua[2] + PIN ua[3] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 93.850 0.000 94.750 1.000 ; + END + END ua[3] + PIN ua[4] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 74.530 0.000 75.430 1.000 ; + END + END ua[4] + PIN ua[5] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 55.210 0.000 56.110 1.000 ; + END + END ua[5] + PIN ua[6] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 35.890 0.000 36.790 1.000 ; + END + END ua[6] + PIN ua[7] + DIRECTION INOUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 16.570 0.000 17.470 1.000 ; + END + END ua[7] + PIN ui_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 138.310 224.760 138.610 225.760 ; + END + END ui_in[0] + PIN ui_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 135.550 224.760 135.850 225.760 ; + END + END ui_in[1] + PIN ui_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 132.790 224.760 133.090 225.760 ; + END + END ui_in[2] + PIN ui_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 130.030 224.760 130.330 225.760 ; + END + END ui_in[3] + PIN ui_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 127.270 224.760 127.570 225.760 ; + END + END ui_in[4] + PIN ui_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 124.510 224.760 124.810 225.760 ; + END + END ui_in[5] + PIN ui_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 121.750 224.760 122.050 225.760 ; + END + END ui_in[6] + PIN ui_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 118.990 224.760 119.290 225.760 ; + END + END ui_in[7] + PIN uio_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 116.230 224.760 116.530 225.760 ; + END + END uio_in[0] + PIN uio_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 113.470 224.760 113.770 225.760 ; + END + END uio_in[1] + PIN uio_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 110.710 224.760 111.010 225.760 ; + END + END uio_in[2] + PIN uio_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 107.950 224.760 108.250 225.760 ; + END + END uio_in[3] + PIN uio_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 105.190 224.760 105.490 225.760 ; + END + END uio_in[4] + PIN uio_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 102.430 224.760 102.730 225.760 ; + END + END uio_in[5] + PIN uio_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 99.670 224.760 99.970 225.760 ; + END + END uio_in[6] + PIN uio_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met4 ; + RECT 96.910 224.760 97.210 225.760 ; + END + END uio_in[7] + PIN uio_oe[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 49.990 224.760 50.290 225.760 ; + END + END uio_oe[0] + PIN uio_oe[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 47.230 224.760 47.530 225.760 ; + END + END uio_oe[1] + PIN uio_oe[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 44.470 224.760 44.770 225.760 ; + END + END uio_oe[2] + PIN uio_oe[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 41.710 224.760 42.010 225.760 ; + END + END uio_oe[3] + PIN uio_oe[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 38.950 224.760 39.250 225.760 ; + END + END uio_oe[4] + PIN uio_oe[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 36.190 224.760 36.490 225.760 ; + END + END uio_oe[5] + PIN uio_oe[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 33.430 224.760 33.730 225.760 ; + END + END uio_oe[6] + PIN uio_oe[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 30.670 224.760 30.970 225.760 ; + END + END uio_oe[7] + PIN uio_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 72.070 224.760 72.370 225.760 ; + END + END uio_out[0] + PIN uio_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 69.310 224.760 69.610 225.760 ; + END + END uio_out[1] + PIN uio_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 66.550 224.760 66.850 225.760 ; + END + END uio_out[2] + PIN uio_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 63.790 224.760 64.090 225.760 ; + END + END uio_out[3] + PIN uio_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 61.030 224.760 61.330 225.760 ; + END + END uio_out[4] + PIN uio_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 58.270 224.760 58.570 225.760 ; + END + END uio_out[5] + PIN uio_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 55.510 224.760 55.810 225.760 ; + END + END uio_out[6] + PIN uio_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 52.750 224.760 53.050 225.760 ; + END + END uio_out[7] + PIN uo_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 94.150 224.760 94.450 225.760 ; + END + END uo_out[0] + PIN uo_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 91.390 224.760 91.690 225.760 ; + END + END uo_out[1] + PIN uo_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 88.630 224.760 88.930 225.760 ; + END + END uo_out[2] + PIN uo_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 85.870 224.760 86.170 225.760 ; + END + END uo_out[3] + PIN uo_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 83.110 224.760 83.410 225.760 ; + END + END uo_out[4] + PIN uo_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 80.350 224.760 80.650 225.760 ; + END + END uo_out[5] + PIN uo_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 77.590 224.760 77.890 225.760 ; + END + END uo_out[6] + PIN uo_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + ANTENNADIFFAREA 9.421000 ; + PORT + LAYER met4 ; + RECT 74.830 224.760 75.130 225.760 ; + END + END uo_out[7] + PIN VDPWR + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 1.000 5.000 3.000 220.760 ; + END + END VDPWR + PIN VGND + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 4.000 5.000 6.000 220.760 ; + END + END VGND + OBS + LAYER nwell ; + RECT 134.820 10.170 149.590 17.860 ; + LAYER li1 ; + RECT 135.000 10.320 149.410 17.720 ; + LAYER met1 ; + RECT 122.330 7.910 152.740 19.970 ; + LAYER met2 ; + RECT 120.490 7.920 152.730 19.460 ; + LAYER met3 ; + RECT 1.000 4.460 152.735 19.465 ; + LAYER met4 ; + RECT 6.000 224.360 30.270 224.760 ; + RECT 31.370 224.360 33.030 224.760 ; + RECT 34.130 224.360 35.790 224.760 ; + RECT 36.890 224.360 38.550 224.760 ; + RECT 39.650 224.360 41.310 224.760 ; + RECT 42.410 224.360 44.070 224.760 ; + RECT 45.170 224.360 46.830 224.760 ; + RECT 47.930 224.360 49.590 224.760 ; + RECT 50.690 224.360 52.350 224.760 ; + RECT 53.450 224.360 55.110 224.760 ; + RECT 56.210 224.360 57.870 224.760 ; + RECT 58.970 224.360 60.630 224.760 ; + RECT 61.730 224.360 63.390 224.760 ; + RECT 64.490 224.360 66.150 224.760 ; + RECT 67.250 224.360 68.910 224.760 ; + RECT 70.010 224.360 71.670 224.760 ; + RECT 72.770 224.360 74.430 224.760 ; + RECT 75.530 224.360 77.190 224.760 ; + RECT 78.290 224.360 79.950 224.760 ; + RECT 81.050 224.360 82.710 224.760 ; + RECT 83.810 224.360 85.470 224.760 ; + RECT 86.570 224.360 88.230 224.760 ; + RECT 89.330 224.360 90.990 224.760 ; + RECT 92.090 224.360 93.750 224.760 ; + RECT 94.850 224.360 96.510 224.760 ; + RECT 97.610 224.360 99.270 224.760 ; + RECT 100.370 224.360 102.030 224.760 ; + RECT 103.130 224.360 104.790 224.760 ; + RECT 105.890 224.360 107.550 224.760 ; + RECT 108.650 224.360 110.310 224.760 ; + RECT 111.410 224.360 113.070 224.760 ; + RECT 114.170 224.360 115.830 224.760 ; + RECT 116.930 224.360 118.590 224.760 ; + RECT 119.690 224.360 121.350 224.760 ; + RECT 122.450 224.360 124.110 224.760 ; + RECT 125.210 224.360 126.870 224.760 ; + RECT 127.970 224.360 129.630 224.760 ; + RECT 130.730 224.360 132.390 224.760 ; + RECT 133.490 224.360 135.150 224.760 ; + RECT 136.250 224.360 137.910 224.760 ; + RECT 139.010 224.360 140.670 224.760 ; + RECT 141.770 224.360 143.430 224.760 ; + RECT 144.530 224.360 146.190 224.760 ; + RECT 147.290 224.360 152.710 224.760 ; + RECT 6.000 221.160 152.710 224.360 ; + RECT 6.400 4.600 152.710 221.160 ; + RECT 6.000 1.400 152.710 4.600 ; + RECT 6.000 1.000 16.170 1.400 ; + RECT 17.870 1.000 35.490 1.400 ; + RECT 37.190 1.000 54.810 1.400 ; + RECT 56.510 1.000 74.130 1.400 ; + RECT 75.830 1.000 93.450 1.400 ; + RECT 95.150 1.000 112.770 1.400 ; + RECT 114.470 1.000 132.090 1.400 ; + RECT 133.790 1.000 151.410 1.400 ; + END +END tt_um_mattvenn_double_inverter +END LIBRARY + diff --git a/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.v b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.v new file mode 100644 index 0000000..0ba9a7e --- /dev/null +++ b/projects/tt_um_mattvenn_double_inverter/tt_um_mattvenn_double_inverter.v @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Your Name + * SPDX-License-Identifier: Apache-2.0 + */ + +`default_nettype none + +module tt_um_mattvenn_double_inverter ( + input wire VGND, + input wire VDPWR, // 1.8v power supply +// input wire VAPWR, // 3.3v power supply + input wire [7:0] ui_in, // Dedicated inputs + output wire [7:0] uo_out, // Dedicated outputs + input wire [7:0] uio_in, // IOs: Input path + output wire [7:0] uio_out, // IOs: Output path + output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) + inout wire [7:0] ua, // Analog pins, only ua[5:0] can be used + input wire ena, // always 1 when the design is powered, so you can ignore it + input wire clk, // clock + input wire rst_n // reset_n - low to reset +); + + double_inverter double_inverter( + .VDD(VDPWR), + .VSS(VGND), + .INPUT(ua[1]), + .OUTPUT(ua[0]) + ); + + assign uo_out[0] = VGND; + assign uo_out[1] = VGND; + assign uo_out[2] = VGND; + assign uo_out[3] = VGND; + assign uo_out[4] = VGND; + assign uo_out[5] = VGND; + assign uo_out[6] = VGND; + assign uo_out[7] = VGND; + + assign uio_out[0] = VGND; + assign uio_out[1] = VGND; + assign uio_out[2] = VGND; + assign uio_out[3] = VGND; + assign uio_out[4] = VGND; + assign uio_out[5] = VGND; + assign uio_out[6] = VGND; + assign uio_out[7] = VGND; + + assign uio_oe[0] = VGND; + assign uio_oe[1] = VGND; + assign uio_oe[2] = VGND; + assign uio_oe[3] = VGND; + assign uio_oe[4] = VGND; + assign uio_oe[5] = VGND; + assign uio_oe[6] = VGND; + assign uio_oe[7] = VGND; + +endmodule