Colorize modules in GUI

[olofk]

Just got the OpenROAD gui running natively on my machine and built the award-winning SERV, the world's smallest RISC-V CPU, with the tools.

One thing I always wanted to do is to colorize the cells according to the verilog module they came from so that I can get a visual of how much space each part of the design takes up. Is this possible to do with the GUI?

[maliberty]

You'll want the Hierarchy Browser:

As you expand the hierarchy it will color the layout. A simple example with gcd:

[maliberty]

The goal is to flatten modules below a certain size and keep those above that size. To know what the size is you have to first synthesize the modules to find out. Hierarchy boundaries impede optimization so this tries to find a good tradeoff. The code itself is ugly and its expensive to run yosys twice. This could be improved by using some other metric than final gate count that is a reasonable proxy for it and available earlier.

If you just want to keep everything it is much simpler to just avoid -flatten.

[olofk]

I see your point about multiple synthesis runs. I might make a stab at modularizing the code slightly now that I know the background. For my particular case, I think avoiding -flatten is good enough.

All in all, my original question was answered and I'm looking forward to try it out once I've gotten myself a hierarchical netlist. Thank you for the support.

[maliberty]

@gadfort had some suggestions on how to improve this. If you have time to explore I think he could provide a pointer.

[olofk]

Will do. Thanks. And just to finish this topic, here's a picture of the SERV-based Subservient SoC, the world's smallest RISC-V SoC with all its 1006 cells, of which the CPU itself apparently uses 523 :)

[gadfort]

@olofk @maliberty this is what I have mocked up to help avoid over flattening in yosys: https://github.com/siliconcompiler/siliconcompiler/blob/ca2858c82cda4861217f1b618a399f10502fb393/siliconcompiler/tools/yosys/syn_asic.tcl