diff --git a/Makefile b/Makefile
index 499dd33..6f235b4 100644
--- a/Makefile
+++ b/Makefile
@@ -4,7 +4,7 @@ ifeq ($(BOARD),)
 all: zip
 
 zip: build
-	find out/ -name "*.ihx" -print | zip out/stm8ef-bin docs/words.md -@
+	find out/ -name "*.ihx" -print | zip -r out/stm8ef-bin docs/words.md lib/* -@
 
 build: words
 	make BOARD=CORE
diff --git a/lib/hw/opt.fs b/lib/hw/opt.fs
new file mode 100644
index 0000000..5c568e8
--- /dev/null
+++ b/lib/hw/opt.fs
@@ -0,0 +1,13 @@
+\ STM8S option setting words
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef
+
+\ store char to (a), and inverted value to (a+1)
+: CN! ( c a -- )
+  2DUP C! SWAP NOT SWAP 1+ C!
+;
+
+\ unlock write protection, store option byte
+: OPT! ( c a -- )
+  FLASH_CR2 DUP C@ $80 OR SWAP CN!
+  ULOCK CN! LOCK
+;
diff --git a/lib/hw/pwm.fs b/lib/hw/pwm.fs
new file mode 100644
index 0000000..37323d3
--- /dev/null
+++ b/lib/hw/pwm.fs
@@ -0,0 +1,45 @@
+
+\ Init Timer1 with prescaler ( n=15 -> 1 MHz), CC PWM1..PWM3
+: T1PwmInit ( n -- )
+  TIM1_PSCRH 2C!
+  $80 TIM1_BKR C!
+  $60 TIM1_CCMR1 C!
+  $60 TIM1_CCMR2 C!
+  $60 TIM1_CCMR3 C!
+  $11 TIM1_CCER1 C!
+  $01 TIM1_CCER2 C!
+  1   TIM1_CR1 C!
+;
+
+\ Set Timer1 reload value
+: T1Reload ( n -- )
+  TIM1_ARRH 2C!
+;
+
+\ Set PWM1 compare value
+: PWM1 ( n -- )
+  TIM1_CCR1H 2C!
+;
+
+\ Set PWM2 compare value
+: PWM2 ( n -- )
+  TIM1_CCR2H 2C!
+;
+
+\ Set PWM3 compare value
+: PWM3 ( n -- )
+  TIM1_CCR3H 2C!
+;
+
+\ convert duty cycle [1/1000] to PWM reload value
+: duty ( n -- n )
+  TIM1_ARRH 2C@ 1000 */ 
+;
+
+\ Example:
+\   15  initTIM1
+\   1000 relTIM1
+\   800 pwm1
+\   500 pwm2
+\   200 pwm3
+
diff --git a/lib/math/isqrt.fs b/lib/math/isqrt.fs
new file mode 100644
index 0000000..7676c16
--- /dev/null
+++ b/lib/math/isqrt.fs
@@ -0,0 +1,21 @@
+\ Some integer square root (C) RigTig 2017
+\ github.com/TG9541/stm8ef/blob/master/LICENSE.md
+
+\ require: math/double.fs
+
+: isqrt ( d -- n )
+  $8000 ( d c ) $8000 ( d c g )
+  BEGIN
+    DUP DUP UM* ( d c g g^2)
+    6 PICK 6 PICK ( d c g g^2 d )
+    d> IF ( d c g )
+      OVER XOR
+    THEN ( d c g )
+    SWAP 2/ $7FFF AND ( d g c )
+    DUP 0= IF
+      DROP ROT ROT 2DROP -1 ( g true )
+    ELSE
+      SWAP OVER ( d c g c ) OR 0
+    THEN
+  UNTIL
+;
diff --git a/lib/math/srl.fs b/lib/math/srl.fs
new file mode 100644
index 0000000..c21284c
--- /dev/null
+++ b/lib/math/srl.fs
@@ -0,0 +1,7 @@
+\ STM8S: Shift Right Logical
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef
+
+\ SRL: shift right logical (unsigned divide by 2)
+: SRL ( n -- n )
+  \ LDW Y,X , LDW X,(X) , SRLW X , EXGW X,Y , LDW (X),Y
+  [ $9093 , $FE C, $54 C, $51 C, $FF C, ] ;
diff --git a/lib/regs/awu.fs b/lib/regs/awu.fs
new file mode 100644
index 0000000..96a5819
--- /dev/null
+++ b/lib/regs/awu.fs
@@ -0,0 +1,12 @@
+\ STM8S103 AWU register words
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef/
+
+\ AWU control/status register 1         (0x00)
+: AWU_CSR1   $50F0 [COMPILE] LITERAL ; IMMEDIATE
+
+\ AWU asynchronous prescaler buffer register (0x3F)
+: AWU_APR    $50F1 [COMPILE] LITERAL ; IMMEDIATE
+
+\ AWU timebase selection register       (0x00)
+: AWU_TBR    $50F2 [COMPILE] LITERAL ; IMMEDIATE
+
diff --git a/lib/regs/opt.fs b/lib/regs/opt.fs
new file mode 100644
index 0000000..7e16acd
--- /dev/null
+++ b/lib/regs/opt.fs
@@ -0,0 +1,12 @@
+\ STM8S option register words
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef
+
+: OPT0 $4800 [COMPILE] LITERAL ; IMMEDIATE
+: OPT1 $4801 [COMPILE] LITERAL ; IMMEDIATE
+: OPT2 $4803 [COMPILE] LITERAL ; IMMEDIATE
+: OPT3 $4805 [COMPILE] LITERAL ; IMMEDIATE
+: OPT4 $4807 [COMPILE] LITERAL ; IMMEDIATE
+: OPT5 $4809 [COMPILE] LITERAL ; IMMEDIATE
+
+: FLASH_CR2 $505B [COMPILE] LITERAL ; IMMEDIATE
+
diff --git a/lib/regs/timer1.fs b/lib/regs/timer1.fs
new file mode 100644
index 0000000..9a7a818
--- /dev/null
+++ b/lib/regs/timer1.fs
@@ -0,0 +1,16 @@
+\ STM8S103 Timer1 register words
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef/
+
+: TIM1_CR1   $5250 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCMR1 $5258 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCMR2 $5259 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCMR3 $525A [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCER1 $525C [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCER2 $525D [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_PSCRH $5260 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_ARRH  $5262 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCR1H $5265 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCR2H $5267 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_CCR3H $5269 [COMPILE] LITERAL ; IMMEDIATE
+: TIM1_BKR   $526D [COMPILE] LITERAL ; IMMEDIATE
+
diff --git a/lib/utils/ivec.fs b/lib/utils/ivec.fs
new file mode 100644
index 0000000..c923cbf
--- /dev/null
+++ b/lib/utils/ivec.fs
@@ -0,0 +1,9 @@
+\ Patch STM8 interrupt vector n to handler a
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef/
+ 
+\ Interrupt handler a should use SAVEC, IRET, and little stack
+\ github.com/TG9541/stm8ef/wiki/STM8S-eForth-Interrupts
+: IVEC  ( a n -- )  
+  2* 2* $800A + !
+;
+
diff --git a/lib/utils/persist.fs b/lib/utils/persist.fs
new file mode 100644
index 0000000..6ff7c2f
--- /dev/null
+++ b/lib/utils/persist.fs
@@ -0,0 +1,10 @@
+\ STM8EF dictionary management
+\ Manage NVM reset 
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef/
+
+\ Set RESET defaults to include newly defined NVM words  
+: PERSIST ( -- )
+  ULOCKF 
+  'BOOT DUP $12 DUP ROT + SWAP CMOVE
+  LOCKF
+;
diff --git a/lib/utils/rammark.fs b/lib/utils/rammark.fs
new file mode 100644
index 0000000..651b83b
--- /dev/null
+++ b/lib/utils/rammark.fs
@@ -0,0 +1,13 @@
+\ STM8EF temporary RAM dictionary
+\ (c) TG9541, refer to licence at github.com/TG9541/stm8ef/
+
+\ Mark current CP, LAST and CONTEXT in RAM mode
+: RAMmark ( -- a a a )
+  RAM last 2- @ last @  last 10 + @
+;
+
+\ Restore marked CP, LAST and CONTEXT in RAM mode
+: RAMdrop ( a a a -- )
+  RAM last 10 + ! last ! last 2- !
+;
+