Merge branch 'master' into dual-uart

TG9541 · Jan 19, 2018 · 25496a0 · 25496a0
2 parents c18641f + 4d46d6d
commit 25496a0
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Showing 3 changed files with 83 additions and 4 deletions.
diff --git a/mcu/STM8L051.efr b/mcu/STM8L051.efr
@@ -1,3 +1,58 @@
+\ STM8L051 Register ans Bit Identifiers
+
+\ Bitmasks (probably names should be changed to BMx ?)
+  01 equ BIT0
+  02 equ BIT1
+  04 equ BIT2
+  08 equ BIT3
+  10 equ BIT4
+  20 equ BIT5
+  40 equ BIT6
+  80 equ BIT7
+ 100 equ BIT8
+ 200 equ BIT9
+ 400 equ BIT10
+ 800 equ BIT11
+1000 equ BIT12
+2000 equ BIT13
+4000 equ BIT14
+8000 equ BIT15
+
+8002 equ RESET_VECTOR
+8006 equ TRAP_VETCOR
+                         \ Interrupt vectors (16 bit part)            
+800A equ INT_TLI         \ 0 External top level interrupt
+800E equ INT_FLASH       \ 1 Flash EOP/WR_PG_DIS
+8012 equ INT_DMA1_01     \ 2
+8016 equ INT_DMA1_23     \ 3
+801A equ INT_RTC         \ 4
+801E equ INT_PVD         \ 5
+8022 equ INT_EXTIB       \ 6
+8026 equ INT_EXTID       \ 7
+802A equ INT_EXTI0       \ 8
+802E equ INT_EXTI1       \ 9
+8032 equ INT_EXTI2       \ 10
+8036 equ INT_EXTI3       \ 11
+803A equ INT_EXTI4       \ 12
+803E equ INT_EXTI5       \ 13
+8042 equ INT_EXTI6       \ 14
+8046 equ INT_EXTI7       \ 15
+\ 804A                   \ 16
+804E equ INT_CLK         \ 17
+8052 equ INT_ADC1        \ 18
+8056 equ INT_TIM2        \ 19
+805A equ INT_TIM2CC      \ 20
+805E equ INT_TIM3        \ 21
+8062 equ INT_TIM3CC      \ 22
+8066 equ INT_RI          \ 23
+\ 806A                   \ 24
+806E equ INT_TIM4        \ 25
+8072 equ INT_SPI1        \ 26
+8076 equ INT_UARTTX      \ 27 USART1_TXD
+807A equ INT_UARTRX      \ 28 USART1_RXD
+807E equ INT_I2C         \ 29
+
+
 \ Port A
 5000 equ PA_ODR \ Port A data output latch register (0x00)
 5001 equ PA_IDR \ Port A in put pin value register (0xXX)

diff --git a/mcu/STM8S103.efr b/mcu/STM8S103.efr
@@ -18,6 +18,8 @@
 4000 equ BIT14
 8000 equ BIT15
 
+8002 equ RESET_VECTOR
+8006 equ TRAP_VETCOR
                      \ Interrupt vectors (16 bit part)
 800A equ INT_TLI     \ External top level interrupt
 800E equ INT_AWU     \ Auto wake up from halt
@@ -27,17 +29,28 @@
 801E equ INT_EXTI2   \ Port C external interrupts
 8022 equ INT_EXTI3   \ Port D external interrupts
 8026 equ INT_EXTI4   \ Port E external interrupts
+\ 802A
+\ 802E
 8032 equ INT_SPI     \ End of transfer
 8036 equ INT_TIM1    \ TIM1 update/overflow/underflow/ trigger/break
 803A equ INT_TIM1CC  \ TIM1 capture/compare
 803E equ INT_TIM     \ TIM2 update /overflow
 8042 equ INT_TIM2CC  \ TIM2 capture/compare
-804E equ INT_UART1TX \ Tx complete
-8052 equ INT_UART1RX \ Receive register DATA FULL
+\ 8046
+\ 804A
+804E equ INT_UARTTX  \ UART1 Tx complete
+8052 equ INT_UARTRX  \ UART1 Receive register DATA FULL
 8056 equ INT_I2C     \ I2C interrupt
+\ 805A
+\ 805E
 8062 equ INT_ADC1    \ ADC1 end of conversion/analog watchdog interrupt
 8066 equ INT_TIM4    \ TIM4 update/overflow
 806A equ INT_FLASH   \ Flash EOP/WR_PG_DIS
+\ 806E
+\ 8072
+\ 8076
+\ 807A
+\ 807E
 
                  \ Register name                      \ Reset status
 4800 equ OPT0    \ Options 0

diff --git a/mcu/STM8S105.efr b/mcu/STM8S105.efr
@@ -18,6 +18,8 @@
 4000 equ BIT14
 8000 equ BIT15
 
+8002 equ RESET_VECTOR
+8006 equ TRAP_VETCOR
                      \ Interrupt vectors (16 bit part)
 800A equ INT_TLI     \ External top level interrupt
 800E equ INT_AWU     \ Auto wake up from halt
@@ -27,19 +29,28 @@
 801E equ INT_EXTI2   \ Port C external interrupts
 8022 equ INT_EXTI3   \ Port D external interrupts
 8026 equ INT_EXTI4   \ Port E external interrupts
+\ 802A
+\ 802E
 8032 equ INT_SPI     \ End of transfer
 8036 equ INT_TIM1    \ TIM1 update/overflow/underflow/ trigger/break
 803A equ INT_TIM1CC  \ TIM1 capture/compare
 803E equ INT_TIM     \ TIM2 update /overflow
 8042 equ INT_TIM2CC  \ TIM2 capture/compare
 8046 equ INT_TIM3    \ TIM3 update /overflow
 804A equ INT_TIM3CC  \ TIM3 capture/compare
+\ 804E
+\ 8052
 8056 equ INT_I2C     \ I2C interrupt
-805A equ INT_UART2TX \ Tx complete
-805C equ INT_UART2RX \ Receive register DATA FULL
+805A equ INT_UARTTX  \ UART2 Tx complete
+805C equ INT_UARTRX  \ UART2 Receive register DATA FULL
 8062 equ INT_ADC1    \ ADC1 end of conversion/analog watchdog interrupt
 8066 equ INT_TIM4    \ TIM4 update/overflow
 806A equ INT_FLASH   \ Flash EOP/WR_PG_DIS
+\ 806E
+\ 8072
+\ 8076
+\ 807A
+\ 807E
 
                  \ Register name                      \ Reset status
 4800 equ OPT0    \ Options 0