.map
+ - > `map文件`，工程编译后产生，用于分析符号映射相关信息
+
+
+
+
+### 三、静态库
+
+
+
+![F28002x_三角函数库相关说明][F28002x_三角函数库相关说明]
+
+
+
+如上图所示，`rts2800_fpu32_eabi.lib` 为主要函数静态库，它主要提供了 C 标准库相关的库函数，覆盖范围最广，其中也包括三角函数 sin、cos 等等；而 `rts2800_fpu32_fast_supplement_eabi.lib` 则是对 `rts2800_fpu32_eabi.lib` 中部分三角函数的覆写，采用更快的 LUT 查找表方式实现；除了这两个静态库以外，`TMU 单元`则可对更小范围的三角函数进行硬件级别的支持，通过生成对应的硬件指令，以实现更快的代码执行速度和更小的代码体积。
+
+- Floating Point mode (--fp_mode) = `relaxed` ---> 使能 TMU 单元
+ - 此时 `rts2800_fpu32_fast_supplement_eabi.lib` 中的部分函数（如上图所示）被硬件指令集替代，通过这些硬件指令集实现的相关计算不完全符合 ISO 规范，并且会损失一些精度，但是可以有更快的执行速度以及更小的代码。
+- Floating Point mode (--fp_mode) = `strict` ---> 禁能 TMU 单元
+ - 此时 `rts2800_fpu32_fast_supplement_eabi.lib` 中所有的库函数都将由 LUT 的方式实现，并且在程序链接阶段，该库将会覆盖 `rts2800_fpu32_eabi.lib` 中的同名函数（即优先被链接器链接）。
+
+
+
+
+### 四、工程设置
+
+
+
+![优化设置][优化设置]
+
+
+
+> - 优化等级
+> - 2 级优化：使能 DriverLib 函数内联、……
+> - 4 级优化：For sin32, cos32 and sincos32 on devices with limited memory、……
+> - 速度 vs. 代码尺寸优化
+> - 默认 2 级
+> - 浮点模式
+> - relaxed：使能 TMU 单元
+> - strict：关闭 TMU 单元
+
+
+
+![库选择和切换][库选择和切换]
+
+
+
+> 在此可方便切换 `C2000WARE` 的库版本：配合`头文件包含设置（Include Options）`和`库引用设置（File Search Path）`以及工程中的`库源文件相对链接引用`，可实现无缝切换库版本并进行编译。
+
+
+
+![头文件包含设置][头文件包含设置]
+
+
+
+> 工程头文件包含设置统一使用相对路径的方式，例如相对 `${COM_TI_C2000WARE_SOFTWARE_PACKAGE_INSTALL_DIR}/` 目录进行头文件的引用包含。
+
+
+
+![库引用设置][库引用设置]
+
+
+
+> 与头文件包含设置类似，采用相对路径法添加 `.lib` 文件进行引用链接
+>> :warning: 注意：针对 `rts2800_fpu32_fast_supplement_eabi.lib` 和 `rts2800_fpu32_eabi.lib`，必须注意两个静态库文件的引用顺序，并且，勾选下方的 `Search libraries in priority order (--priority, -priority)` 前方的复选框以使能按顺序链接库文件。
+
+
+
+![工程全局预定义宏_FLASH][工程全局预定义宏_FLASH]
+
+![工程全局预定义宏_RAM][工程全局预定义宏_RAM]
+
+
+
+> 工程全局预定义宏设置： :warning: 注意 `Configuration` 不同，预定义宏会有差别。
+
+
+
+![语言设置][语言设置]
+
+
+
+> 部分 C 语法需要 C99 支持，故选择 C99 mode。
+
+
+
+![堆栈大小设置][堆栈大小设置]
+
+
+
+> `堆`大小默认为空，可能需要设置一下，否则编译可能会有警告。
+
+## :gear: 硬件 & 软件 需求
+
+### 硬件需求
+
+- TMS320F280025 Custom PCB Board
+- Texas Instruments XDS100v3 USB Debug Probe
+
+### 软件需求
+
+- Code Composer Studio 9.3.0
+
+---
+
+## :star: License
+
+MIT License
+
+Copyright © 2021 SummerFalls
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+[F28002x_三角函数库相关说明]: ./__Docs__/F28002x_三角函数库相关说明.png
+[目录结构]: ./__Docs__/目录结构.png
+[优化设置]: ./__Docs__/优化设置.png
+[库选择和切换]: ./__Docs__/库选择和切换.png
+[头文件包含设置]: ./__Docs__/头文件包含设置.png
+[库引用设置]: ./__Docs__/库引用设置.png
+[工程全局预定义宏_FLASH]: ./__Docs__/工程全局预定义宏_FLASH.png
+[工程全局预定义宏_RAM]: ./__Docs__/工程全局预定义宏_RAM.png
+[语言设置]: ./__Docs__/语言设置.png
+[堆栈大小设置]: ./__Docs__/堆栈大小设置.png
diff --git a/User_Src/User_Device.c b/User_Src/User_Device.c
new file mode 100644
index 0000000..60ed0ac
--- /dev/null
+++ b/User_Src/User_Device.c
@@ -0,0 +1,185 @@
+/*
+ * @ : User_Device.c
+ * @ :
+ * @ : Tomy
+ * @ : 20201215
+ * @ 汾: V1.0
+ * @ ʷ: V1.0 20201215 Summary
+ *
+ * MIT License. Copyright (c) 2021 SummerFalls.
+ */
+
+#include "User_Device.h"
+#include "driverlib.h"
+
+/*******************************************************************************
+* @name : User_Device_Init
+* @brief : Function to initialize the device. Primarily initializes system control to a
+* known state by disabling the watchdog, setting up the SYSCLKOUT frequency,
+* and enabling the clocks to the peripherals.
+* @param : void
+* @retval : void
+*******************************************************************************/
+void User_Device_Init(void)
+{
+ //
+ // Disable the watchdog
+ //
+ SysCtl_disableWatchdog();
+
+#ifdef _FLASH
+ //
+ // Copy FPU Math Tables from Flash to RAM
+ //
+ // The FPUmathTablesRunStart, FPUmathTablesLoadSize, and
+ // FPUmathTablesLoadStart symbols are created by the linker. Refer to the
+ // device .cmd file.
+ //
+ memcpy(&FPUmathTablesRunStart, &FPUmathTablesLoadStart, (uint32_t)&FPUmathTablesLoadSize);
+
+ //
+ // Copy time critical code and flash setup code to RAM. This includes the
+ // following functions: InitFlash();
+ //
+ // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
+ // are created by the linker. Refer to the device .cmd file.
+ //
+ memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
+
+ //
+ // Call Flash Initialization to setup flash waitstates. This function must
+ // reside in RAM.
+ //
+ Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);
+#endif
+
+ //
+ // Set up PLL control and clock dividers
+ //
+ SysCtl_setClock(DEVICE_SETCLOCK_CFG_USER);
+
+ //
+ // Make sure the LSPCLK divider is set to the default (divide by 4)
+ //
+ SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4);
+
+ //
+ // These asserts will check that the #defines for the clock rates in
+ // device.h match the actual rates that have been configured. If they do
+ // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
+ // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
+ // expected if these are not correct.
+ //
+ ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
+ ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
+
+#ifndef _FLASH
+ //
+ // Call Device_cal function when run using debugger
+ // This function is called as part of the Boot code. The function is called
+ // in the Device_init function since during debug time resets, the boot code
+ // will not be executed and the gel script will reinitialize all the
+ // registers and the calibrated values will be lost.
+ // Sysctl_deviceCal is a wrapper function for Device_Cal
+ //
+ SysCtl_deviceCal();
+#endif
+
+ //
+ // Turn on all peripherals
+ //
+ User_Device_enableAllPeripherals();
+
+ //
+ // Lock VREGCTL Register
+ // The register VREGCTL is not supported in this device. It is locked to
+ // prevent any writes to this register
+ //
+ ASysCtl_lockVREG();
+}
+
+//*****************************************************************************
+//
+// Function to turn on all peripherals, enabling reads and writes to the
+// peripherals' registers.
+//
+// Note that to reduce power, unused peripherals should be disabled.
+//
+//*****************************************************************************
+void User_Device_enableAllPeripherals(void)
+{
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CPUBGCRC);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ERAD);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSITXA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_FSIRXA);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_LINA);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_LINB);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_PMBUSA);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC1);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB1);
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLB2);
+
+ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HICA);
+}
+
+//*****************************************************************************
+//
+// Function to disable pin locks and enable pullups on GPIOs.
+//
+//*****************************************************************************
+void User_Device_initGPIO(void)
+{
+ //
+ // Disable pin locks.
+ //
+ GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF);
+ GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF);
+ GPIO_unlockPortConfig(GPIO_PORT_H, 0xFFFFFFFF);
+}
+
+/* -------------------------------------------- END OF FILE -------------------------------------------- */
diff --git a/User_Src/User_Device.h b/User_Src/User_Device.h
new file mode 100644
index 0000000..2e5a7f5
--- /dev/null
+++ b/User_Src/User_Device.h
@@ -0,0 +1,106 @@
+/*
+ * @ : User_Device.h
+ * @ :
+ * @ : Tomy
+ * @ : 20201215
+ * @ 汾: V1.0
+ * @ ʷ: V1.0 20201215 Summary
+ *
+ * MIT License. Copyright (c) 2021 SummerFalls.
+ */
+
+#ifndef USER_SRC_USER_DEVICE_H_
+#define USER_SRC_USER_DEVICE_H_
+
+#include "driverlib.h"
+
+//*****************************************************************************
+//
+// Defines related to clock configuration
+//
+//*****************************************************************************
+//
+// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
+//
+#define DEVICE_OSCSRC_FREQ 20000000U
+
+//
+// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
+// PLLSYSCLK = 20MHz (XTAL_OSC) * 30 (IMULT) / (2 (REFDIV) * 3 (ODIV) * 1(SYSDIV))
+// PLLSYSCLK = 10MHz (INT_OSC2) * 60 (IMULT) / (2 (REFDIV) * 3 (ODIV) * 1(SYSDIV))
+//
+
+#define DEVICE_SETCLOCK_CFG_USER (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(60) | \
+ SYSCTL_REFDIV(2) | SYSCTL_ODIV(3) | \
+ SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | \
+ SYSCTL_DCC_BASE_0)
+
+//
+// 100MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
+// code below if a different clock configuration is used!
+//
+#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 30) / (2 * 3 * 1))
+
+
+//
+// 25MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
+// low speed peripheral clock divider of 4. Update the code below if a
+// different LSPCLK divider is used!
+//
+#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
+
+//*****************************************************************************
+//
+// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
+// will convert the desired delay in microseconds to the count value expected
+// by the function. \b x is the number of microseconds to delay.
+//
+//*****************************************************************************
+#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \
+ (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L)
+
+//
+// Defines for setting FSI clock speeds
+//
+#define FSI_PRESCALE_50MHZ 1U
+#define FSI_PRESCALE_25MHZ 2U
+#define FSI_PRESCALE_10MHZ 5U
+#define FSI_PRESCALE_5MHZ 10U
+
+//*****************************************************************************
+//
+// Defines, Globals, and Header Includes related to Flash Support
+//
+//*****************************************************************************
+#ifdef _FLASH
+#include
+
+extern uint16_t RamfuncsLoadStart;
+extern uint16_t RamfuncsLoadEnd;
+extern uint16_t RamfuncsLoadSize;
+extern uint16_t RamfuncsRunStart;
+extern uint16_t RamfuncsRunEnd;
+extern uint16_t RamfuncsRunSize;
+#endif
+
+#define DEVICE_FLASH_WAITSTATES 4
+
+/* For rts2800_fpu32_fast_supplement_eabi.lib LUT */
+#ifdef _FLASH
+extern uint16_t FPUmathTablesLoadStart;
+extern uint16_t FPUmathTablesLoadSize;
+extern uint16_t FPUmathTablesRunStart;
+#endif
+
+//*****************************************************************************
+//
+// Function Prototypes
+//
+//*****************************************************************************
+void User_Device_Init(void);
+void User_Device_enableAllPeripherals(void);
+void User_Device_initGPIO(void);
+
+#endif /* USER_SRC_USER_DEVICE_H_ */
+
+/* -------------------------------------------- END OF FILE -------------------------------------------- */
diff --git a/User_Src/User_HAL.c b/User_Src/User_HAL.c
new file mode 100644
index 0000000..bf9afb4
--- /dev/null
+++ b/User_Src/User_HAL.c
@@ -0,0 +1,33 @@
+/*
+ * @ : User_HAL.c
+ * @ :
+ * @ : Tomy
+ * @ : 20201215
+ * @ 汾: V1.0
+ * @ ʷ: V1.0 20201215 Summary
+ *
+ * MIT License. Copyright (c) 2021 SummerFalls.
+ */
+
+#include "User_HAL.h"
+#include "device.h"
+
+/*******************************************************************************
+* @name : HAL_setupCpuTimer
+* @brief : setup CPU Timer
+* @param : void
+* @retval : void
+*******************************************************************************/
+void HAL_setupCpuTimer(uint32_t base, uint32_t periodCount)
+{
+ CPUTimer_setPreScaler(base, 0); // divide by 1 (SYSCLKOUT)
+ CPUTimer_setPeriod(base, periodCount);
+ CPUTimer_stopTimer(base); // Stop timer / reload / restart
+ CPUTimer_setEmulationMode(base, CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
+ CPUTimer_reloadTimerCounter(base); // Reload counter with period value
+ CPUTimer_resumeTimer(base);
+
+ return;
+}
+
+/* -------------------------------------------- END OF FILE -------------------------------------------- */
diff --git a/User_Src/User_HAL.h b/User_Src/User_HAL.h
new file mode 100644
index 0000000..9ba248b
--- /dev/null
+++ b/User_Src/User_HAL.h
@@ -0,0 +1,50 @@
+/*
+ * @ : User_HAL.h
+ * @ :
+ * @ : Tomy
+ * @ : 20201215
+ * @ 汾: V1.0
+ * @ ʷ: V1.0 20201215 Summary
+ *
+ * MIT License. Copyright (c) 2021 SummerFalls.
+ */
+
+#ifndef USER_SRC_USER_HAL_H_
+#define USER_SRC_USER_HAL_H_
+
+#include
+
+//
+// Define the system frequency (MHz)
+//
+#define SYSTEM_FREQUENCY (DEVICE_SYSCLK_FREQ / 1000000U)
+
+//
+// Timer definitions based on System Clock
+//
+#define MICROSEC SYSTEM_FREQUENCY
+#define MICROSEC_50 50 * MICROSEC // 50 uS
+#define MICROSEC_100 100 * MICROSEC // 0.1 mS
+#define MICROSEC_150 150 * MICROSEC // 0.15 mS
+#define MILLISEC 1000 * MICROSEC // 1 mS
+
+#define MILSEC_0_5 0.5 * MILLISEC // 0.5 mS
+#define MILSEC_1 1.0 * MILLISEC // 1.0 mS
+#define MILSEC_2 2.0 * MILLISEC // 2.0 mS
+#define MILSEC_5 5.0 * MILLISEC // 5.0 mS
+#define MILSEC_7_5 7.5 * MILLISEC // 7.5 mS
+#define MILSEC_10 10 * MILLISEC // 10 mS
+#define MILSEC_20 20 * MILLISEC // 20 mS
+#define MILSEC_50 50 * MILLISEC // 50 mS
+#define MILSEC_100 100 * MILLISEC // 100 mS
+#define MILSEC_500 500 * MILLISEC // 500 mS
+#define MILSEC_1000 1000 * MILLISEC // 1000 mS
+
+//! \brief Sets up the CPU timers
+//! \param[in] base The cpu timer base
+//! \param[in] periodCount The cpu timer period count
+extern void HAL_setupCpuTimer(uint32_t base, uint32_t periodCount);
+
+#endif /* USER_SRC_USER_HAL_H_ */
+
+/* -------------------------------------------- END OF FILE -------------------------------------------- */
diff --git "a/__Docs__/F28002x_\344\270\211\350\247\222\345\207\275\346\225\260\345\272\223\347\233\270\345\205\263\350\257\264\346\230\216.drawio" "b/__Docs__/F28002x_\344\270\211\350\247\222\345\207\275\346\225\260\345\272\223\347\233\270\345\205\263\350\257\264\346\230\216.drawio"
new file mode 100644
index 0000000..189fc9f
--- /dev/null
+++ "b/__Docs__/F28002x_\344\270\211\350\247\222\345\207\275\346\225\260\345\272\223\347\233\270\345\205\263\350\257\264\346\230\216.drawio"
@@ -0,0 +1 @@
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\ No newline at end of file
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diff --git a/f28002x_headers_nonbios.cmd b/f28002x_headers_nonbios.cmd
new file mode 100644
index 0000000..188603c
--- /dev/null
+++ b/f28002x_headers_nonbios.cmd
@@ -0,0 +1,268 @@
+MEMORY
+{
+ ADCA_RESULT : origin = 0x000B00, length = 0x000020
+ ADCC_RESULT : origin = 0x000B40, length = 0x000020
+ ADCA : origin = 0x007400, length = 0x000080
+ ADCC : origin = 0x007500, length = 0x000080
+
+ ANALOG_SUBSYS : origin = 0x05D700, length = 0x000100
+
+ BGCRC : origin = 0x006340, length = 0x000080
+
+ CANA : origin = 0x048000, length = 0x000800
+
+ CLB_LOGIC_CONFIG1 : origin = 0x00003000, length = 0x00000100
+ CLB_LOGIC_CONFIG2 : origin = 0x00003200, length = 0x00000100
+ CLB_LOGIC_CONTROL1 : origin = 0x00003100, length = 0x00000080
+ CLB_LOGIC_CONTROL2 : origin = 0x00003300, length = 0x00000080
+ CLB_DATA_EXCHANGE1 : origin = 0x00003180, length = 0x00000080
+ CLB_DATA_EXCHANGE2 : origin = 0x00003380, length = 0x00000080
+
+ CLB_XBAR : origin = 0x007A40, length = 0x000040
+
+ CMPSS1 : origin = 0x005C80, length = 0x000020
+ CMPSS2 : origin = 0x005CA0, length = 0x000020
+ CMPSS3 : origin = 0x005CC0, length = 0x000020
+ CMPSS4 : origin = 0x005CE0, length = 0x000020
+
+ CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
+ CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */
+ CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */
+
+ DCC0 : origin = 0x05E700, length = 0x000040
+ DCC1 : origin = 0x05E740, length = 0x000040
+
+ DCSM_BANK0_Z1 : origin = 0x05F000, length = 0x000030
+ DCSM_BANK0_Z2 : origin = 0x05F040, length = 0x000030
+ DCSM_BANK1_Z1 : origin = 0x05F100, length = 0x000030
+ DCSM_BANK1_Z2 : origin = 0x05F140, length = 0x000030
+ DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */
+ DCSM_COMMON2 : origin = 0x05F080, length = 0x000010 /* Common Dual code security module registers */
+
+ DMA : origin = 0x001000, length = 0x000200
+
+ ECAP1 : origin = 0x005200, length = 0x000040 /* Enhanced Capture 1 registers */
+ ECAP2 : origin = 0x005240, length = 0x000040 /* Enhanced Capture 2 registers */
+ ECAP3 : origin = 0x005280, length = 0x000040 /* Enhanced Capture 3 registers */
+
+ EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */
+ EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */
+ EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */
+ EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */
+ EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */
+ EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */
+ EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */
+
+ EPWM_XBAR : origin = 0x007A00, length = 0x000040
+
+ EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */
+ EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */
+
+ FLASH0_CTRL : origin = 0x05F800, length = 0x000300
+ FLASH0_ECC : origin = 0x05FB00, length = 0x000040
+
+ FSITXA : origin = 0x006600, length = 0x000080
+ FSIRXA : origin = 0x006680, length = 0x000080
+
+ GPIOCTRL : origin = 0x007C00, length = 0x000200 /* GPIO control registers */
+ GPIODAT : origin = 0x007F00, length = 0x000040 /* GPIO data registers */
+
+ HIC : origin = 0x006500, length = 0x000100
+
+ I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */
+ I2CB : origin = 0x007340, length = 0x000040 /* I2C-A registers */
+
+ INPUT_XBAR : origin = 0x007900, length = 0x000020
+
+ LINA : origin = 0x006A00, length = 0x000100
+ LINB : origin = 0x006B00, length = 0x000100
+
+ MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */
+ ACCESSPROTECTION : origin = 0x05F500, length = 0x000040 /* Access Protection registers */
+ MEMORYERROR : origin = 0x05F540, length = 0x000040 /* Access Protection registers */
+
+ NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */
+
+ OUTPUT_XBAR : origin = 0x007A80, length = 0x000040
+
+ PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
+
+ PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */
+
+ PMBUSA : origin = 0x006400, length = 0x000020
+
+ SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */
+
+ SPIA : origin = 0x006100, length = 0x000010
+ SPIB : origin = 0x006110, length = 0x000010
+
+ WD : origin = 0x007000, length = 0x000040
+ DMACLASRCSEL : origin = 0x007980, length = 0x000040
+ DEV_CFG : origin = 0x05D000, length = 0x0001A0
+ CLK_CFG : origin = 0x05D200, length = 0x000100
+ CPU_SYS : origin = 0x05D300, length = 0x000100
+ PERIPH_AC : origin = 0x05D500, length = 0x000200
+
+ ERAD_GLOBAL : origin = 0x05E800, length = 0x000014
+ ERAD_HWBP1 : origin = 0x05E900, length = 0x000008
+ ERAD_HWBP2 : origin = 0x05E908, length = 0x000008
+ ERAD_HWBP3 : origin = 0x05E910, length = 0x000008
+ ERAD_HWBP4 : origin = 0x05E918, length = 0x000008
+ ERAD_HWBP5 : origin = 0x05E920, length = 0x000008
+ ERAD_HWBP6 : origin = 0x05E928, length = 0x000008
+ ERAD_HWBP7 : origin = 0x05E930, length = 0x000008
+ ERAD_HWBP8 : origin = 0x05E938, length = 0x000008
+ ERAD_CTR1 : origin = 0x05E980, length = 0x000010
+ ERAD_CTR2 : origin = 0x05E990, length = 0x000010
+ ERAD_CTR3 : origin = 0x05E9A0, length = 0x000010
+ ERAD_CTR4 : origin = 0x05E9B0, length = 0x000010
+
+ XBAR : origin = 0x007920, length = 0x000020
+ SYNC_SOC : origin = 0x007940, length = 0x000010
+
+ XINT : origin = 0x007070, length = 0x000010
+}
+
+SECTIONS
+{
+/*** PIE Vect Table and Boot ROM Variables Structures ***/
+ UNION run = PIE_VECT
+ {
+ PieVectTableFile
+ GROUP
+ {
+ EmuKeyVar
+ EmuBModeVar
+ FlashCallbackVar
+ FlashScalingVar
+ }
+ }
+
+ AdcaResultFile : > ADCA_RESULT, type=NOINIT
+ AdccResultFile : > ADCC_RESULT, type=NOINIT
+
+ AdcaRegsFile : > ADCA, type=NOINIT
+ AdccRegsFile : > ADCC, type=NOINIT
+
+ AnalogSubsysRegsFile : > ANALOG_SUBSYS, type=NOINIT
+
+ BgcrcRegsFile : > BGCRC, type=NOINIT
+
+ CanaRegsFile : > CANA, type=NOINIT
+
+ Clb1LogicCfgRegsFile : > CLB_LOGIC_CONFIG1, type=NOINIT
+ Clb2LogicCfgRegsFile : > CLB_LOGIC_CONFIG2, type=NOINIT
+ Clb1LogicCtrlRegsFile : > CLB_LOGIC_CONTROL1, type=NOINIT
+ Clb2LogicCtrlRegsFile : > CLB_LOGIC_CONTROL2, type=NOINIT
+ Clb1DataExchgRegsFile : > CLB_DATA_EXCHANGE1, type=NOINIT
+ Clb2DataExchgRegsFile : > CLB_DATA_EXCHANGE2, type=NOINIT
+
+ ClbXbarRegsFile : > CLB_XBAR, type=NOINIT
+
+ Cmpss1RegsFile : > CMPSS1, type=NOINIT
+ Cmpss2RegsFile : > CMPSS2, type=NOINIT
+ Cmpss3RegsFile : > CMPSS3, type=NOINIT
+ Cmpss4RegsFile : > CMPSS4, type=NOINIT
+
+ CpuTimer0RegsFile : > CPU_TIMER0, type=NOINIT
+ CpuTimer1RegsFile : > CPU_TIMER1, type=NOINIT
+ CpuTimer2RegsFile : > CPU_TIMER2, type=NOINIT
+
+ Dcc0RegsFile : > DCC0, type=NOINIT
+ Dcc1RegsFile : > DCC1, type=NOINIT
+
+ DcsmBank0Z1RegsFile : > DCSM_BANK0_Z1, type=NOINIT
+ DcsmBank0Z2RegsFile : > DCSM_BANK0_Z2, type=NOINIT
+ DcsmBank1Z1RegsFile : > DCSM_BANK1_Z1, type=NOINIT
+ DcsmBank1Z2RegsFile : > DCSM_BANK1_Z2, type=NOINIT
+ DcsmCommonRegsFile : > DCSM_COMMON, type=NOINIT
+ DcsmCommon2RegsFile : > DCSM_COMMON2, type=NOINIT
+
+ DmaRegsFile : > DMA, type=NOINIT
+
+ ECap1RegsFile : > ECAP1, type=NOINIT
+ ECap2RegsFile : > ECAP2, type=NOINIT
+ ECap3RegsFile : > ECAP3, type=NOINIT
+
+ EPwm1RegsFile : > EPWM1, type=NOINIT
+ EPwm2RegsFile : > EPWM2, type=NOINIT
+ EPwm3RegsFile : > EPWM3, type=NOINIT
+ EPwm4RegsFile : > EPWM4, type=NOINIT
+ EPwm5RegsFile : > EPWM5, type=NOINIT
+ EPwm6RegsFile : > EPWM6, type=NOINIT
+ EPwm7RegsFile : > EPWM7, type=NOINIT
+
+ EPwmXbarRegsFile : > EPWM_XBAR, type=NOINIT
+
+ EQep1RegsFile : > EQEP1, type=NOINIT
+ EQep2RegsFile : > EQEP2, type=NOINIT
+
+ EnhancedDebugGlobalRegsFile : > ERAD_GLOBAL, type=NOINIT
+ EnhancedDebugHWBP1RegsFile : > ERAD_HWBP1, type=NOINIT
+ EnhancedDebugHWBP2RegsFile : > ERAD_HWBP2, type=NOINIT
+ EnhancedDebugHWBP3RegsFile : > ERAD_HWBP3, type=NOINIT
+ EnhancedDebugHWBP4RegsFile : > ERAD_HWBP4, type=NOINIT
+ EnhancedDebugHWBP5RegsFile : > ERAD_HWBP5, type=NOINIT
+ EnhancedDebugHWBP6RegsFile : > ERAD_HWBP6, type=NOINIT
+ EnhancedDebugHWBP7RegsFile : > ERAD_HWBP7, type=NOINIT
+ EnhancedDebugHWBP8RegsFile : > ERAD_HWBP8, type=NOINIT
+ EnhancedDebugCounter1RegsFile : > ERAD_CTR1, type=NOINIT
+ EnhancedDebugCounter2RegsFile : > ERAD_CTR2, type=NOINIT
+ EnhancedDebugCounter3RegsFile : > ERAD_CTR3, type=NOINIT
+ EnhancedDebugCounter4RegsFile : > ERAD_CTR4, type=NOINIT
+
+ Flash0CtrlRegsFile : > FLASH0_CTRL, type=NOINIT
+ Flash0EccRegsFile : > FLASH0_ECC, type=NOINIT
+
+ FsiTxaRegsFile : > FSITXA, type=NOINIT
+ FsiRxaRegsFile : > FSIRXA, type=NOINIT
+
+ GpioCtrlRegsFile : > GPIOCTRL, type=NOINIT
+ GpioDataRegsFile : > GPIODAT, type=NOINIT
+
+ HicRegsFile : > HIC, type=NOINIT
+
+ I2caRegsFile : > I2CA, type=NOINIT
+ I2cbRegsFile : > I2CB, type=NOINIT
+
+ InputXbarRegsFile : > INPUT_XBAR, type=NOINIT
+ XbarRegsFile : > XBAR, type=NOINIT
+
+ LinaRegsFile : > LINA, type=NOINIT
+ LinbRegsFile : > LINB, type=NOINIT
+
+ MemCfgRegsFile : > MEMCFG, type=NOINIT
+ AccessProtectionRegsFile : > ACCESSPROTECTION, type=NOINIT
+ MemoryErrorRegsFile : > MEMORYERROR, type=NOINIT
+
+ NmiIntruptRegsFile : > NMIINTRUPT, type=NOINIT
+
+ OutputXbarRegsFile : > OUTPUT_XBAR, type=NOINIT
+
+ PieCtrlRegsFile : > PIE_CTRL, type=NOINIT
+
+ PmbusaRegsFile : > PMBUSA, type=NOINIT
+
+ SciaRegsFile : > SCIA, type=NOINIT
+
+ SpiaRegsFile : > SPIA, type=NOINIT
+ SpibRegsFile : > SPIB, type=NOINIT
+
+ WdRegsFile : > WD, type=NOINIT
+ DmaClaSrcSelRegsFile : > DMACLASRCSEL, type=NOINIT
+ DevCfgRegsFile : > DEV_CFG, type=NOINIT
+ ClkCfgRegsFile : > CLK_CFG, type=NOINIT
+ CpuSysRegsFile : > CPU_SYS, type=NOINIT
+ SysPeriphAcRegsFile : > PERIPH_AC, type=NOINIT
+
+ SyncSocRegsFile : > SYNC_SOC, type=NOINIT
+
+ XintRegsFile : > XINT, type=NOINIT
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
diff --git a/main.c b/main.c
new file mode 100644
index 0000000..57764b3
--- /dev/null
+++ b/main.c
@@ -0,0 +1,252 @@
+/*
+ * @ : main.c
+ * @ :
+ * @ : Tomy
+ * @ : 20201215
+ * @ 汾: V1.0
+ * @ ʷ: V1.0 20201215 Summary
+ *
+ * MIT License. Copyright (c) 2021 SummerFalls.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/* LIB_0: driverlib */
+#include "device.h"
+
+/* LIB_1: Bit-field */
+#include "f28x_project.h"
+
+/* C2000Ware_X_XX_XX_XX_Software\libraries\math\FPUfastRTS\c28\lib\rts2800_fpu32_fast_supplement_eabi.lib */
+#include "fastrts.h"
+#include "fpu32/C28x_FPU_FastRTS.h"
+
+/* C2000Ware_X_XX_XX_XX_Software\libraries\math\IQmath\c28\lib\IQmath_fpu32_eabi.lib */
+/* Properties -> Build -> C2000 Compiler -> Predefined Symbols: MATH_TYPE=FLOAT_MATH */
+#include "IQmathLib.h"
+
+/* User Include Header Files */
+#include "User_Device.h"
+#include "User_HAL.h"
+
+//
+// State Machine function prototypes
+//
+
+// Alpha states
+void A0(void); //state A0
+void B0(void); //state B0
+
+// A branch states
+void A1(void); //state A1
+void A2(void); //state A2
+void A3(void); //state A3
+
+// B branch states
+void B1(void); //state B1
+void B2(void); //state B2
+void B3(void); //state B3
+
+//
+// Global variables used in this system
+//
+
+// Variable declarations
+void (*Alpha_State_Ptr)(void); // Base States pointer
+void (*A_Task_Ptr)(void); // State pointer A branch
+void (*B_Task_Ptr)(void); // State pointer B branch
+
+uint16_t vTimer0[4]; // Virtual Timers slaved off CPU Timer 0 (A events)
+uint16_t vTimer1[4]; // Virtual Timers slaved off CPU Timer 1 (B events)
+
+
+/* For Math Library Test */
+float fa = 55.55232f;
+float fb = 123.44f;
+float fc = 0.0f;
+_iq testIQ = _IQ(0.15);
+float64_t v64 = 0.0;
+float32u_t in, out_s, out_c;
+int32_t vint32 = 0;
+
+void main(void)
+{
+ /* Device_init() replaced by User_Device_Init() for the macro DEVICE_SETCLOCK_CFG */
+ User_Device_Init();
+
+ //
+ // Timing sync for background loops
+ //
+ HAL_setupCpuTimer(CPUTIMER0_BASE, MICROSEC_50); // A tasks
+ HAL_setupCpuTimer(CPUTIMER1_BASE, MICROSEC_100); // B tasks
+
+ // Tasks State-machine init
+ Alpha_State_Ptr = &A0;
+ A_Task_Ptr = &A1;
+ B_Task_Ptr = &B1;
+
+ //
+ // Initializations COMPLETE
+ // - IDLE loop. Just loop forever
+ //
+ for(;;) //infinite loop
+ {
+ // State machine entry & exit point
+ //===========================================================
+ (*Alpha_State_Ptr)(); // jump to an Alpha state (A0,B0,...)
+ //===========================================================
+ }
+}
+
+//=============================================================================
+// STATE-MACHINE SEQUENCING AND SYNCRONIZATION FOR SLOW BACKGROUND TASKS
+//=============================================================================
+
+//--------------------------------- FRAMEWORK ---------------------------------
+void A0(void)
+{
+ // loop rate synchronizer for A-tasks
+ if(CPUTimer_getTimerOverflowStatus(CPUTIMER0_BASE))
+ {
+ CPUTimer_clearOverflowFlag(CPUTIMER0_BASE); // clear flag
+
+ //-----------------------------------------------------------
+ (*A_Task_Ptr)(); // jump to an A Task (A1,A2,A3,...)
+ //-----------------------------------------------------------
+
+ vTimer0[0]++; // virtual timer 0, instance 0 (spare)
+ }
+
+ Alpha_State_Ptr = &B0; // Comment out to allow only A tasks
+}
+
+void B0(void)
+{
+ // loop rate synchronizer for B-tasks
+ if(CPUTimer_getTimerOverflowStatus(CPUTIMER1_BASE))
+ {
+ CPUTimer_clearOverflowFlag(CPUTIMER1_BASE); // clear flag
+
+ //-----------------------------------------------------------
+ (*B_Task_Ptr)(); // jump to a B Task (B1,B2,B3,...)
+ //-----------------------------------------------------------
+
+ vTimer1[0]++; // virtual timer 1, instance 0 (spare)
+ }
+
+ Alpha_State_Ptr = &A0; // Allow A state tasks
+}
+
+//==============================================================================
+// A - TASKS (executed in every 50 usec)
+//==============================================================================
+
+//--------------------------------------------------------
+void A1(void) // SPARE (not used)
+//--------------------------------------------------------
+{
+ //-------------------
+ //the next time CpuTimer0 'counter' reaches Period value go to A2
+ A_Task_Ptr = &A2;
+ //-------------------
+}
+
+//-----------------------------------------------------------------
+void A2(void) // SPARE (not used)
+//-----------------------------------------------------------------
+{
+ //-------------------
+ //the next time CpuTimer0 'counter' reaches Period value go to A3
+ A_Task_Ptr = &A3;
+ //-------------------
+}
+
+//-----------------------------------------
+void A3(void) // SPARE (not used)
+//-----------------------------------------
+{
+ //-----------------
+ //the next time CpuTimer0 'counter' reaches Period value go to A1
+ A_Task_Ptr = &A1;
+ //-----------------
+}
+
+//==============================================================================
+// B - TASKS (executed in every 100 usec)
+//==============================================================================
+
+//----------------------------------- USER -------------------------------------
+
+//----------------------------------------
+void B1(void) // Toggle GPIO-00
+//----------------------------------------
+{
+ //-----------------
+ //the next time CpuTimer1 'counter' reaches Period value go to B2
+ B_Task_Ptr = &B2;
+ //-----------------
+
+ //
+ // Run the test for rts2800_fpu32_fast_supplement_eabi.libIQmath_fpu32_eabi.libTMU
+ //
+ fc = fa + fb * 2;
+ testIQ = _IQ(1.9) * _IQ(3.8);
+ testIQ = 1.9 * 3.8;
+ testIQ = 1.9f * 3.8f;
+ v64 = 1.9 * 3.8;
+ vint32 = 1.9 * v64;
+ vint32 = 1.9f * v64;
+ testIQ = testIQ * _IQsin(30.0);
+ testIQ = cos(testIQ);
+ testIQ = sinf(testIQ);
+
+
+ testIQ = fabsf(-32947.223F);
+ testIQ = isqrtf(2.718281828459e+00F);
+ testIQ = sqrtf(3.120923179706e+00F);
+ testIQ = sinf(3.067961575771F);
+ testIQ = cosf(46.33178F);
+ testIQ = atanf(0.695312500000F);
+ testIQ = atan2f(7.0F, -7.0F);
+
+ /* Runs the sincos routine ---------------------------------------- */
+ out_s.f32 = FLT_MAX;
+ out_c.f32 = FLT_MAX;
+ in.f32 = -2.589359569951F;
+ sincosf(in.f32, (float32_t *)&out_s, (float32_t *)&out_c);
+
+ /* Runs the FD$$DIV routine in the ASM file: fs_div28.asm ---------------------------------------- */
+ fa = 2.718281828459e+00F;
+ fb = -2.000000000000e+00F;
+ fc = fa / fb;
+ fc = testIQ / fc;
+
+ /* ---------------------------------------- */
+ testIQ = expf(3.06796157577F);
+ testIQ = logf(63.06835937500F);
+ testIQ = powf(1.44337660406F, -1.84077694546F);
+}
+
+//----------------------------------------
+void B2(void) // SPARE
+//----------------------------------------
+{
+ //-----------------
+ //the next time CpuTimer1 'counter' reaches Period value go to B3
+ B_Task_Ptr = &B3;
+ //-----------------
+}
+
+//----------------------------------------
+void B3(void) // SPARE
+//----------------------------------------
+{
+ //-----------------
+ //the next time CpuTimer1 'counter' reaches Period value go to B1
+ B_Task_Ptr = &B1;
+ //-----------------
+}
diff --git a/targetConfigs/TMS320F280025C.ccxml b/targetConfigs/TMS320F280025C.ccxml
new file mode 100644
index 0000000..f77f931
--- /dev/null
+++ b/targetConfigs/TMS320F280025C.ccxml
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/targetConfigs/readme.txt b/targetConfigs/readme.txt
new file mode 100644
index 0000000..d783fef
--- /dev/null
+++ b/targetConfigs/readme.txt
@@ -0,0 +1,9 @@
+The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
+on the device and connection settings specified in your project on the Properties > General page.
+
+Please note that in automatic target-configuration management, changes to the project's device and/or
+connection settings will either modify an existing or generate a new target-configuration file. Thus,
+if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
+you may create your own target-configuration file for this project and manage it manually. You can
+always switch back to automatic target-configuration management by checking the "Manage the project's
+target-configuration automatically" checkbox on the project's Properties > General page.
\ No newline at end of file