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top_level_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'top_level'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power on -o top_level_map.ncd top_level.ngd top_level.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue May 15 22:11:41 2018
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 21 secs
Total CPU time at the beginning of Placer: 18 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b04f4a9c) REAL time: 31 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:b04f4a9c) REAL time: 32 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b04f4a9c) REAL time: 32 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:1af0507a) REAL time: 37 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:1af0507a) REAL time: 37 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:1af0507a) REAL time: 37 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:1af0507a) REAL time: 37 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1af0507a) REAL time: 37 secs
Phase 9.8 Global Placement
............................................................................
...................................................................................................................................................................................................................................................
......................................................................
................................................................................
Phase 9.8 Global Placement (Checksum:2b56fc4) REAL time: 1 mins 7 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:2b56fc4) REAL time: 1 mins 7 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:d1b2e1c4) REAL time: 1 mins 29 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:d1b2e1c4) REAL time: 1 mins 29 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:849437ac) REAL time: 1 mins 29 secs
Total REAL time to Placer completion: 1 mins 29 secs
Total CPU time to Placer completion: 1 mins 22 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 22
Slice Logic Utilization:
Number of Slice Registers: 343 out of 18,224 1%
Number used as Flip Flops: 342
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,768 out of 9,112 63%
Number used as logic: 5,707 out of 9,112 62%
Number using O6 output only: 3,229
Number using O5 output only: 172
Number using O5 and O6: 2,306
Number used as ROM: 0
Number used as Memory: 1 out of 2,176 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 1
Number using O6 output only: 1
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 60
Number with same-slice register load: 52
Number with same-slice carry load: 8
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,828 out of 2,278 80%
Number of MUXCYs used: 3,144 out of 4,556 69%
Number of LUT Flip Flop pairs used: 5,790
Number with an unused Flip Flop: 5,508 out of 5,790 95%
Number with an unused LUT: 22 out of 5,790 1%
Number of fully used LUT-FF pairs: 260 out of 5,790 4%
Number of unique control sets: 29
Number of slice register sites lost
to control set restrictions: 144 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 15 out of 232 6%
Number of LOCed IOBs: 15 out of 15 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 5
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 2 out of 32 6%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.20
Peak Memory Usage: 481 MB
Total REAL time to MAP completion: 1 mins 36 secs
Total CPU time to MAP completion: 1 mins 28 secs
Mapping completed.
See MAP report file "top_level_map.mrp" for details.