Fault Detection

• Online Concurrent checkers:
  • Checker Extraction Method: The main Idea here is to go into details of the architecture and extract relevant checkers. To do so, we need a systematic approach for checker selection. One way to do that is to extract the flow chart of the system and check all the paths and also extract higher level information about these parts. This approach is rather expensive since we are checking every property of the circuit at the lowest level.
    • LBDR Checker Extraction
    • FIFO Checker Extraction
    • Arbiter Checker Extraction
    • Checkers supplementary results
• Data-Path error detection/correction mechanisms

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Relevant Publications:

• S. P. Azad, B. Niazmand, A. K. Sandhu, J. Raik, G. Jervan and T. Hollstein, "Automated area and coverage optimization of minimal latency checkers," 2017 22nd IEEE European Test Symposium (ETS), Limassol, 2017, pp. 1-2.
• Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Govind, V.; Hollstein, T.; Jervan, G. (2015). A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers. 9th International Symposium on Networks-on-Chip (NOCS) 2015. ACM, -.
• Saltarelli, P.; Niazmand, B.; Hariharan, R.; Raik, J.; Jervan, G.; Hollstein, t. (2015). Automated Minimization of Concurrent Online Checkers for Network-on-Chips. 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015). IEEE, 1−8.
• Saltarelli, P.; Niazmand, B.; Raik, J.; Hariharan, R.; Jervan, G.; Holistein, T. (2015). A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers. Euromicro Conference on Digital System Design (DSD) 2015. IEEE, 288−292.