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Net Engine FPGA with Software is an FPGA accelerator that enhances CNN performance in embedded systems by offloading tasks like 2D convolution and max-pooling, featuring the complete design of the Net Engine IP, software drivers, pre-trained models, and test data for facial computing.

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Net-Engine IP with Software

This project provides an FPGA-based hardware accelerator called the Net Engine for improving the performance of convolutional neural networks (CNNs) on embedded system. The system accelerates tasks like convolution and max-pooling by offloading them from the CPU to the FPGA.

Project Overview

The Net Engine enhances real-time facial computing by speeding up the execution of deep learning models. The project includes the FPGA hardware design, software drivers, pre-trained neural network models, and test data.

Implementation

To verify and measure performance, the Net Engine IP and Net Engine Driver were used to implement the Proposed Network for detecting facial bounding boxes.

  • Net Engine IP: A hardware IP core designed for efficient convolution operations.
  • Net Engine Driver: A driver that facilitates communication/ manipulation between the hardware IP and the processing system.

Folder Structure

Net-Engine-FPGA-With-Software
├───data                     # Input and output data for testing and validation
├───documents                # Detailed documentation and design diagrams
├───images                   # Image files related to the project
├───model                    # Pre-trained model weights for testing
└───source files             # Source code and hardware design files
    ├───net engine driver    # C code for the Net Engine driver
    ├───net engine ip        # Verilog files for the custom IP core
    │   ├───sources          # Verilog source files for the Net Engine IP
    │   └───test bench       # Testbenches for verifying IP functionality
    └───neural network       # Neural network component used for testing

Key Components

System Overview

For a detailed explanation of the system's architecture and design, please refer to the System Overview.

Net Engine IP

The Net Engine IP is a custom FPGA block designed to perform 2D convolution and max-pooling operations. It accelerates deep learning tasks by offloading these operations from the CPU to the FPGA. Links:

Net Engine Driver

The Net Engine Driver is software that configures the Net Engine and manages data transfer between the CPU and the FPGA. Links:

Neural Network Implementation

The neural Network Implementation is software component, that can be used to predict a output using above mentioned components. Links:

Additional Resources

  • Detailed technical documentation is available in the Dissertation.
  • A visual presentation of the implementation and summarized results can be found in the Project Presentation.

About

Net Engine FPGA with Software is an FPGA accelerator that enhances CNN performance in embedded systems by offloading tasks like 2D convolution and max-pooling, featuring the complete design of the Net Engine IP, software drivers, pre-trained models, and test data for facial computing.

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