Here is a demo of the Rx and Tx modules for the Arty A7 card. The connection between the FPGA and the external terminal is made through the USB port. The Rx module of the FPGA is connected to the Tx module of the FPGA. Therefore, the Tx module returns the information received by the Rx module. The baudrate for the demo is 115200, the parity is odd. Pin G13 is used to see the Tx signal.
Connection via Putty:
Tx signal (bit duration = 8.67µs 1 square = 10µS):
This is the clock for the duration of one bit as a function of the baudrate.
In:
-
clk : FPGA clock.
-
rst : Reset the clock on a rising edge of the input bit.
-
baudrate_clk_ticks : Number of rising edge on the input clock to change the state of the baudrate clock The calculation is as follows:
Example for a baud rate of 115200 bits/s and a 100MHz clock:
Out:
- baudclk : Clock at baudrate frequency.
This is the Rx component
In:
-
clk : Clock at baudrate frequency.
-
rst : Reset the clock on a rising edge of the input bit.
-
RX : Bit from transmitter.
-
parity : Parity mode.
-
timeout_value :
Example for a baud rate of 115200 bits/s (bit duration of 8.7µs) and a desired timeout duration of 130µs:
-
error_parity : Is equal to 1 if the parity bit does not correspond to the frame, 0 otherwise
-
end_reception : Equals 1 when the frame is fully received and the parity bit is calculated. Remains high for the duration of a clock cycle (from one rising edge to another).
-
timeout : Equals 1 when the timeout duration is reached. Remains high for the duration of a clock cycle (from one rising edge to another).
-
RXREG : Corresponds to the data transmitted in the frame. The data is kept for the duration of a clock cycle (from one rising edge to another).
No parity:
Odd parity with frame = 0x509 = 0101 1010 1001 :
Even parity with frame = 0x509 = 0101 1010 1001 :
Odd parity with frame = 0x1A9 = 0001 1010 1001 :
Even parity with frame = 0x1A9 = 0001 1010 1001 :
Timeout at 130µs :
This is the Tx Component.
In:
- clk : Clock at baudrate frequency.
- rst : Reset the clock on a rising edge of the input bit.
- set : Send the data on a rising edge of set.
- data : Data to send.
- parity : Parity mode.
Out:
- TX : Frame bit sent.
- end_transmission : Goes to 1 when the frame has been sent. Remains at 1 for a clock cycle ((from one rising edge to another).
No parity :
Odd parity for data = 0x43 :
Even parity for data = 0x43 :
Odd parity for data = 0x44 :
Even parity for data = 0x44 :
