rocm-6: reapply ISA compatibility widening patches

NixOS · Jan 21, 2025 · 0f5740f · 0f5740f
1 parent d71047b
commit 0f5740f
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Showing 8 changed files with 47 additions and 181 deletions.
diff --git a/pkgs/development/rocm-modules/6/clr/default.nix b/pkgs/development/rocm-modules/6/clr/default.nix
@@ -3,6 +3,7 @@
   stdenv,
   callPackage,
   fetchFromGitHub,
+  fetchpatch,
   rocmUpdateScript,
   makeWrapper,
   cmake,
@@ -124,28 +125,17 @@ stdenv.mkDerivation (finalAttrs: {
   patches = [
     ./cmake-find-x11-libgl.patch
     ./0001-handle-v1-of-compressed-fatbins.patch # https://github.com/ROCm/clr/issues/99
-    # ./fix-null-stream-sync-perf.patch # https://github.com/ROCm/clr/issues/78
-    # (fetchpatch {
-    #   name = "add-missing-operators.patch";
-    #   url = "https://github.com/ROCm/clr/commit/86bd518981b364c138f9901b28a529899d8654f3.patch";
-    #   hash = "sha256-lbswri+zKLxif0hPp4aeJDeVfadhWZz4z+m+G2XcCPI=";
-    # })
-    # (fetchpatch {
-    #   name = "static-functions.patch";
-    #   url = "https://github.com/ROCm/clr/commit/77c581a3ebd47b5e2908973b70adea66891159ee.patch";
-    #   hash = "sha256-auBedbd7rghlKav7A9V6l64J7VmtE9GizIdi5gWj+fs=";
-    # })
 
-    # (fetchpatch {
-    #   name = "extend-hip-isa-compatibility-check.patch";
-    #   url = "https://salsa.debian.org/rocm-team/rocm-hipamd/-/raw/d6d20142c37e1dff820950b16ff8f0523241d935/debian/patches/0026-extend-hip-isa-compatibility-check.patch";
-    #   hash = "sha256-eG0ALZZQLRzD7zJueJFhi2emontmYy6xx8Rsm346nQI=";
-    # })
-    # (fetchpatch {
-    #   name = "improve-rocclr-isa-compatibility-check.patch";
-    #   url = "https://salsa.debian.org/rocm-team/rocm-hipamd/-/raw/d6d20142c37e1dff820950b16ff8f0523241d935/debian/patches/0025-improve-rocclr-isa-compatibility-check.patch";
-    #   hash = "sha256-8eowuRiOAdd9ucKv4Eg9FPU7c6367H3eP3fRAGfXc6Y=";
-    # })
+    # improve rocclr isa compatibility check
+    (fetchpatch {
+      sha256 = "sha256-wUrhpYN68AbEXeFU5f366C6peqHyq25kujJXY/bBJMs=";
+      url = "https://github.com/GZGavinZhao/clr/commit/22c17a0ac09c6b77866febf366591f669a1ed133.patch";
+    })
+    # [PATCH] Improve hipamd compat check
+    (fetchpatch {
+      sha256 = "sha256-uZQ8rMrWH61CCbxwLqQGggDmXFmYTi6x8OcgYPrZRC8=";
+      url = "https://github.com/GZGavinZhao/clr/commit/63c6ee630966744d4199fdfb854e98d2da9e1122.patch";
+    })
   ];
 
   postPatch = ''

diff --git a/pkgs/development/rocm-modules/6/hipblaslt/default.nix b/pkgs/development/rocm-modules/6/hipblaslt/default.nix
@@ -76,6 +76,7 @@ stdenv.mkDerivation (
     requiredSystemFeatures = [ "big-parallel" ];
 
     patches = [
+      # TensileCreateExtOpLibraries build failure https://github.com/ROCm/hipBLASLt/issues/1571
       ./ext-op-first.diff
     ];
 

diff --git a/pkgs/development/rocm-modules/6/llvm/default.nix b/pkgs/development/rocm-modules/6/llvm/default.nix
@@ -309,7 +309,13 @@ rec {
           pname = "${old.pname}-rocm";
           patches = filteredPatches ++ [
             ./clang-bodge-ignore-systemwide-incls.diff
-            ./clang-log-jobs.diff # FIXME: rebase for 20+?
+            ./clang-log-jobs.diff
+            (fetchpatch {
+              # [ClangOffloadBundler]: Add GetBundleIDsInFile to OffloadBundler
+              sha256 = "sha256-G/mzUdFfrJ2bLJgo4+mBcR6Ox7xGhWu5X+XxT4kH2c8=";
+              url = "https://github.com/GZGavinZhao/rocm-llvm-project/commit/6d296f879b0fed830c54b2a9d26240da86c8bb3a.patch";
+              relative = "clang";
+            })
             # FIXME: if llvm was overrideable properly this wouldn't be needed
             (substituteAll {
               src = ./clang-at-least-16-LLVMgold-path.patch;

diff --git a/pkgs/development/rocm-modules/6/rocblas/default.nix b/pkgs/development/rocm-modules/6/rocblas/default.nix
@@ -2,6 +2,7 @@
   lib,
   stdenv,
   fetchFromGitHub,
+  fetchpatch,
   rocmUpdateScript,
   cmake,
   rocm-cmake,
@@ -170,12 +171,11 @@ stdenv.mkDerivation (finalAttrs: {
   passthru.amdgpu_targets = gpuTargets';
 
   patches = [
-    # (fetchpatch {
-    #   name = "Extend-rocBLAS-HIP-ISA-compatibility.patch";
-    #   url = "https://github.com/GZGavinZhao/rocBLAS/commit/89b75ff9cc731f71f370fad90517395e117b03bb.patch";
-    #   hash = "sha256-W/ohOOyNCcYYLOiQlPzsrTlNtCBdJpKVxO8s+4G7sjo=";
-    # })
-    # ./offload-compress.diff
+    (fetchpatch {
+      name = "Extend-rocBLAS-HIP-ISA-compatibility.patch";
+      url = "https://github.com/GZGavinZhao/rocBLAS/commit/89b75ff9cc731f71f370fad90517395e117b03bb.patch";
+      hash = "sha256-W/ohOOyNCcYYLOiQlPzsrTlNtCBdJpKVxO8s+4G7sjo=";
+    })
   ];
 
   # Pass $NIX_BUILD_CORES to Tensile

diff --git a/pkgs/development/rocm-modules/6/rocblas/offload-compress.diff b/pkgs/development/rocm-modules/6/rocblas/offload-compress.diff
diff --git a/pkgs/development/rocm-modules/6/rocblas/offload-compress.py b/pkgs/development/rocm-modules/6/rocblas/offload-compress.py
diff --git a/pkgs/development/rocm-modules/6/rocm-comgr/default.nix b/pkgs/development/rocm-modules/6/rocm-comgr/default.nix
@@ -1,6 +1,7 @@
 {
   lib,
   stdenv,
+  fetchpatch,
   cmake,
   python3,
   rocm-merged-llvm,
@@ -27,6 +28,21 @@ stdenv.mkDerivation (finalAttrs: {
 
   sourceRoot = "${finalAttrs.src.name}/amd/comgr";
 
+  patches = [
+    # [Comgr] Extend ISA compatibility
+    (fetchpatch {
+      sha256 = "sha256-dgow0kwSWM1TnkqWOZDRQrh5nuF8p5jbYyOLCpQsH4k=";
+      url = "https://github.com/GZGavinZhao/rocm-llvm-project/commit/a439e4f37ce71de48d4a979594276e3be0e6278f.patch";
+      relative = "amd/comgr";
+    })
+    #[Comgr] Extend ISA compatibility for CCOB
+    (fetchpatch {
+      sha256 = "sha256-6Rwz12Lk4R2JK3olii3cr2Zd0ZLYe7VSpK1YRCOsJWY=";
+      url = "https://github.com/GZGavinZhao/rocm-llvm-project/commit/2d8c459a4d4c0567a7a275b4b54560d88e5c6919.patch";
+      relative = "amd/comgr";
+    })
+  ];
+
   nativeBuildInputs = [
     cmake
     python3

diff --git a/pkgs/development/rocm-modules/6/tensile/default.nix b/pkgs/development/rocm-modules/6/tensile/default.nix
@@ -2,6 +2,7 @@
   lib,
   stdenv,
   fetchFromGitHub,
+  fetchpatch,
   rocmUpdateScript,
   buildPythonPackage,
   pytestCheckHook,
@@ -88,6 +89,11 @@ buildPythonPackage rec {
 
   patches =
     (lib.optional (!isTensileLite) ./tensile-6.3.0-create-library-dont-copy-twice.diff)
+    ++ (lib.optional (!isTensileLite) (fetchpatch {
+      # [PATCH] Extend Tensile HIP ISA compatibility
+      sha256 = "sha256-d+fVf/vz+sxGqJ96vuxe0jRMgbC5K6j5FQ5SJ1e3Sl8=";
+      url = "https://github.com/GZGavinZhao/Tensile/commit/855cb15839849addb0816a6dde45772034a3e41f.patch";
+    }))
     ++ (lib.optional isTensileLite ./tensile-create-library-dont-copy-twice.diff)
     ++ (lib.optional isTensileLite ./gen_assembly-venv-err-handling.diff)
     ++ (lib.optional isTensileLite ./log-fallback.diff);