AHB Bus Decoder

[nickelpro]

No description provided.

[rishyak]

The decoder is used to perform centralised address decoding, which improves the portability of peripherals by making them independent of the system memory map.

General outline for address decoding:

• The central decoder is used to provide the select signal selX, for each of the subordinates on the bus

• A subordinate must only sample the address and control signals and selX when ready is high (current transfer is completing)

• The minimum address space that can be allocated to a single subordinate is 1kB

• The manager will be designed such that they will not perform incrementing transfers over 1kb

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Default Subordinate Note

In case an SoC does not contain a completely filled memory map (which is very likely early on with us), a default subordinate must be implemented to provide a response when any of the non-existent address locations are accessed

• Non-sequential or sequential transfers: Respond error
• Idle or busy transfers: Zero-wait state okay response
• This functionality will be implemented as part of the decoder