AES-128 in UART

This project demonstrates secure communication using AES encryption over UART. It involves implementing the AES algorithm in Verilog, complemented by a CRC16 module for data validation, and an open-source UART core for serial data transmission. Data integrity is ensured by computing a CRC16 checksum for a 112-bit data block, appending it, and then encrypting the combined data. The encrypted data is converted from parallel to serial form, transmitted in 8-bit packets, received, converted back to parallel form, decrypted, and validated using the CRC16 checksum, ensuring secure and reliable data communication.

Tx State Machine

State	hold	EnTx	tx_start	PISO_reset	en_crc	PISO_load	EN_UDR	Next State
RESET	1	0	0	1	1	0	0	(start) ? LOAD : IDEL
LOAD	1	0	0	0	1	1	0	LoadByteToUDR
LoadByteToUDR	0	1	0	0	1	0	0	START_UART_Tx
START_UART_Tx	1	1	1	0	1	0	1	WAIT_DONE
WAIT_DONE	1	1	1	0	1	0	1	(Done) ? WAIT_UNDONE : WAIT_DONE
WAIT_UNDONE	1	1	0	0	1	0	1	(!Done) ? CHECK_EMPTY : WAIT_UNDONE
CHECK_EMPTY	1	0	0	0	1	0	0	PISO_empty ? IDEL : LoadByteToUDR
IDEL	1	0	0	1	1	0	0	start ? LOAD : IDEL
default	-	-	-	-	-	-	-	RESET

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Complete Tx Core

Rx State Machine

State	Wr	EnRx	En_valadation	SIPO_reset	EnDec	Next State
START_RX	0	1	1	0	0	(Done) ? SIPO_WRITE : START_RX
SIPO_WRITE	1	1	1	0	0	(full) ? EN_COMB : WAIT_UNDONE
WAIT_UNDONE	0	1	1	0	0	(!Done) ? START_RX : WAIT_UNDONE
EN_COMB	0	0	1	0	1	IDEL
IDEL	0	0	1	0	1	(!tx_out) ? START_RX : IDEL
default	-	-	-	-	-	IDEL

Complete Rx Core

Source Files

• AES_in_UART/TOP_Tx.v: transmitter top-level core
• AES_in_UART/TOP_Rx.v: receiver top-level core
• AES_in_UART/core.v : test module to test the whole system

Results

source

References

TimRudy's UART Core
Gourav Saini's Medium Article
AES Encryption Wikipedia Article
Publication by M. RAMAKRISHNA and JAGAN MOHAN RAO
Ben Eater's CRC16 Hardware Implementation