- Cscc::_discrete_restriction< T > | |
- Cscc::_max_excl_restriction< T > | |
- Cscc::_max_restriction< T > | |
- Cscc::_min_excl_restriction< T > | |
- Cscc::_min_max_excl_restriction< T > | |
- Cscc::_min_max_restriction< T > | |
- Cscc::_min_restriction< T > | |
- ►Cscc::abstract_bitfield< datatype_t > | Abstract baseclass for bitfield |
- Cscc::bitfield< datatype_t > | |
- Caxi::ac_ace< CFG, TYPES > | Snoop address(AC) channel signals |
- ►Caxi::ac_ace< CFG, CFG::master_types > | |
+ ►Cscc::abstract_bitfield< datatype_t > | Abstract baseclass for bitfield |
+ Cscc::bitfield< datatype_t > | |
+ Caxi::ac_ace< CFG, TYPES > | Snoop address(AC) channel signals |
+ ►Caxi::ac_ace< CFG, CFG::master_types > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ ►Caxi::ac_ace< CFG, CFG::slave_types > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > | |
+ ►Caxi::ace_fw_transport_if | |
+ ►Caxi::lwtr::ace_lwtr< axi::axi_protocol_types > | |
+ Caxi::lwtr::ace_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::scv::ace_recorder< axi::axi_protocol_types > | |
+ Caxi::lwtr::ace_lwtr< TYPES > | The TLM2 transaction recorder |
+ ►Caxi::pe::ace_target_pe | |
+ Caxi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::scv::ace_recorder< TYPES > | The TLM2 transaction recorder |
+ Caxi::scv::impl::ace_recording_types< TYPES > | |
+ Cscc::addr_range | Struct representing address range |
+ ►Caxi::ar_ace< CFG, TYPES > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ ►Caxi::ar_ace< CFG, CFG::master_types > | |
Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::ac_ace< CFG, CFG::slave_types > | |
+ ►Caxi::ar_ace< CFG, CFG::slave_types > | |
Caxi::pin::ace_target< CFG > | |
- Caxi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > | |
- ►Caxi::ace_fw_transport_if | |
- ►Caxi::lwtr::ace_lwtr< axi::axi_protocol_types > | |
- Caxi::lwtr::ace_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Caxi::scv::ace_recorder< axi::axi_protocol_types > | |
- Caxi::lwtr::ace_lwtr< TYPES > | The TLM2 transaction recorder |
- ►Caxi::pe::ace_target_pe | |
- Caxi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pin::ace_initiator< CFG > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::scv::ace_recorder< TYPES > | The TLM2 transaction recorder |
- Caxi::scv::impl::ace_recording_types< TYPES > | |
- Cscc::addr_range | Struct representing address range |
- ►Caxi::ar_ace< CFG, TYPES > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- ►Caxi::ar_ace< CFG, CFG::master_types > | |
- Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::ar_ace< CFG, CFG::slave_types > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::ar_axi< CFG, TYPES > | |
- ►Caxi::ar_axi< CFG, CFG::master_types > | |
- Caxi::pin::axi4_initiator< CFG > | |
- ►Caxi::ar_axi< CFG, CFG::slave_types > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::ar_axi_lite< CFG, TYPES > | Read address channel signals |
- Cscv_tr::AttrDesc | |
- ►Caxi::aw_ace< CFG, TYPES > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- ►Caxi::aw_ace< CFG, CFG::master_types > | |
- Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::aw_ace< CFG, CFG::slave_types > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::aw_axi< CFG, TYPES > | |
- ►Caxi::aw_axi< CFG, CFG::master_types > | |
- Caxi::pin::axi4_initiator< CFG > | |
- ►Caxi::aw_axi< CFG, CFG::slave_types > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::aw_axi_lite< CFG, TYPES > | Write address channel signals |
- Caxi::axi4_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH > | |
- Caxi::axi4_lite_cfg< BUSWDTH, ADDRWDTH > | |
- ►Caxi::axi_bw_transport_if | |
- Caxi::lwtr::axi_lwtr< TYPES > | The TLM2 transaction recorder |
- Caxi::pe::ace_target_pe | |
- Caxi::pe::simple_axi_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pin::ace_lite_target< CFG > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::scv::axi_recorder< TYPES > | The TLM2 transaction recorder |
- ►Caxi::axi_fw_transport_if | |
- ►Caxi::lwtr::axi_lwtr< axi::axi_protocol_types > | |
- Caxi::lwtr::axi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Caxi::scv::axi_recorder< axi::axi_protocol_types > | |
- Caxi::lwtr::axi_lwtr< TYPES > | The TLM2 transaction recorder |
- ►Caxi::pe::axi_target_pe | |
- Caxi::pe::simple_target< 32 > | |
- Caxi::pe::simple_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pin::axi4_initiator< CFG > | |
- Caxi::scv::axi_recorder< TYPES > | The TLM2 transaction recorder |
- Caxi::axi_protocol_types | The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicated protocol traits class has to be defined |
- ►Caxi::b_axi< CFG, TYPES > | |
- Caxi::pin::ace_initiator< CFG > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- Caxi::pin::ace_target< CFG > | |
- ►Caxi::b_axi< CFG, CFG::master_types > | |
- Caxi::pin::axi4_initiator< CFG > | |
- ►Caxi::b_axi< CFG, CFG::slave_types > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::b_axi_lite< CFG, TYPES > | Write response channel signals |
- ►Caxi::fsm::base | Base class of all AXITLM based adapters and interfaces |
- Caxi::pe::ace_target_pe | |
- Caxi::pe::axi_target_pe | |
- ►Caxi::pe::simple_initiator_b | |
- Caxi::pe::simple_axi_initiator< 32 > | |
- Caxi::pe::simple_ace_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::simple_axi_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pin::ace_initiator< CFG > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::pin::axi4_initiator< CFG > | |
- Caxi::pin::axi4_target< CFG > | |
- ►CBASE | |
- Caxi::scv::axitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
- Cchi::scv::chitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
- Cscc::ticking_clock< BASE > | |
- Cscc::tickless_clock< BASE > | |
- ►Cbase_type | |
- Ctlm::scc::tagged_target_mixin< base_type, TYPES > | |
- ►CBASE_TYPE | |
- Ctlm::scc::initiator_mixin< BASE_TYPE, TYPES > | Initiator socket mixin |
- Ctlm::scc::signal_initiator_mixin< BASE_TYPE > | |
- Ctlm::scc::signal_target_mixin< BASE_TYPE > | |
- Ctlm::scc::tagged_initiator_mixin< BASE_TYPE, TYPES > | |
- Ctlm::scc::target_mixin< BASE_TYPE, TYPES > | |
- Cutil::BitFieldArray< T, BaseOffset, BitsPerItem, NumItems > | Array of bit field elements |
- Cutil::BitFieldMember< T, Offset, Bits > | Bit field element |
- ►CCATEGORY | |
- Clogging::Output2FILE< CATEGORY > | |
- ►Ccci::cci_param | |
- Cscc::cci_param_restricted< T, TM > | Extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter |
- Caxi::cd_ace< CFG, TYPES > | Snoop data(cd) channel signals |
- ►Caxi::cd_ace< CFG, CFG::master_types > | |
- Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::cd_ace< CFG, CFG::slave_types > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::checker::checker_if< TYPES > | |
- ►Caxi::checker::checker_if< axi::axi_protocol_types > | |
- Caxi::checker::ace_protocol | |
- Caxi::checker::axi_protocol | |
- ►Cchi::chi_fw_transport_if | |
- ►Cchi::lwtr::chi_lwtr< chi::chi_protocol_types > | |
- Cchi::lwtr::chi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Cchi::lwtr::chi_lwtr< TYPES > | The TLM2 transaction recorder |
- Cchi::scv::chi_trx_recorder< TYPES > | The TLM2 transaction recorder |
- Cchi::chi_protocol_types | The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicated protocol traits class has to be defined |
- Cchi::scv::impl::chi_recording_types< TYPES > | |
- ►Caxi::common | |
- ►Caxi::axi_extension< axi4 > | |
- Caxi::axi4_extension | |
- ►Caxi::axi_extension< axi3 > | |
- Caxi::axi3_extension | |
- ►Caxi::axi_extension< ace, ace_response > | |
- Caxi::ace_extension | |
- Caxi::axi_extension< REQ, RESP > | |
- Cchi::common | |
- Cscc::configurer::ConfigHolder | |
- ►Ccci_utils::consuming_broker | |
- Cscc::cci_broker | |
- Caxi::cr_ace< CFG, TYPES > | Snoop response(cr) channel signals |
- ►Caxi::cr_ace< CFG, CFG::master_types > | |
- Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::cr_ace< CFG, CFG::slave_types > | |
- Caxi::pin::ace_target< CFG > | |
- Cscc::sc_variable< T >::creator | |
- Cscc::sc_variable< bool >::creator | |
- ►Cchi::credit | |
- Cchi::chi_credit_extension | |
- Cchi::data | |
- Clogging::DEFAULT | Default logging category |
- Cutil::delegate< T > | |
- Cutil::delegate< bool(const scc::impl::sc_register &, DATATYPE &, sc_core::sc_time &)> | |
- Cutil::delegate< bool(scc::impl::sc_register &, DATATYPE &, sc_core::sc_time &)> | |
- Cutil::delegate< R(A...)> | Fast alternative to std::function |
- Cutil::BitFieldArray< T, BaseOffset, BitsPerItem, NumItems >::Element | |
- Cahb::enable_for_enum< Enum > | |
- Caxi::enable_for_enum< Enum > | |
- Cchi::enable_for_enum< Enum > | |
- Caxi::enable_for_enum< bar_e > | |
- Caxi::enable_for_enum< burst_e > | |
- Cchi::enable_for_enum< dat_optype_e > | |
- Cchi::enable_for_enum< dat_resptype_e > | |
- Caxi::enable_for_enum< domain_e > | |
- Caxi::enable_for_enum< lock_e > | |
- Cchi::enable_for_enum< req_optype_e > | |
- Caxi::enable_for_enum< resp_e > | |
- Cchi::enable_for_enum< rsp_optype_e > | |
- Cchi::enable_for_enum< rsp_resperrtype_e > | |
- Cchi::enable_for_enum< rsp_resptype_e > | |
- Caxi::enable_for_enum< snoop_e > | |
- Cchi::enable_for_enum< snp_optype_e > | |
- ►Cboost::statechart::event | |
- Caxi::fsm::AckRecv | |
- Caxi::fsm::BegPartReq | |
- Caxi::fsm::BegPartResp | |
- Caxi::fsm::BegReq | |
- Caxi::fsm::BegResp | |
- Caxi::fsm::EndPartReq | |
- Caxi::fsm::EndPartResp | |
- Caxi::fsm::EndReq | |
- Caxi::fsm::EndResp | |
- Caxi::fsm::EndRespNoAck | |
- Caxi::fsm::WReq | |
- ►CEXT | |
- Ctlm::scc::tlm_ext_mm< EXT > | |
- Cscc::ForLoop< SIZE > | |
- Cscc::ForLoop< 1 > | |
- Caxi::fsm::fsm_handle | |
- ►Cscc::trace::fst_trace | |
- Cscc::trace::fst_trace_enum | |
- Cscc::trace::fst_trace_t< T, OT > | |
- Cscc::trace::gz_writer | |
- Cstd::hash< util::delegate< R(A...)> > | Hash overload for delegate<T, A...> |
- Cscc::impl::helper< T, bool > | |
- Cscc::impl::helper< T, false > | |
- Cscc::impl::helper< T, true > | |
- ►Cscc::indexed_resource_access_if | Interface defining access to an indexed resource e.g. register file |
- Cscc::sc_register_indexed< DATATYPE, SIZE, START > | |
- Cinitiator | Initiator ID recording TLM extension |
- Cutil::IoRedirector | Allows to capture the strings written to std::cout and std::cerr (MT-safe) |
- Caxi::lite_master_types | |
- Caxi::lite_slave_types | |
- Cscc::ordered_semaphore::lock | Lock for the semaphore |
- Clogging::Log< T > | |
- Cscc::LogConfig | Configuration class for the logging setup |
- Cutil::range_lut< T >::lut_entry | Lut entry |
- Ctlm::scc::lwtr::lwtr4tlm2_extension_registry< TYPES > | The TLM transaction extensions recorder registry |
- Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< TYPES > | The TLM transaction extensions recorder interface |
- ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< axi_protocol_types > | |
- Caxi::lwtr::ace_ext_recording | |
- Caxi::lwtr::axi3_ext_recording | |
- Caxi::lwtr::axi4_ext_recording | |
- Caxi::lwtr::tlm_id_ext_recording | |
- ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< chi_protocol_types > | |
- Cchi::lwtr::chi_ctrl_ext_recording | |
- Cchi::lwtr::chi_data_ext_recording | |
- Cchi::lwtr::chi_link_ext_recording | |
- Cchi::lwtr::chi_snp_ext_recording | |
- Cchi::lwtr::tlm_id_ext_recording | |
- ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< tlm::tlm_base_protocol_types > | |
- Ctlm::scc::lwtr::tlm_id_ext_recording | |
- Caxi::master_types | |
- Cscc::MT19937 | Mersenne-twister based random number generator |
- Cutil::MT19937 | Mersenne-Twister pseudo random number generator |
- ►Ctlm::scc::lwtr::nb_rec_entry | |
- Caxi::lwtr::nb_ace_rec_entry | |
- Cchi::lwtr::nb_chi_rec_entry | |
- Cscc::observer::notification_handle | A handle to be used be the observed object to notify the observer about a change |
- ►Cscc::observer | The interface defining an observer |
- Cscc::fst_trace_file | |
- Cscc::vcd_mt_trace_file | |
- Cscc::vcd_push_trace_file | |
- CPath | Path recording TLM extension |
- Ctlm::scc::tlm_managed_extension< T >::pool | |
- Cutil::pool_allocator< ELEM_SIZE, CHUNK_SIZE > | Generic pool allocator singleton not being MT-safe |
- Cutil::pool_allocator< sizeof(payload_type)> | |
- Caxi::pe::tx_reorderer::que_entry | |
- Cscc::router< BUSWIDTH >::range_entry | |
- Cutil::range_lut< T > | Range based lookup table |
- Cutil::range_lut< std::pair< scc::resource_access_if *, uint64_t > > | |
- Cutil::range_lut< unsigned > | |
- Cutil::stl_pool_allocator< T >::rebind< U > | |
- ►CREQ | |
- Caxi::axi_extension< REQ, RESP > | |
- ►Caxi::request | |
- ►Caxi::axi3 | |
- Caxi::axi_extension< axi3 > | |
- ►Caxi::axi4 | |
- Caxi::axi_extension< axi4 > | |
- ►Caxi::ace | |
- Caxi::axi_extension< ace, ace_response > | |
- Cchi::request | |
- ►Cscc::resetable | Base class for components having a reset |
- Cscc::tlm_target_bfs_register_base< derived_t, use_URID > | |
- ►Cscc::resource_access_if | Interface defining access to a resource e.g. a register |
- Cscc::bitfield_register< datatype_t > | Register that can contain bitfields |
- ►Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
- Cscc::sc_register_masked< DATATYPE, WRMASK, RDMASK > | |
- ►Caxi::response | |
- Caxi::axi_extension< axi4 > | |
- Caxi::axi_extension< axi3 > | |
- ►Caxi::ace_response | |
- Caxi::axi_extension< ace, ace_response > | |
- Caxi::axi_extension< REQ, RESP > | |
- Cchi::response | |
- Caxi::rresp_ace< CFG, TYPES > | |
- ►Caxi::rresp_ace< CFG, CFG::master_types > | |
- Caxi::pin::ace_initiator< CFG > | |
- ►Caxi::rresp_ace< CFG, CFG::slave_types > | |
- Caxi::pin::ace_target< CFG > | |
- ►Caxi::rresp_axi< CFG, TYPES > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- ►Caxi::rresp_axi< CFG, CFG::master_types > | |
- Caxi::pin::axi4_initiator< CFG > | |
- ►Caxi::rresp_axi< CFG, CFG::slave_types > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::rresp_axi_lite< CFG, TYPES > | Read data channel signals |
- ►Cruntime_error | |
- Cscv_tr::SQLiteDB::SQLiteException | |
- ►Csc_core::sc_attribute | |
- Cscc::sc_attribute_randomized< int > | |
- Cscc::ext_attribute< T > | Extended sc_attribute |
- Cscc::sc_attribute_randomized< T > | |
- Cscc::sc_bigint_tester< size > | |
- Cscc::sc_biguint_tester< size > | |
- Cscc::sc_bv_tester< size > | |
- ►Csc_core::sc_clock | |
- Cscc::sc_clock_ext | A clock source with construction time configurable start delay |
- Cscc::sc_int_tester< size > | |
- ►Csc_core::sc_interface | |
- ►Caxi::bw_blocking_transport_if< TYPES::tlm_payload_type > | |
- ►Caxi::ace_bw_transport_if< axi::axi_protocol_types > | |
- Caxi::lwtr::ace_lwtr< axi::axi_protocol_types > | |
- Caxi::scv::ace_recorder< axi::axi_protocol_types > | |
- Caxi::lwtr::ace_lwtr< TYPES > | The TLM2 transaction recorder |
- ►Caxi::pe::axi_initiator_b | |
- Caxi::pe::ace_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::ace_lite_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::axi_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::simple_ace_initiator< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::scv::ace_recorder< TYPES > | The TLM2 transaction recorder |
- Caxi::ace_bw_transport_if< TYPES > | |
- ►Ctlm::scc::pe::intor_bw< type::NB > | |
- ►Ctlm::scc::pe::intor_bw_nb | |
- Caxi::pe::ace_target_pe::bw_intor_impl | |
- Caxi::pe::axi_target_pe::bw_intor_impl | |
- ►Ctlm::scc::pe::intor_bw< type::BL > | |
- Ctlm::scc::pe::intor_bw_b | |
- ►Ctlm::scc::pe::intor_fw< type::NB > | |
- ►Ctlm::scc::pe::intor_fw_nb | |
- Caxi::pe::rate_limiting_buffer | |
- Caxi::pe::tx_reorderer | |
- Ctlm::scc::pe::parallel_pe | |
- ►Ctlm::scc::pe::intor_fw< type::BL > | |
- ►Ctlm::scc::pe::intor_fw_b | |
- Caxi::pe::axi_initiator_b | |
- Caxi::pe::simple_initiator_b | |
- ►Cchi::pe::chi_rn_initiator_b | |
- Cchi::pe::chi_rn_initiator< BUSWIDTH, TYPES, N, POL > | |
- ►Ctlm::scc::tlm_signal_bw_transport_if< bool, tlm_signal_baseprotocol_types< bool > > | |
- Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
- ►Ctlm::scc::tlm_signal_bw_transport_if< TYPE, tlm_signal_baseprotocol_types< TYPE > > | |
- Ctlm::scc::sc_signal2tlm_signal< TYPE > | |
- ►Ctlm::scc::tlm_signal_fw_transport_if< bool, tlm_signal_baseprotocol_types< bool > > | |
- Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
- ►Ctlm::scc::tlm_signal_fw_transport_if< TYPE, tlm_signal_baseprotocol_types< TYPE > > | |
- Ctlm::scc::tlm_signal2sc_signal< TYPE > | |
- Caxi::bw_blocking_transport_if< TRANS > | |
- ►Cchi::bw_blocking_transport_if< TRANS > | |
- ►Cchi::chi_bw_transport_if< chi::chi_protocol_types > | |
- Cchi::lwtr::chi_lwtr< chi::chi_protocol_types > | |
- Cchi::lwtr::chi_lwtr< TYPES > | The TLM2 transaction recorder |
- Cchi::pe::chi_rn_initiator_b | |
- Cchi::scv::chi_trx_recorder< TYPES > | The TLM2 transaction recorder |
- Cchi::chi_bw_transport_if< TYPES > | |
- Ctlm::scc::pe::intor_bw< TYPE > | |
- Ctlm::scc::pe::intor_fw< TYPE > | |
- Ctlm::scc::tlm_signal_bw_transport_if< SIG, TYPES > | |
- Ctlm::scc::tlm_signal_fw_transport_if< SIG, TYPES > | |
- Cscc::dt::sc_logic_7 | |
- Cscc::sc_lv_tester< size > | |
- ►Csc_core::sc_module | |
- ►Cahb::pe::ahb_initiator_b | |
- Cahb::pe::ahb3_initiator< BUSWIDTH, TYPES, N, POL > | |
- ►Cahb::pe::ahb_target_b | |
- Cahb::pe::ahb3_target< BUSWIDTH, TYPES, N, POL > | |
- Cahb::pin::initiator< WIDTH > | |
- Cahb::pin::target< DWIDTH, AWIDTH > | |
- ►Capb::pe::apb_initiator_b | |
- Capb::pe::apb_initiator< BUSWIDTH, TYPES, N, POL > | |
- ►Capb::pe::apb_target_b | |
- Capb::pe::apb_target< BUSWIDTH, TYPES, N, POL > | |
- ►Caxi::axi_initiator_base | Axi_initiator class provides an input_socket for incoming TLM transactions. It attaches AXI extension to the tlm_generic_payload and forwards it to the AXI Protocol Engine |
- Caxi::axi_initiator< BUSWIDTH > | |
- ►Caxi::axi_target_base | Axi_target class instantiates the AXI Protocol Engine. It accesses the Protocol Engine with access() callback function and forwards the transactions via the output_socket |
- Caxi::axi_target< BUSWIDTH > | |
- Caxi::lwtr::ace_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Caxi::lwtr::axi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::ace_target_pe | |
- Caxi::pe::axi_initiator_b | |
- Caxi::pe::axi_target_pe | |
- Caxi::pe::ordered_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::rate_limiting_buffer | |
- Caxi::pe::reordering_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::simple_initiator_b | |
- Caxi::pe::tx_reorderer | |
- Caxi::pin::ace_initiator< CFG > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- Caxi::pin::ace_target< CFG > | |
- Caxi::pin::axi4_initiator< CFG > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::scv::axitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
- Cchi::lwtr::chi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Cchi::pe::chi_rn_initiator_b | |
- Cchi::scv::chitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
- Cobi::pin::target< DATA_WIDTH, ADDR_WIDTH, ID_WIDTH, USER_WIDTH > | |
- Cscc::configurer | Design configuration reader |
- Cscc::hierarchy_dumper | |
- Cscc::memory< SIZE, BUSWIDTH > | Simple TLM2.0 LT memory model |
- Cscc::perf_estimator | Performance estimator |
- Cscc::router< BUSWIDTH > | TLM2.0 router for loosly-timed (LT) models |
- Cscc::tick2time | |
- Cscc::time2tick | Translate a tick-less clock (sc_time based) to boolean clock |
- Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
- Cscc::tlm_target_mod< BUSWIDTH, ADDR_UNIT_WIDTH > | |
- ►Cscc::tracer_base | Base class for automatic tracer |
- ►Cscc::tracer | Component traversing the SystemC object hierarchy and tracing the objects |
- Cscc::configurable_tracer | Configurable tracer for automatic port and signal tracing |
- Cscc::value_registry | |
- Ctlm::scc::lwtr::tlm2_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Ctlm::scc::pe::parallel_pe | |
- Ctlm::scc::sc_signal2tlm_signal< TYPE > | |
- Ctlm::scc::scv::tlm_recorder_module< BUSWIDTH, TYPES > | The TLM2 transaction recorder |
- Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
- Ctlm::scc::tlm_signal2sc_signal< TYPE > | |
- ►Csc_core::sc_object | |
- Cscc::peq< tlm::scc::tlm_gp_shared_ptr > | |
- Cscc::peq< aw_data > | |
- Cscc::peq< std::tuple< axi::fsm::protocol_time_point_e, tlm::scc::tlm_gp_shared_ptr, bool > > | |
- Cscc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > | |
- Cscc::peq< tlm::tlm_generic_payload * > | |
- Cscc::peq< chi::lwtr::nb_chi_rec_entry > | |
- Cscc::peq< std::tuple< uint8_t, axi::fsm::fsm_handle * > > | |
- Cscc::peq< tlm_signal_type > | |
- Cscc::peq< std::function< void(void)> > | |
- Cscc::peq< axi::lwtr::nb_ace_rec_entry > | |
- Cscc::peq< tlm::scc::lwtr::nb_rec_entry > | |
- Cscc::peq< std::tuple< payload_type *, tlm::tlm_phase > > | |
- Cscc::bitfield_register< datatype_t > | Register that can contain bitfields |
- Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
- ►Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
- Cscc::ordered_semaphore_t< 1 > | |
- Cscc::ordered_semaphore_t< CAPACITY > | |
- Cscc::peq< TYPE > | Priority event queue |
- Cscc::sc_thread_pool | |
- ►Cscc::sc_variable_b | |
- Cscc::sc_variable< unsigned > | |
- Cscc::sc_ref_variable< T > | Sc_ref_variable for a particular plain data type. This marks an existing C++ variable as discoverable via the sc_object tree. Whenever possible sc_variable should be used as this does not support value change callback |
- Cscc::sc_ref_variable< sc_core::sc_event > | |
- Cscc::sc_ref_variable_masked< T > | Sc_variable for a particular plain data type with limited bit width |
- Cscc::sc_variable< T > | SystemC variable |
- Cscc::sc_variable< bool > | |
- Cscc::tlm_target_bfs_register_base< derived_t, use_URID > | |
- ►Csc_core::sc_port | |
- Cscc::sc_in_opt< sc_core::sc_time > | |
- Cscc::sc_in_opt< sc_dt::sc_uint< 0 > > | |
- Cscc::sc_in_opt< T > | |
- Cscc::sc_in_opt< bool > | |
- Cscc::sc_in_opt< sc_dt::sc_logic > | |
- ►Cscc::sc_inout_opt< T > | |
- Cscc::sc_out_opt< sc_dt::sc_uint< 0 > > | |
- Cscc::sc_out_opt< T > | |
- Cscc::sc_inout_opt< bool > | |
- Cscc::sc_inout_opt< sc_dt::sc_logic > | |
- ►Csc_core::sc_prim_channel | |
- Cscc::fifo_w_cb< tlm::tlm_generic_payload * > | |
- Cscc::fifo_w_cb< std::tuple< payload_type *, unsigned > > | |
- Cscc::fifo_w_cb< std::tuple< tlm::tlm_generic_payload *, unsigned > > | |
- Cscc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > | |
- Cscc::fifo_w_cb< T > | Fifo with callbacks |
- ►Csc_core::sc_semaphore_if | |
- Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
- ►Csc_core::sc_signal | |
- Cscc::sc_owning_signal< T, POL > | Sc_signal which takes ownership of the data (acquire()/release()) |
- ►Csc_core::sc_signal_in_if | |
- Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
- ►Csc_core::sc_trace_file | |
- Cscc::fst_trace_file | |
- Cscc::vcd_mt_trace_file | |
- Cscc::vcd_pull_trace_file | |
- Cscc::vcd_push_trace_file | |
- ►Csc_trace_file | |
- Cscc::value_registry_impl | |
- Cscc::sc_uint_tester< size > | |
- Cscc::sc_variable_vector< T > | |
- Cscc::ScLogger< SEVERITY > | Logger class |
- ►Cscv_enum_base | |
- Cscv_tr::scv_extensions< tlm::scc::scv::tlm_phase_enum > | |
- Cscv_tr::scv_extensions< tlm::tlm_command > | |
- Cscv_tr::scv_extensions< tlm::tlm_dmi::dmi_access_e > | |
- Cscv_tr::scv_extensions< tlm::tlm_gp_option > | |
- Cscv_tr::scv_extensions< tlm::tlm_response_status > | |
- Cscv_tr::scv_extensions< tlm::tlm_sync_enum > | |
- ►Cscv_extensions_base | |
- Cscv_tr::scv_extensions< tlm::scc::scv::tlm_dmi_data > | |
- Cscv_tr::scv_extensions< tlm::scc::scv::tlm_gp_data > | |
- Caxi::select_if< Cond, T, S > | |
- Caxi::select_if< true, T, S > | |
- Caxi::signal_types | |
- ►Cboost::statechart::simple_state | |
- Caxi::fsm::ReadIdle | Phase between 2 read burst response beats |
- Caxi::fsm::WriteIdle | Phase between 2 burst beats, should keep the link locked |
- Caxi::slave_types | |
- Cchi::snp_request | |
- Cscc::tlm_target_bfs< regs_t, owner_t >::socket_accessor | |
- Cutil::sparse_array< T, SIZE, PAGE_ADDR_BITS > | Sparse array suitable for large sizes |
- Cutil::sparse_array< uint8_t, SIZE > | |
- Cscv_tr::SQLiteDB | |
- ►Cboost::statechart::state | |
- Caxi::fsm::ATrans | Special state to map AWREADY/WDATA of SNPS to AXI protocol |
- Caxi::fsm::Idle | Idle state |
- Caxi::fsm::PartialRequest | Burst beat |
- Caxi::fsm::PartialResponse | Beat of a burst response |
- Caxi::fsm::Request | Request, either the last beat of a write or the address phase of a read |
- Caxi::fsm::Response | Write response or the last read response (beat) |
- Caxi::fsm::WaitAck | Waiting for ack in case of ACE access |
- Caxi::fsm::WaitForResponse | Operation state where the target can do it's stuff |
- ►Cboost::statechart::state_machine | |
- Caxi::fsm::AxiProtocolFsm | |
- Cutil::stl_pool_allocator< T > | |
- ►Cstd::streambuf | |
- Cutil::lz4c_steambuf | |
- Cutil::lz4d_streambuf | |
- ►Cstd::stringbuf | |
- Cscc::stream_redirection | Stream redirector |
- ►Caxi::pe::target_info_if | |
- Caxi::pe::simple_target< 32 > | |
- Caxi::pe::ordered_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::reordering_target< BUSWIDTH, TYPES, N, POL > | |
- Caxi::pe::simple_target< BUSWIDTH, TYPES, N, POL > | |
- Cscc::target_memory_map_entry< BUSWIDTH > | |
- Cscc::target_name_map_entry< BUSWIDTH > | |
- Cutil::thread_pool | Simple thread pool |
- Cutil::thread_syncronizer | Executes a function syncronized in another thread |
- ►Ctlm::tlm_base_initiator_socket | |
- ►Caxi::ace_initiator_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Caxi::scv::ace_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Caxi::ace_initiator_socket< CFG::BUSWIDTH > | |
- Caxi::axi_initiator_socket< 64 > | |
- Caxi::axi_initiator_socket< 32 > | |
- ►Caxi::axi_initiator_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Caxi::scv::axi_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Caxi::axi_initiator_socket< CFG::BUSWIDTH > | |
- Cchi::chi_initiator_socket< 32, chi::chi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Ctlm::scc::tlm_signal_initiator_socket< tlm_signal_type, protocol_types, 32 > | |
- Ctlm::scc::tlm_signal_initiator_socket< TYPE > | |
- Caxi::ace_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Caxi::axi_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Cchi::chi_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Ctlm::scc::tlm_signal_initiator_socket< SIG, TYPES, N, POL > | |
- ►Ctlm::scc::tlm_base_mm_interface | |
- Ctlm::scc::tlm_signal_gp< SIG >::gp_mm | |
- ►Ctlm::tlm_base_target_socket | |
- Caxi::ace_target_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Caxi::ace_target_socket< CFG::BUSWIDTH > | |
- Caxi::axi_target_socket< 32 > | |
- ►Caxi::axi_target_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Caxi::scv::axi_rec_target_socket< BUSWIDTH, TYPES, N, POL > | |
- Caxi::axi_target_socket< CFG::BUSWIDTH > | |
- Cchi::chi_target_socket< 32, chi::chi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
- Ctlm::scc::tlm_signal_target_socket< tlm_signal_type, protocol_types, 32 > | |
- Ctlm::scc::tlm_signal_target_socket< TYPE > | |
- Caxi::ace_target_socket< BUSWIDTH, TYPES, N, POL > | |
- Caxi::axi_target_socket< BUSWIDTH, TYPES, N, POL > | |
- Cchi::chi_target_socket< BUSWIDTH, TYPES, N, POL > | |
- Ctlm::scc::tlm_signal_target_socket< SIG, TYPES, N, POL > | |
- ►Ctlm::tlm_bw_transport_if | |
- Caxi::ace_bw_transport_if< axi::axi_protocol_types > | |
- Caxi::lwtr::axi_lwtr< axi::axi_protocol_types > | |
- Caxi::pe::simple_axi_initiator< 32 > | |
- Caxi::scv::axi_recorder< axi::axi_protocol_types > | |
- Cchi::chi_bw_transport_if< chi::chi_protocol_types > | |
- ►Ctlm::scc::lwtr::tlm2_lwtr< tlm::tlm_base_protocol_types > | |
- Ctlm::scc::lwtr::tlm2_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
- Ctlm::scc::scv::tlm_recorder< tlm::tlm_base_protocol_types > | |
- Cahb::pe::ahb_initiator_b | |
- Capb::pe::apb_initiator_b | |
- Caxi::ace_bw_transport_if< TYPES > | |
- Cchi::chi_bw_transport_if< TYPES > | |
- Ctlm::scc::lwtr::tlm2_lwtr< TYPES > | The TLM2 transaction recorder |
- Ctlm::scc::scv::tlm_recorder< TYPES > | The TLM2 transaction recorder |
- Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- Ctlm::scc::scv::tlm_dmi_data | |
- ►Ctlm::tlm_extension | |
- Cahb::ahb_extension | |
- Caxi::ace_extension | |
- Caxi::axi3_extension | |
- Caxi::axi4_extension | |
- Cchi::chi_credit_extension | |
- Cchi::chi_ctrl_extension | |
- Cchi::chi_data_extension | |
- Cchi::chi_snp_extension | |
- Cobi::obi_extension | |
- Cscp::tlm_extensions::initiator_id | |
- Cscp::tlm_extensions::path_trace | |
- Ctlm::scc::data_buffer | |
- Ctlm::scc::lwtr::link_pred_ext | |
- Ctlm::scc::scv::tlm_recording_extension | Generic payload extension class holding the handle of the last recorded SCV transaction |
- ►Ctlm::scc::tlm_gp_mm | |
- Ctlm::scc::tlm_gp_mm_t< SZ, BE > | |
- Ctlm::scc::tlm_gp_mm_v | |
- Ctlm::scc::tlm_id_extension | |
- Ctlm::scc::tlm_unmanaged_extension< T > | |
- Ctlm::scc::scv::tlm_extension_recording_registry< TYPES > | The TLM transaction extensions recorder registry |
- Ctlm::scc::scv::tlm_extensions_recording_if< TYPES > | The TLM transaction extensions recorder interface |
- ►Ctlm::scc::scv::tlm_extensions_recording_if< axi_protocol_types > | |
- Caxi::scv::ace_ext_recording | |
- Caxi::scv::axi3_ext_recording | |
- Caxi::scv::axi4_ext_recording | |
- Caxi::scv::tlm_id_ext_recording | |
- ►Ctlm::scc::scv::tlm_extensions_recording_if< chi_protocol_types > | |
- Cchi::chi_credit_ext_recording | |
- Cchi::chi_ctrl_ext_recording | |
- Cchi::chi_data_ext_recording | |
- Cchi::chi_snp_ext_recording | |
- Cchi::tlm_id_ext_recording | |
- ►Ctlm::scc::scv::tlm_extensions_recording_if< tlm::tlm_base_protocol_types > | |
- Ctlm::scc::scv::tlm_id_ext_recording | |
- ►Ctlm::tlm_fw_transport_if | |
- Ctlm::scc::lwtr::tlm2_lwtr< tlm::tlm_base_protocol_types > | |
- Ctlm::scc::scv::tlm_recorder< tlm::tlm_base_protocol_types > | |
- Cahb::pe::ahb_target_b | |
- Capb::pe::apb_target_b | |
- Ctlm::scc::lwtr::tlm2_lwtr< TYPES > | The TLM2 transaction recorder |
- Ctlm::scc::scv::tlm_recorder< TYPES > | The TLM2 transaction recorder |
- Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
- ►Ctlm::scc::tlm_generic_payload_base | |
- Ctlm::scc::tlm_signal_gp< SIG > | |
- Ctlm::scc::scv::tlm_gp_data | |
- Ctlm::scc::tlm_gp_shared_ptr | |
- ►Ctlm::tlm_initiator_socket | |
- Ctlm::scc::initiator_mixin< tlm::tlm_initiator_socket< 0 > > | |
- ►Ctlm::scc::scv::tlm_rec_initiator_socket< 0 > | |
- Ctlm::scc::initiator_mixin< tlm::scc::scv::tlm_rec_initiator_socket< 0 > > | |
- Ctlm::scc::scv::tlm_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
- Ctlm::scc::tlm_managed_extension< T > | |
- ►Ctlm::tlm_mm_interface | |
- Ctlm::scc::tlm_mm< TYPES, CLEANUP_DATA > | Tlm memory manager |
- ►CTYPES::tlm_payload_type | |
- Caxi::scv::impl::ace_recording_payload< TYPES > | Class to hold the information to be recorded on the timed streams |
- Cchi::scv::impl::chi_recording_payload< TYPES > | Class to hold the information to be recorded on the timed streams |
- Ctlm::scc::scv::impl::tlm_recording_payload< TYPES > | |
- Ctlm::scc::scv::impl::tlm_recording_types< TYPES > | |
- Ctlm::scc::tlm_signal_baseprotocol_types< SIG > | |
- ►Cscc::tlm_target< BUSWIDTH, ADDR_UNIT_WIDTH > | Simple access-width based bus interface (no DMI support) |
- Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
- ►Cscc::tlm_target< LT, 8 > | |
- Cscc::tlm_target_mod< BUSWIDTH, ADDR_UNIT_WIDTH > | |
- ►Cscc::tlm_target_bfs_base< owner_t > | |
- Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
- Cscc::tlm_target_bfs_params | |
- ►Ctlm::tlm_target_socket | |
- ►Ctlm::scc::scv::tlm_rec_target_socket< LT > | |
- Ctlm::scc::target_mixin< tlm::scc::scv::tlm_rec_target_socket< LT > > | |
- Ctlm::scc::target_mixin< tlm::tlm_target_socket< LT > > | |
- Ctlm::scc::target_mixin< tlm::tlm_target_socket< WIDTH > > | |
- Ctlm::scc::scv::tlm_rec_target_socket< BUSWIDTH, TYPES, N, POL > | |
- ►Cscc::traceable | Interface defining a traceable component |
- Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
- Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
- Cscc::trace::traits< T > | |
- Cahb::pe::ahb_initiator_b::tx_state | |
- Caxi::pe::axi_initiator_b::tx_state | |
- Cchi::pe::chi_rn_initiator_b::tx_state | |
- Clwtr::value_converter< tlm::tlm_command > | |
- Clwtr::value_converter< tlm::tlm_dmi::dmi_access_e > | |
- Clwtr::value_converter< tlm::tlm_gp_option > | |
- Clwtr::value_converter< tlm::tlm_phase > | |
- Clwtr::value_converter< tlm::tlm_response_status > | |
- Clwtr::value_converter< tlm::tlm_sync_enum > | |
- Cscc::value_registry_if::value_holder | |
- Cscc::value_registry_if | |
- Cscc::trace::vcd_scope_stack< T > | |
- Cscc::trace::vcd_trace | |
- Cutil::watchdog | Watch dog based on https://github.com/didenko/TimeoutGuard |
- ►Caxi::wdata_axi< CFG, TYPES > | |
- Caxi::pin::ace_initiator< CFG > | |
- Caxi::pin::ace_lite_initiator< CFG > | |
- Caxi::pin::ace_lite_target< CFG > | |
- Caxi::pin::ace_target< CFG > | |
- ►Caxi::wdata_axi< CFG, CFG::master_types > | |
- Caxi::pin::axi4_initiator< CFG > | |
- ►Caxi::wdata_axi< CFG, CFG::slave_types > | |
- Caxi::pin::axi4_target< CFG > | |
- Caxi::wdata_axi_lite< CFG, TYPES > | Write data channel signals |
+ Caxi::ar_axi< CFG, TYPES > | |
+ ►Caxi::ar_axi< CFG, CFG::master_types > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ ►Caxi::ar_axi< CFG, CFG::slave_types > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::ar_axi_lite< CFG, TYPES > | Read address channel signals |
+ Cscv_tr::AttrDesc | |
+ ►Caxi::aw_ace< CFG, TYPES > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ ►Caxi::aw_ace< CFG, CFG::master_types > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ ►Caxi::aw_ace< CFG, CFG::slave_types > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::aw_axi< CFG, TYPES > | |
+ ►Caxi::aw_axi< CFG, CFG::master_types > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ ►Caxi::aw_axi< CFG, CFG::slave_types > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::aw_axi_lite< CFG, TYPES > | Write address channel signals |
+ Caxi::axi4_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH > | |
+ Caxi::axi4_lite_cfg< BUSWDTH, ADDRWDTH > | |
+ ►Caxi::axi_bw_transport_if | |
+ Caxi::lwtr::axi_lwtr< TYPES > | The TLM2 transaction recorder |
+ Caxi::pe::ace_target_pe | |
+ Caxi::pe::simple_axi_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::scv::axi_recorder< TYPES > | The TLM2 transaction recorder |
+ ►Caxi::axi_fw_transport_if | |
+ ►Caxi::lwtr::axi_lwtr< axi::axi_protocol_types > | |
+ Caxi::lwtr::axi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::scv::axi_recorder< axi::axi_protocol_types > | |
+ Caxi::lwtr::axi_lwtr< TYPES > | The TLM2 transaction recorder |
+ ►Caxi::pe::axi_target_pe | |
+ Caxi::pe::simple_target< 32 > | |
+ Caxi::pe::simple_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ Caxi::scv::axi_recorder< TYPES > | The TLM2 transaction recorder |
+ Caxi::axi_protocol_types | The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicated protocol traits class has to be defined |
+ ►Caxi::b_axi< CFG, TYPES > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ Caxi::pin::ace_target< CFG > | |
+ ►Caxi::b_axi< CFG, CFG::master_types > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ ►Caxi::b_axi< CFG, CFG::slave_types > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::b_axi_lite< CFG, TYPES > | Write response channel signals |
+ ►Caxi::fsm::base | Base class of all AXITLM based adapters and interfaces |
+ Caxi::pe::ace_target_pe | |
+ Caxi::pe::axi_target_pe | |
+ ►Caxi::pe::simple_initiator_b | |
+ Caxi::pe::simple_axi_initiator< 32 > | |
+ Caxi::pe::simple_ace_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::simple_axi_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ Caxi::pin::axi4_target< CFG > | |
+ ►CBASE | |
+ Caxi::scv::axitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
+ Cchi::scv::chitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
+ Cscc::ticking_clock< BASE > | |
+ Cscc::tickless_clock< BASE > | |
+ ►CBASE_TYPE | |
+ Ctlm::scc::initiator_mixin< BASE_TYPE, TYPES > | Initiator socket mixin |
+ Ctlm::scc::signal_initiator_mixin< BASE_TYPE > | |
+ Ctlm::scc::signal_target_mixin< BASE_TYPE > | |
+ Ctlm::scc::tagged_initiator_mixin< BASE_TYPE, TYPES > | |
+ Ctlm::scc::target_mixin< BASE_TYPE, TYPES > | |
+ ►Cbase_type | |
+ Ctlm::scc::tagged_target_mixin< base_type, TYPES > | |
+ Cutil::BitFieldArray< T, BaseOffset, BitsPerItem, NumItems > | Array of bit field elements |
+ Cutil::BitFieldMember< T, Offset, Bits > | Bit field element |
+ ►CCATEGORY | |
+ Clogging::Output2FILE< CATEGORY > | |
+ ►Ccci::cci_param | |
+ Cscc::cci_param_restricted< T, TM > | Extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter |
+ Caxi::cd_ace< CFG, TYPES > | Snoop data(cd) channel signals |
+ ►Caxi::cd_ace< CFG, CFG::master_types > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ ►Caxi::cd_ace< CFG, CFG::slave_types > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::checker::checker_if< TYPES > | |
+ ►Caxi::checker::checker_if< axi::axi_protocol_types > | |
+ Caxi::checker::ace_protocol | |
+ Caxi::checker::axi_protocol | |
+ ►Cchi::chi_fw_transport_if | |
+ ►Cchi::lwtr::chi_lwtr< chi::chi_protocol_types > | |
+ Cchi::lwtr::chi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Cchi::lwtr::chi_lwtr< TYPES > | The TLM2 transaction recorder |
+ Cchi::scv::chi_trx_recorder< TYPES > | The TLM2 transaction recorder |
+ Cchi::chi_protocol_types | The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicated protocol traits class has to be defined |
+ Cchi::scv::impl::chi_recording_types< TYPES > | |
+ ►Caxi::common | |
+ ►Caxi::axi_extension< axi4 > | |
+ Caxi::axi4_extension | |
+ ►Caxi::axi_extension< axi3 > | |
+ Caxi::axi3_extension | |
+ ►Caxi::axi_extension< ace, ace_response > | |
+ Caxi::ace_extension | |
+ Caxi::axi_extension< REQ, RESP > | |
+ Cchi::common | |
+ Cscc::configurer::ConfigHolder | |
+ ►Ccci_utils::consuming_broker | |
+ Cscc::cci_broker | |
+ Caxi::cr_ace< CFG, TYPES > | Snoop response(cr) channel signals |
+ ►Caxi::cr_ace< CFG, CFG::master_types > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ ►Caxi::cr_ace< CFG, CFG::slave_types > | |
+ Caxi::pin::ace_target< CFG > | |
+ Cscc::sc_variable< T >::creator | |
+ Cscc::sc_variable< bool >::creator | |
+ ►Cchi::credit | |
+ Cchi::chi_credit_extension | |
+ Cchi::data | |
+ Clogging::DEFAULT | Default logging category |
+ Cutil::delegate< T > | |
+ Cutil::delegate< bool(const scc::impl::sc_register &, DATATYPE &, sc_core::sc_time &)> | |
+ Cutil::delegate< bool(scc::impl::sc_register &, DATATYPE &, sc_core::sc_time &)> | |
+ Cutil::delegate< R(A...)> | Fast alternative to std::function |
+ Cutil::BitFieldArray< T, BaseOffset, BitsPerItem, NumItems >::Element | |
+ Cahb::enable_for_enum< Enum > | |
+ Caxi::enable_for_enum< Enum > | |
+ Cchi::enable_for_enum< Enum > | |
+ Caxi::enable_for_enum< bar_e > | |
+ Caxi::enable_for_enum< burst_e > | |
+ Cchi::enable_for_enum< dat_optype_e > | |
+ Cchi::enable_for_enum< dat_resptype_e > | |
+ Caxi::enable_for_enum< domain_e > | |
+ Caxi::enable_for_enum< lock_e > | |
+ Cchi::enable_for_enum< req_optype_e > | |
+ Caxi::enable_for_enum< resp_e > | |
+ Cchi::enable_for_enum< rsp_optype_e > | |
+ Cchi::enable_for_enum< rsp_resperrtype_e > | |
+ Cchi::enable_for_enum< rsp_resptype_e > | |
+ Caxi::enable_for_enum< snoop_e > | |
+ Cchi::enable_for_enum< snp_optype_e > | |
+ ►Cboost::statechart::event | |
+ Caxi::fsm::AckRecv | |
+ Caxi::fsm::BegPartReq | |
+ Caxi::fsm::BegPartResp | |
+ Caxi::fsm::BegReq | |
+ Caxi::fsm::BegResp | |
+ Caxi::fsm::EndPartReq | |
+ Caxi::fsm::EndPartResp | |
+ Caxi::fsm::EndReq | |
+ Caxi::fsm::EndResp | |
+ Caxi::fsm::EndRespNoAck | |
+ Caxi::fsm::WReq | |
+ ►CEXT | |
+ Ctlm::scc::tlm_ext_mm< EXT > | |
+ Cscc::ForLoop< SIZE > | |
+ Cscc::ForLoop< 1 > | |
+ Caxi::fsm::fsm_handle | |
+ ►Cscc::trace::fst_trace | |
+ Cscc::trace::fst_trace_enum | |
+ Cscc::trace::fst_trace_t< T, OT > | |
+ Cscc::trace::gz_writer | |
+ Cstd::hash< util::delegate< R(A...)> > | Hash overload for delegate<T, A...> |
+ Cscc::impl::helper< T, bool > | |
+ Cscc::impl::helper< T, false > | |
+ Cscc::impl::helper< T, true > | |
+ ►Cscc::indexed_resource_access_if | Interface defining access to an indexed resource e.g. register file |
+ Cscc::sc_register_indexed< DATATYPE, SIZE, START > | |
+ Cinitiator | Initiator ID recording TLM extension |
+ Cutil::IoRedirector | Allows to capture the strings written to std::cout and std::cerr (MT-safe) |
+ Caxi::lite_master_types | |
+ Caxi::lite_slave_types | |
+ Cscc::ordered_semaphore::lock | Lock for the semaphore |
+ Clogging::Log< T > | |
+ Cscc::LogConfig | Configuration class for the logging setup |
+ Cutil::range_lut< T >::lut_entry | Lut entry |
+ Ctlm::scc::lwtr::lwtr4tlm2_extension_registry< TYPES > | The TLM transaction extensions recorder registry |
+ Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< TYPES > | The TLM transaction extensions recorder interface |
+ ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< axi_protocol_types > | |
+ Caxi::lwtr::ace_ext_recording | |
+ Caxi::lwtr::axi3_ext_recording | |
+ Caxi::lwtr::axi4_ext_recording | |
+ Caxi::lwtr::tlm_id_ext_recording | |
+ ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< chi_protocol_types > | |
+ Cchi::lwtr::chi_ctrl_ext_recording | |
+ Cchi::lwtr::chi_data_ext_recording | |
+ Cchi::lwtr::chi_link_ext_recording | |
+ Cchi::lwtr::chi_snp_ext_recording | |
+ Cchi::lwtr::tlm_id_ext_recording | |
+ ►Ctlm::scc::lwtr::lwtr4tlm2_extension_registry_if< tlm::tlm_base_protocol_types > | |
+ Ctlm::scc::lwtr::tlm_id_ext_recording | |
+ Caxi::master_types | |
+ Cscc::MT19937 | Mersenne-twister based random number generator |
+ Cutil::MT19937 | Mersenne-Twister pseudo random number generator |
+ ►Ctlm::scc::lwtr::nb_rec_entry | |
+ Caxi::lwtr::nb_ace_rec_entry | |
+ Cchi::lwtr::nb_chi_rec_entry | |
+ Cscc::observer::notification_handle | A handle to be used be the observed object to notify the observer about a change |
+ ►Cscc::observer | The interface defining an observer |
+ Cscc::fst_trace_file | |
+ Cscc::vcd_mt_trace_file | |
+ Cscc::vcd_push_trace_file | |
+ CPath | Path recording TLM extension |
+ Ctlm::scc::tlm_managed_extension< T >::pool | |
+ Cutil::pool_allocator< ELEM_SIZE, CHUNK_SIZE > | Generic pool allocator singleton not being MT-safe |
+ Cutil::pool_allocator< sizeof(payload_type)> | |
+ Caxi::pe::tx_reorderer::que_entry | |
+ Cscc::router< BUSWIDTH >::range_entry | |
+ Cutil::range_lut< T > | Range based lookup table |
+ Cutil::range_lut< std::pair< scc::resource_access_if *, uint64_t > > | |
+ Cutil::range_lut< unsigned > | |
+ Cutil::stl_pool_allocator< T >::rebind< U > | |
+ ►CREQ | |
+ Caxi::axi_extension< REQ, RESP > | |
+ ►Caxi::request | |
+ ►Caxi::axi3 | |
+ Caxi::axi_extension< axi3 > | |
+ ►Caxi::axi4 | |
+ Caxi::axi_extension< axi4 > | |
+ ►Caxi::ace | |
+ Caxi::axi_extension< ace, ace_response > | |
+ Cchi::request | |
+ ►Cscc::resetable | Base class for components having a reset |
+ Cscc::tlm_target_bfs_register_base< derived_t, use_URID > | |
+ ►Cscc::resource_access_if | Interface defining access to a resource e.g. a register |
+ Cscc::bitfield_register< datatype_t > | Register that can contain bitfields |
+ ►Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
+ Cscc::sc_register_masked< DATATYPE, WRMASK, RDMASK > | |
+ ►Caxi::response | |
+ Caxi::axi_extension< axi4 > | |
+ Caxi::axi_extension< axi3 > | |
+ ►Caxi::ace_response | |
+ Caxi::axi_extension< ace, ace_response > | |
+ Caxi::axi_extension< REQ, RESP > | |
+ Cchi::response | |
+ Caxi::rresp_ace< CFG, TYPES > | |
+ ►Caxi::rresp_ace< CFG, CFG::master_types > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ ►Caxi::rresp_ace< CFG, CFG::slave_types > | |
+ Caxi::pin::ace_target< CFG > | |
+ ►Caxi::rresp_axi< CFG, TYPES > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ ►Caxi::rresp_axi< CFG, CFG::master_types > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ ►Caxi::rresp_axi< CFG, CFG::slave_types > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::rresp_axi_lite< CFG, TYPES > | Read data channel signals |
+ ►Cruntime_error | |
+ Cscv_tr::SQLiteDB::SQLiteException | |
+ ►Csc_core::sc_attribute | |
+ Cscc::sc_attribute_randomized< int > | |
+ Cscc::ext_attribute< T > | Extended sc_attribute |
+ Cscc::sc_attribute_randomized< T > | |
+ Cscc::sc_bigint_tester< size > | |
+ Cscc::sc_biguint_tester< size > | |
+ Cscc::sc_bv_tester< size > | |
+ ►Csc_core::sc_clock | |
+ Cscc::sc_clock_ext | A clock source with construction time configurable start delay |
+ Cscc::sc_int_tester< size > | |
+ ►Csc_core::sc_interface | |
+ ►Caxi::bw_blocking_transport_if< TYPES::tlm_payload_type > | |
+ ►Caxi::ace_bw_transport_if< axi::axi_protocol_types > | |
+ Caxi::lwtr::ace_lwtr< axi::axi_protocol_types > | |
+ Caxi::scv::ace_recorder< axi::axi_protocol_types > | |
+ Caxi::lwtr::ace_lwtr< TYPES > | The TLM2 transaction recorder |
+ ►Caxi::pe::axi_initiator_b | |
+ Caxi::pe::ace_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::ace_lite_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::axi_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::simple_ace_initiator< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::scv::ace_recorder< TYPES > | The TLM2 transaction recorder |
+ Caxi::ace_bw_transport_if< TYPES > | |
+ ►Ctlm::scc::pe::intor_bw< type::NB > | |
+ ►Ctlm::scc::pe::intor_bw_nb | |
+ Caxi::pe::ace_target_pe::bw_intor_impl | |
+ Caxi::pe::axi_target_pe::bw_intor_impl | |
+ ►Ctlm::scc::pe::intor_bw< type::BL > | |
+ Ctlm::scc::pe::intor_bw_b | |
+ ►Ctlm::scc::pe::intor_fw< type::NB > | |
+ ►Ctlm::scc::pe::intor_fw_nb | |
+ Caxi::pe::rate_limiting_buffer | |
+ Caxi::pe::tx_reorderer | |
+ Ctlm::scc::pe::parallel_pe | |
+ ►Ctlm::scc::pe::intor_fw< type::BL > | |
+ ►Ctlm::scc::pe::intor_fw_b | |
+ Caxi::pe::axi_initiator_b | |
+ Caxi::pe::simple_initiator_b | |
+ ►Cchi::pe::chi_rn_initiator_b | |
+ Cchi::pe::chi_rn_initiator< BUSWIDTH, TYPES, N, POL > | |
+ ►Ctlm::scc::tlm_signal_bw_transport_if< bool, tlm_signal_baseprotocol_types< bool > > | |
+ Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
+ ►Ctlm::scc::tlm_signal_bw_transport_if< TYPE, tlm_signal_baseprotocol_types< TYPE > > | |
+ Ctlm::scc::sc_signal2tlm_signal< TYPE > | |
+ ►Ctlm::scc::tlm_signal_fw_transport_if< bool, tlm_signal_baseprotocol_types< bool > > | |
+ Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
+ ►Ctlm::scc::tlm_signal_fw_transport_if< TYPE, tlm_signal_baseprotocol_types< TYPE > > | |
+ Ctlm::scc::tlm_signal2sc_signal< TYPE > | |
+ Caxi::bw_blocking_transport_if< TRANS > | |
+ ►Cchi::bw_blocking_transport_if< TRANS > | |
+ ►Cchi::chi_bw_transport_if< chi::chi_protocol_types > | |
+ Cchi::lwtr::chi_lwtr< chi::chi_protocol_types > | |
+ Cchi::lwtr::chi_lwtr< TYPES > | The TLM2 transaction recorder |
+ Cchi::pe::chi_rn_initiator_b | |
+ Cchi::scv::chi_trx_recorder< TYPES > | The TLM2 transaction recorder |
+ Cchi::chi_bw_transport_if< TYPES > | |
+ Ctlm::scc::pe::intor_bw< TYPE > | |
+ Ctlm::scc::pe::intor_fw< TYPE > | |
+ Ctlm::scc::tlm_signal_bw_transport_if< SIG, TYPES > | |
+ Ctlm::scc::tlm_signal_fw_transport_if< SIG, TYPES > | |
+ Cscc::dt::sc_logic_7 | |
+ Cscc::sc_lv_tester< size > | |
+ ►Csc_core::sc_module | |
+ ►Cahb::pe::ahb_initiator_b | |
+ Cahb::pe::ahb3_initiator< BUSWIDTH, TYPES, N, POL > | |
+ ►Cahb::pe::ahb_target_b | |
+ Cahb::pe::ahb3_target< BUSWIDTH, TYPES, N, POL > | |
+ Cahb::pin::initiator< WIDTH > | |
+ Cahb::pin::target< DWIDTH, AWIDTH > | |
+ ►Capb::pe::apb_initiator_b | |
+ Capb::pe::apb_initiator< BUSWIDTH, TYPES, N, POL > | |
+ ►Capb::pe::apb_target_b | |
+ Capb::pe::apb_target< BUSWIDTH, TYPES, N, POL > | |
+ ►Caxi::axi_initiator_base | Axi_initiator class provides an input_socket for incoming TLM transactions. It attaches AXI extension to the tlm_generic_payload and forwards it to the AXI Protocol Engine |
+ Caxi::axi_initiator< BUSWIDTH > | |
+ ►Caxi::axi_target_base | Axi_target class instantiates the AXI Protocol Engine. It accesses the Protocol Engine with access() callback function and forwards the transactions via the output_socket |
+ Caxi::axi_target< BUSWIDTH > | |
+ Caxi::lwtr::ace_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::lwtr::axi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::ace_target_pe | |
+ Caxi::pe::axi_initiator_b | |
+ Caxi::pe::axi_target_pe | |
+ Caxi::pe::ordered_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::rate_limiting_buffer | |
+ Caxi::pe::reordering_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::simple_initiator_b | |
+ Caxi::pe::tx_reorderer | |
+ Caxi::pin::ace_initiator< CFG > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ Caxi::pin::ace_target< CFG > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::scv::axitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
+ Cchi::lwtr::chi_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Cchi::pe::chi_rn_initiator_b | |
+ Cchi::scv::chitlm_recorder_module< BUSWIDTH, TYPES, BASE > | The TLM2 transaction recorder |
+ Cobi::pin::target< DATA_WIDTH, ADDR_WIDTH, ID_WIDTH, USER_WIDTH > | |
+ Cscc::configurer | Design configuration reader |
+ Cscc::hierarchy_dumper | |
+ Cscc::memory< SIZE, BUSWIDTH > | Simple TLM2.0 LT memory model |
+ Cscc::perf_estimator | Performance estimator |
+ Cscc::router< BUSWIDTH > | TLM2.0 router for loosly-timed (LT) models |
+ Cscc::tick2time | |
+ Cscc::time2tick | Translate a tick-less clock (sc_time based) to boolean clock |
+ Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
+ Cscc::tlm_target_mod< BUSWIDTH, ADDR_UNIT_WIDTH > | |
+ ►Cscc::tracer_base | Base class for automatic tracer |
+ ►Cscc::tracer | Component traversing the SystemC object hierarchy and tracing the objects |
+ Cscc::configurable_tracer | Configurable tracer for automatic port and signal tracing |
+ Cscc::value_registry | |
+ Ctlm::scc::lwtr::tlm2_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Ctlm::scc::pe::parallel_pe | |
+ Ctlm::scc::sc_signal2tlm_signal< TYPE > | |
+ Ctlm::scc::scv::tlm_recorder_module< BUSWIDTH, TYPES > | The TLM2 transaction recorder |
+ Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
+ Ctlm::scc::tlm_signal2sc_signal< TYPE > | |
+ ►Csc_core::sc_object | |
+ Cscc::peq< tlm::scc::tlm_gp_shared_ptr > | |
+ Cscc::peq< aw_data > | |
+ Cscc::peq< std::tuple< axi::fsm::protocol_time_point_e, tlm::scc::tlm_gp_shared_ptr, bool > > | |
+ Cscc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > | |
+ Cscc::peq< tlm::tlm_generic_payload * > | |
+ Cscc::peq< chi::lwtr::nb_chi_rec_entry > | |
+ Cscc::peq< std::tuple< uint8_t, axi::fsm::fsm_handle * > > | |
+ Cscc::peq< tlm_signal_type > | |
+ Cscc::peq< std::function< void(void)> > | |
+ Cscc::peq< axi::lwtr::nb_ace_rec_entry > | |
+ Cscc::peq< tlm::scc::lwtr::nb_rec_entry > | |
+ Cscc::peq< std::tuple< payload_type *, tlm::tlm_phase > > | |
+ Cscc::bitfield_register< datatype_t > | Register that can contain bitfields |
+ Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
+ ►Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
+ Cscc::ordered_semaphore_t< 1 > | |
+ Cscc::ordered_semaphore_t< CAPACITY > | |
+ Cscc::peq< TYPE > | Priority event queue |
+ Cscc::sc_thread_pool | |
+ ►Cscc::sc_variable_b | |
+ Cscc::sc_variable< unsigned > | |
+ Cscc::sc_ref_variable< T > | Sc_ref_variable for a particular plain data type. This marks an existing C++ variable as discoverable via the sc_object tree. Whenever possible sc_variable should be used as this does not support value change callback |
+ Cscc::sc_ref_variable< sc_core::sc_event > | |
+ Cscc::sc_ref_variable_masked< T > | Sc_variable for a particular plain data type with limited bit width |
+ Cscc::sc_variable< T > | SystemC variable |
+ Cscc::sc_variable< bool > | |
+ Cscc::tlm_target_bfs_register_base< derived_t, use_URID > | |
+ ►Csc_core::sc_port | |
+ Cscc::sc_in_opt< sc_core::sc_time > | |
+ Cscc::sc_in_opt< sc_dt::sc_uint< 0 > > | |
+ Cscc::sc_in_opt< T > | |
+ Cscc::sc_in_opt< bool > | |
+ Cscc::sc_in_opt< sc_dt::sc_logic > | |
+ ►Cscc::sc_inout_opt< T > | |
+ Cscc::sc_out_opt< sc_dt::sc_uint< 0 > > | |
+ Cscc::sc_out_opt< T > | |
+ Cscc::sc_inout_opt< bool > | |
+ Cscc::sc_inout_opt< sc_dt::sc_logic > | |
+ ►Csc_core::sc_prim_channel | |
+ Cscc::fifo_w_cb< tlm::tlm_generic_payload * > | |
+ Cscc::fifo_w_cb< std::tuple< payload_type *, unsigned > > | |
+ Cscc::fifo_w_cb< std::tuple< tlm::tlm_generic_payload *, unsigned > > | |
+ Cscc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > | |
+ Cscc::fifo_w_cb< T > | Fifo with callbacks |
+ ►Csc_core::sc_semaphore_if | |
+ Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
+ ►Csc_core::sc_signal | |
+ Cscc::sc_owning_signal< T, POL > | Sc_signal which takes ownership of the data (acquire()/release()) |
+ ►Csc_core::sc_signal_in_if | |
+ Ctlm::scc::tlm_signal< SIG, TYPES, N > | |
+ ►Csc_core::sc_trace_file | |
+ Cscc::fst_trace_file | |
+ Cscc::vcd_mt_trace_file | |
+ Cscc::vcd_pull_trace_file | |
+ Cscc::vcd_push_trace_file | |
+ ►Csc_trace_file | |
+ Cscc::value_registry_impl | |
+ Cscc::sc_uint_tester< size > | |
+ Cscc::sc_variable_vector< T > | |
+ Cscc::ScLogger< SEVERITY > | Logger class |
+ ►Cscv_enum_base | |
+ Cscv_tr::scv_extensions< tlm::scc::scv::tlm_phase_enum > | |
+ Cscv_tr::scv_extensions< tlm::tlm_command > | |
+ Cscv_tr::scv_extensions< tlm::tlm_dmi::dmi_access_e > | |
+ Cscv_tr::scv_extensions< tlm::tlm_gp_option > | |
+ Cscv_tr::scv_extensions< tlm::tlm_response_status > | |
+ Cscv_tr::scv_extensions< tlm::tlm_sync_enum > | |
+ ►Cscv_extensions_base | |
+ Cscv_tr::scv_extensions< tlm::scc::scv::tlm_dmi_data > | |
+ Cscv_tr::scv_extensions< tlm::scc::scv::tlm_gp_data > | |
+ Caxi::select_if< Cond, T, S > | |
+ Caxi::select_if< true, T, S > | |
+ Caxi::signal_types | |
+ ►Cboost::statechart::simple_state | |
+ Caxi::fsm::ReadIdle | Phase between 2 read burst response beats |
+ Caxi::fsm::WriteIdle | Phase between 2 burst beats, should keep the link locked |
+ Caxi::slave_types | |
+ Cchi::snp_request | |
+ Cscc::tlm_target_bfs< regs_t, owner_t >::socket_accessor | |
+ Cutil::sparse_array< T, SIZE, PAGE_ADDR_BITS > | Sparse array suitable for large sizes |
+ Cutil::sparse_array< uint8_t, SIZE > | |
+ Cscv_tr::SQLiteDB | |
+ ►Cboost::statechart::state | |
+ Caxi::fsm::ATrans | Special state to map AWREADY/WDATA of SNPS to AXI protocol |
+ Caxi::fsm::Idle | Idle state |
+ Caxi::fsm::PartialRequest | Burst beat |
+ Caxi::fsm::PartialResponse | Beat of a burst response |
+ Caxi::fsm::Request | Request, either the last beat of a write or the address phase of a read |
+ Caxi::fsm::Response | Write response or the last read response (beat) |
+ Caxi::fsm::WaitAck | Waiting for ack in case of ACE access |
+ Caxi::fsm::WaitForResponse | Operation state where the target can do it's stuff |
+ ►Cboost::statechart::state_machine | |
+ Caxi::fsm::AxiProtocolFsm | |
+ Cutil::stl_pool_allocator< T > | |
+ ►Cstd::streambuf | |
+ Cutil::lz4c_steambuf | |
+ Cutil::lz4d_streambuf | |
+ ►Cstd::stringbuf | |
+ Cscc::stream_redirection | Stream redirector |
+ ►Caxi::pe::target_info_if | |
+ Caxi::pe::simple_target< 32 > | |
+ Caxi::pe::ordered_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::reordering_target< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::pe::simple_target< BUSWIDTH, TYPES, N, POL > | |
+ Cscc::target_memory_map_entry< BUSWIDTH > | |
+ Cscc::target_name_map_entry< BUSWIDTH > | |
+ Cutil::thread_pool | Simple thread pool |
+ Cutil::thread_syncronizer | Executes a function syncronized in another thread |
+ ►Ctlm::tlm_base_initiator_socket | |
+ ►Caxi::ace_initiator_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Caxi::scv::ace_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::ace_initiator_socket< CFG::BUSWIDTH > | |
+ Caxi::axi_initiator_socket< 64 > | |
+ Caxi::axi_initiator_socket< 32 > | |
+ ►Caxi::axi_initiator_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Caxi::scv::axi_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::axi_initiator_socket< CFG::BUSWIDTH > | |
+ Cchi::chi_initiator_socket< 32, chi::chi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Ctlm::scc::tlm_signal_initiator_socket< tlm_signal_type, protocol_types, 32 > | |
+ Ctlm::scc::tlm_signal_initiator_socket< TYPE > | |
+ Caxi::ace_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::axi_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Cchi::chi_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Ctlm::scc::tlm_signal_initiator_socket< SIG, TYPES, N, POL > | |
+ ►Ctlm::scc::tlm_base_mm_interface | |
+ Ctlm::scc::tlm_signal_gp< SIG >::gp_mm | |
+ ►Ctlm::tlm_base_target_socket | |
+ Caxi::ace_target_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Caxi::ace_target_socket< CFG::BUSWIDTH > | |
+ Caxi::axi_target_socket< 32 > | |
+ ►Caxi::axi_target_socket< 32, axi::axi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Caxi::scv::axi_rec_target_socket< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::axi_target_socket< CFG::BUSWIDTH > | |
+ Cchi::chi_target_socket< 32, chi::chi_protocol_types, 1, sc_core::SC_ONE_OR_MORE_BOUND > | |
+ Ctlm::scc::tlm_signal_target_socket< tlm_signal_type, protocol_types, 32 > | |
+ Ctlm::scc::tlm_signal_target_socket< TYPE > | |
+ Caxi::ace_target_socket< BUSWIDTH, TYPES, N, POL > | |
+ Caxi::axi_target_socket< BUSWIDTH, TYPES, N, POL > | |
+ Cchi::chi_target_socket< BUSWIDTH, TYPES, N, POL > | |
+ Ctlm::scc::tlm_signal_target_socket< SIG, TYPES, N, POL > | |
+ ►Ctlm::tlm_bw_transport_if | |
+ Caxi::ace_bw_transport_if< axi::axi_protocol_types > | |
+ Caxi::lwtr::axi_lwtr< axi::axi_protocol_types > | |
+ Caxi::pe::simple_axi_initiator< 32 > | |
+ Caxi::scv::axi_recorder< axi::axi_protocol_types > | |
+ Cchi::chi_bw_transport_if< chi::chi_protocol_types > | |
+ ►Ctlm::scc::lwtr::tlm2_lwtr< tlm::tlm_base_protocol_types > | |
+ Ctlm::scc::lwtr::tlm2_lwtr_recorder< BUSWIDTH, TYPES, N, POL > | |
+ Ctlm::scc::scv::tlm_recorder< tlm::tlm_base_protocol_types > | |
+ Cahb::pe::ahb_initiator_b | |
+ Capb::pe::apb_initiator_b | |
+ Caxi::ace_bw_transport_if< TYPES > | |
+ Cchi::chi_bw_transport_if< TYPES > | |
+ Ctlm::scc::lwtr::tlm2_lwtr< TYPES > | The TLM2 transaction recorder |
+ Ctlm::scc::scv::tlm_recorder< TYPES > | The TLM2 transaction recorder |
+ Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ Ctlm::scc::scv::tlm_dmi_data | |
+ ►Ctlm::tlm_extension | |
+ Cahb::ahb_extension | |
+ Caxi::ace_extension | |
+ Caxi::axi3_extension | |
+ Caxi::axi4_extension | |
+ Cchi::chi_credit_extension | |
+ Cchi::chi_ctrl_extension | |
+ Cchi::chi_data_extension | |
+ Cchi::chi_snp_extension | |
+ Cobi::obi_extension | |
+ Cscp::tlm_extensions::initiator_id | |
+ Cscp::tlm_extensions::path_trace | |
+ Ctlm::scc::data_buffer | |
+ Ctlm::scc::lwtr::link_pred_ext | |
+ Ctlm::scc::scv::tlm_recording_extension | Generic payload extension class holding the handle of the last recorded SCV transaction |
+ ►Ctlm::scc::tlm_gp_mm | |
+ Ctlm::scc::tlm_gp_mm_t< SZ, BE > | |
+ Ctlm::scc::tlm_gp_mm_v | |
+ Ctlm::scc::tlm_id_extension | |
+ Ctlm::scc::tlm_unmanaged_extension< T > | |
+ Ctlm::scc::scv::tlm_extension_recording_registry< TYPES > | The TLM transaction extensions recorder registry |
+ Ctlm::scc::scv::tlm_extensions_recording_if< TYPES > | The TLM transaction extensions recorder interface |
+ ►Ctlm::scc::scv::tlm_extensions_recording_if< axi_protocol_types > | |
+ Caxi::scv::ace_ext_recording | |
+ Caxi::scv::axi3_ext_recording | |
+ Caxi::scv::axi4_ext_recording | |
+ Caxi::scv::tlm_id_ext_recording | |
+ ►Ctlm::scc::scv::tlm_extensions_recording_if< chi_protocol_types > | |
+ Cchi::chi_credit_ext_recording | |
+ Cchi::chi_ctrl_ext_recording | |
+ Cchi::chi_data_ext_recording | |
+ Cchi::chi_snp_ext_recording | |
+ Cchi::tlm_id_ext_recording | |
+ ►Ctlm::scc::scv::tlm_extensions_recording_if< tlm::tlm_base_protocol_types > | |
+ Ctlm::scc::scv::tlm_id_ext_recording | |
+ ►Ctlm::tlm_fw_transport_if | |
+ Ctlm::scc::lwtr::tlm2_lwtr< tlm::tlm_base_protocol_types > | |
+ Ctlm::scc::scv::tlm_recorder< tlm::tlm_base_protocol_types > | |
+ Cahb::pe::ahb_target_b | |
+ Capb::pe::apb_target_b | |
+ Ctlm::scc::lwtr::tlm2_lwtr< TYPES > | The TLM2 transaction recorder |
+ Ctlm::scc::scv::tlm_recorder< TYPES > | The TLM2 transaction recorder |
+ Ctlm::scc::tlm2_pv_av_initiator_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ Ctlm::scc::tlm2_pv_av_target_adapter< BUSWIDTH, TYPES, N, POL, TSOCKET_TYPE, ISOCKET_TYPE > | |
+ ►Ctlm::scc::tlm_generic_payload_base | |
+ Ctlm::scc::tlm_signal_gp< SIG > | |
+ Ctlm::scc::scv::tlm_gp_data | |
+ Ctlm::scc::tlm_gp_shared_ptr | |
+ ►Ctlm::tlm_initiator_socket | |
+ Ctlm::scc::initiator_mixin< tlm::tlm_initiator_socket< 0 > > | |
+ ►Ctlm::scc::scv::tlm_rec_initiator_socket< 0 > | |
+ Ctlm::scc::initiator_mixin< tlm::scc::scv::tlm_rec_initiator_socket< 0 > > | |
+ Ctlm::scc::scv::tlm_rec_initiator_socket< BUSWIDTH, TYPES, N, POL > | |
+ Ctlm::scc::tlm_managed_extension< T > | |
+ ►Ctlm::tlm_mm_interface | |
+ Ctlm::scc::tlm_mm< TYPES, CLEANUP_DATA > | Tlm memory manager |
+ ►CTYPES::tlm_payload_type | |
+ Caxi::scv::impl::ace_recording_payload< TYPES > | Class to hold the information to be recorded on the timed streams |
+ Cchi::scv::impl::chi_recording_payload< TYPES > | Class to hold the information to be recorded on the timed streams |
+ Ctlm::scc::scv::impl::tlm_recording_payload< TYPES > | |
+ Ctlm::scc::scv::impl::tlm_recording_types< TYPES > | |
+ Ctlm::scc::tlm_signal_baseprotocol_types< SIG > | |
+ ►Cscc::tlm_target< BUSWIDTH, ADDR_UNIT_WIDTH > | Simple access-width based bus interface (no DMI support) |
+ Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
+ ►Cscc::tlm_target< LT, 8 > | |
+ Cscc::tlm_target_mod< BUSWIDTH, ADDR_UNIT_WIDTH > | |
+ ►Cscc::tlm_target_bfs_base< owner_t > | |
+ Cscc::tlm_target_bfs< regs_t, owner_t > | Peripheral base class using scc::tlm_target |
+ Cscc::tlm_target_bfs_params | |
+ ►Ctlm::tlm_target_socket | |
+ ►Ctlm::scc::scv::tlm_rec_target_socket< LT > | |
+ Ctlm::scc::target_mixin< tlm::scc::scv::tlm_rec_target_socket< LT > > | |
+ Ctlm::scc::target_mixin< tlm::tlm_target_socket< LT > > | |
+ Ctlm::scc::target_mixin< tlm::tlm_target_socket< WIDTH > > | |
+ Ctlm::scc::scv::tlm_rec_target_socket< BUSWIDTH, TYPES, N, POL > | |
+ ►Cscc::traceable | Interface defining a traceable component |
+ Cscc::impl::sc_register< DATATYPE > | Simple register implementation |
+ Cscc::ordered_semaphore | The ordered_semaphore primitive channel class |
+ Cscc::trace::traits< T > | |
+ Cahb::pe::ahb_initiator_b::tx_state | |
+ Caxi::pe::axi_initiator_b::tx_state | |
+ Cchi::pe::chi_rn_initiator_b::tx_state | |
+ Clwtr::value_converter< tlm::tlm_command > | |
+ Clwtr::value_converter< tlm::tlm_dmi::dmi_access_e > | |
+ Clwtr::value_converter< tlm::tlm_gp_option > | |
+ Clwtr::value_converter< tlm::tlm_phase > | |
+ Clwtr::value_converter< tlm::tlm_response_status > | |
+ Clwtr::value_converter< tlm::tlm_sync_enum > | |
+ Cscc::value_registry_if::value_holder | |
+ Cscc::value_registry_if | |
+ Cscc::trace::vcd_scope_stack< T > | |
+ Cscc::trace::vcd_trace | |
+ Cutil::watchdog | Watch dog based on https://github.com/didenko/TimeoutGuard |
+ ►Caxi::wdata_axi< CFG, TYPES > | |
+ Caxi::pin::ace_initiator< CFG > | |
+ Caxi::pin::ace_lite_initiator< CFG > | |
+ Caxi::pin::ace_lite_target< CFG > | |
+ Caxi::pin::ace_target< CFG > | |
+ ►Caxi::wdata_axi< CFG, CFG::master_types > | |
+ Caxi::pin::axi4_initiator< CFG > | |
+ ►Caxi::wdata_axi< CFG, CFG::slave_types > | |
+ Caxi::pin::axi4_target< CFG > | |
+ Caxi::wdata_axi_lite< CFG, TYPES > | Write data channel signals |