diff --git a/develop/ace__initiator_8h_source.html b/develop/ace__initiator_8h_source.html new file mode 100644 index 00000000..8235e4cd --- /dev/null +++ b/develop/ace__initiator_8h_source.html @@ -0,0 +1,832 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_initiator.h Source File + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
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+ +
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+ +
+
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+
ace_initiator.h
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+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_INITIATOR_H_
+
18 #define _BUS_AXI_PIN_ACE_INITIATOR_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <tlm_utils/peq_with_cb_and_phase.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_initiator : public sc_core::sc_module,
+
37  public aw_ace<CFG, typename CFG::master_types>,
+
38  public wdata_ace<CFG, typename CFG::master_types>,
+
39  public b_ace<CFG, typename CFG::master_types>,
+
40  public ar_ace<CFG, typename CFG::master_types>,
+
41  public rresp_ace<CFG, typename CFG::master_types>,
+
42 
+
43  public ac_ace<CFG, typename CFG::master_types>,
+
44  public cr_ace<CFG, typename CFG::master_types>,
+
45  public cd_ace<CFG, typename CFG::master_types>,
+
46 
+
47  protected axi::fsm::base,
+
48  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
49  SC_HAS_PROCESS(ace_initiator);
+
50 
+
51  enum { CACHELINE_SZ = 64 };
+
52 
+
53  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
54  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
55 
+
56  sc_core::sc_in<bool> clk_i{"clk_i"};
+
57 
+
58  axi::ace_target_socket<CFG::BUSWIDTH> tsckt{"tsckt"};
+
59 
+
60  ace_initiator(sc_core::sc_module_name const& nm)
+
61  : sc_core::sc_module(nm)
+
62  // coherent= true
+
63  , base(CFG::BUSWIDTH, true) {
+
64  instance_name = name();
+
65  tsckt(*this);
+
66  SC_METHOD(clk_delay);
+
67  sensitive << clk_i.pos();
+
68  SC_THREAD(ar_t);
+
69  SC_THREAD(r_t);
+
70  SC_THREAD(aw_t);
+
71  SC_THREAD(wdata_t);
+
72  SC_THREAD(b_t);
+
73  SC_THREAD(ac_t);
+
74  SC_THREAD(cr_resp_t);
+
75  SC_THREAD(cd_t);
+
76  SC_THREAD(rack_t);
+
77  SC_THREAD(wack_t);
+
78  }
+
79 
+
80 private:
+
81  void b_transport(payload_type& trans, sc_core::sc_time& t) override {
+
82  trans.set_dmi_allowed(false);
+
83  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
84  }
+
85 
+
86  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
87  assert(trans.get_extension<axi::ace_extension>() && "missing ACE extension");
+
88  sc_core::sc_time delay; // FIXME: calculate delay correctly
+
89  fw_peq.notify(trans, phase, delay);
+
90  return tlm::TLM_ACCEPTED;
+
91  }
+
92 
+
93  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override {
+
94  trans.set_dmi_allowed(false);
+
95  return false;
+
96  }
+
97 
+
98  unsigned int transport_dbg(payload_type& trans) override { return 0; }
+
99 
+
100  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
101 
+
102  fsm_handle* create_fsm_handle() { return new fsm_handle(); }
+
103 
+
104  void setup_callbacks(fsm_handle* fsm_hndl);
+
105 
+
106  void clk_delay() { clk_delayed.notify(axi::CLK_DELAY); }
+
107 
+
108  void ar_t();
+
109  void r_t();
+
110  void aw_t();
+
111  void wdata_t();
+
112  void b_t();
+
118  void ac_t();
+
119  void cr_resp_t();
+
120  void cd_t();
+
121 
+
122  void rack_t();
+
123  void wack_t();
+
131  static typename CFG::data_t get_cache_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
132  unsigned int SNOOP = 3; // TBD??
+
133  scc::peq<std::tuple<uint8_t, fsm_handle*>> cd_vl;
+
134  scc::peq<std::tuple<uint8_t, fsm_handle*>> cr_resp_vl;
+
135  std::array<unsigned, 3> outstanding_cnt{0, 0, 0};
+
136  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
137  std::array<fsm_handle*, 3> active_resp{nullptr, nullptr, nullptr};
+
138  std::array<fsm_handle*, 4> active_resp_beat{nullptr, nullptr, nullptr};
+
139  sc_core::sc_clock* clk_if{nullptr};
+
140  sc_core::sc_event clk_delayed, clk_self, r_end_resp_evt, w_end_resp_evt, aw_evt, ar_evt, ac_end_req_evt;
+
141  void nb_fw(payload_type& trans, const phase_type& phase) {
+
142  auto t = sc_core::SC_ZERO_TIME;
+
143  base::nb_fw(trans, phase, t);
+
144  }
+
145  tlm_utils::peq_with_cb_and_phase<ace_initiator> fw_peq{this, &ace_initiator::nb_fw};
+
146  std::unordered_map<unsigned, std::deque<fsm_handle*>> rd_resp_by_id, wr_resp_by_id;
+
147  sc_core::sc_buffer<uint8_t> wdata_vl;
+
148  sc_core::sc_event rack_vl;
+
149  sc_core::sc_event wack_vl;
+
150  void write_ar(tlm::tlm_generic_payload& trans);
+
151  void write_aw(tlm::tlm_generic_payload& trans);
+
152  void write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last = false);
+
153 };
+
154 
+
155 } // namespace pin
+
156 } // namespace axi
+
157 
+
158 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_ar(tlm::tlm_generic_payload& trans) {
+
159  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
160  this->ar_addr.write(addr);
+
161  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
162  this->ar_prot.write(ext->get_prot());
+
163  if(!CFG::IS_LITE) {
+
164  this->ar_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
165  this->ar_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
166  this->ar_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
167  this->ar_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
168  if(ext->is_exclusive())
+
169  this->ar_lock->write(true);
+
170  this->ar_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
171  this->ar_prot.write(ext->get_prot());
+
172  this->ar_qos->write(ext->get_qos());
+
173  this->ar_region->write(ext->get_region());
+
174  this->ar_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
175  this->ar_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
176  this->ar_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
177  this->ar_user->write(ext->get_user(axi::common::id_type::CTRL));
+
178  }
+
179  }
+
180 }
+
181 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_aw(tlm::tlm_generic_payload& trans) {
+
182  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
183  this->aw_addr.write(addr);
+
184  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
185  this->aw_prot.write(ext->get_prot());
+
186  if(ext->is_exclusive())
+
187  this->aw_lock->write(true);
+
188  if(this->aw_id.get_interface())
+
189  this->aw_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
190  this->aw_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
191  this->aw_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
192  this->aw_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
193  this->aw_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
194  this->aw_qos->write(sc_dt::sc_uint<4>(ext->get_qos()));
+
195  this->aw_region->write(sc_dt::sc_uint<4>(ext->get_region()));
+
196  this->aw_user->write(ext->get_user(axi::common::id_type::CTRL));
+
197  this->aw_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
198  this->aw_snoop->write(sc_dt::sc_uint<CFG::AWSNOOPWIDTH>((uint8_t)ext->get_snoop()));
+
199  this->aw_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
200  this->aw_unique->write(ext->get_unique());
+
201  }
+
202 }
+
203 
+
204 // FIXME: strb not yet correct
+
205 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last) {
+
206  typename CFG::data_t data{0};
+
207  sc_dt::sc_uint<CFG::BUSWIDTH / 8> strb{0};
+
208  auto ext = trans.get_extension<axi::ace_extension>();
+
209  auto size = 1u << ext->get_size();
+
210  auto byte_offset = beat * size;
+
211  auto offset = (trans.get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
212  auto beptr = trans.get_byte_enable_length() ? trans.get_byte_enable_ptr() + byte_offset : nullptr;
+
213  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
214  if(beat == 0) {
+
215  auto dptr = trans.get_data_ptr();
+
216  if(dptr)
+
217  for(size_t i = offset; i < size; ++i, ++dptr) {
+
218  auto bit_offs = i * 8;
+
219  data(bit_offs + 7, bit_offs) = *dptr;
+
220  if(beptr) {
+
221  strb[i] = *beptr == 0xff;
+
222  ++beptr;
+
223  } else
+
224  strb[i] = true;
+
225  }
+
226  } else {
+
227  auto beat_start_idx = byte_offset - offset;
+
228  auto data_len = trans.get_data_length();
+
229  auto dptr = trans.get_data_ptr() + beat_start_idx;
+
230  if(dptr)
+
231  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
232  auto bit_offs = i * 8;
+
233  data(bit_offs + 7, bit_offs) = *dptr;
+
234  if(beptr) {
+
235  strb[i] = *beptr == 0xff;
+
236  ++beptr;
+
237  } else
+
238  strb[i] = true;
+
239  }
+
240  }
+
241  } else { // aligned or single beat access
+
242  auto dptr = trans.get_data_ptr() + byte_offset;
+
243  if(dptr)
+
244  for(size_t i = 0; i < size; ++i, ++dptr) {
+
245  auto bit_offs = (offset + i) * 8;
+
246  data(bit_offs + 7, bit_offs) = *dptr;
+
247  if(beptr) {
+
248  strb[offset + i] = *beptr == 0xff;
+
249  ++beptr;
+
250  } else
+
251  strb[offset + i] = true;
+
252  }
+
253  }
+
254  this->w_data.write(data);
+
255  this->w_strb.write(strb);
+
256  if(!CFG::IS_LITE) {
+
257  this->w_id->write(ext->get_id());
+
258  if(this->w_user.get_interface())
+
259  this->w_user->write(ext->get_user(axi::common::id_type::DATA));
+
260  }
+
261 }
+
262 
+
263 template <typename CFG> typename CFG::data_t axi::pin::ace_initiator<CFG>::get_cache_data_for_beat(fsm_handle* fsm_hndl) {
+
264  auto beat_count = fsm_hndl->beat_count;
+
265  // SCCTRACE(SCMOD) << " " ;
+
266  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
267  auto byte_offset = beat_count * size;
+
268  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
269  typename CFG::data_t data{0};
+
270  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
271  if(beat_count == 0) {
+
272  auto dptr = fsm_hndl->trans->get_data_ptr();
+
273  for(size_t i = offset; i < size; ++i, ++dptr) {
+
274  auto bit_offs = i * 8;
+
275  data(bit_offs + 7, bit_offs) = *dptr;
+
276  }
+
277  } else {
+
278  auto beat_start_idx = byte_offset - offset;
+
279  auto data_len = fsm_hndl->trans->get_data_length();
+
280  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
281  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
282  auto bit_offs = i * 8;
+
283  data(bit_offs + 7, bit_offs) = *dptr;
+
284  }
+
285  }
+
286  } else { // aligned or single beat access
+
287  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
288  for(size_t i = 0; i < size; ++i, ++dptr) {
+
289  auto bit_offs = (offset + i) * 8;
+
290  data(bit_offs + 7, bit_offs) = *dptr;
+
291  }
+
292  }
+
293  return data;
+
294 }
+
295 
+
296 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
297  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
298  if(fsm_hndl->is_snoop) {
+
299  SCCTRACE(SCMOD) << " for snoop in RequestPhaseBeg ";
+
300  } else {
+
301  fsm_hndl->beat_count = 0;
+
302  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
303  if(CFG::IS_LITE) {
+
304  auto offset = fsm_hndl->trans->get_address() % (CFG::BUSWIDTH / 8);
+
305  if(offset + fsm_hndl->trans->get_data_length() > CFG::BUSWIDTH / 8) {
+
306  SCCFATAL(SCMOD) << " transaction " << *fsm_hndl->trans << " is not AXI4Lite compliant";
+
307  }
+
308  }
+
309  }
+
310  };
+
311  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
312  sc_assert(fsm_hndl->trans->is_write());
+
313  if(fsm_hndl->beat_count == 0) {
+
314  write_aw(*fsm_hndl->trans);
+
315  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
316  }
+
317  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count);
+
318  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
319  wdata_vl.write(0x1);
+
320  };
+
321  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
322  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
323  tlm::tlm_phase phase = axi::END_PARTIAL_REQ;
+
324  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
325  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
326  fsm_hndl->beat_count++;
+
327  };
+
328  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
329  if(fsm_hndl->is_snoop) {
+
330  SCCTRACE(SCMOD) << " BegReq of setup_cb";
+
331  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
332  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
333  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
334  } else {
+
335  switch(fsm_hndl->trans->get_command()) {
+
336  case tlm::TLM_READ_COMMAND:
+
337  active_req[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
338  write_ar(*fsm_hndl->trans);
+
339  ar_evt.notify(sc_core::SC_ZERO_TIME);
+
340  break;
+
341  case tlm::TLM_WRITE_COMMAND:
+
342  SCCTRACE(SCMOD) << "in BegReqE for trans " << *fsm_hndl->trans;
+
343  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
344  if(fsm_hndl->beat_count == 0) {
+
345  write_aw(*fsm_hndl->trans);
+
346  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
347  }
+
348  /* for Evict Trans, only addr on aw_t, response on b_t() */
+
349  auto ext = fsm_hndl->trans->get_extension<ace_extension>();
+
350  if(!axi::is_dataless(ext)) {
+
351  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count, true);
+
352  wdata_vl.write(0x3);
+
353  }
+
354  }
+
355  }
+
356  };
+
357  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
358  if(fsm_hndl->is_snoop) {
+
359  active_req[SNOOP] = nullptr;
+
360  ac_end_req_evt.notify(); // if snoop
+
361  } else {
+
362  switch(fsm_hndl->trans->get_command()) {
+
363  case tlm::TLM_READ_COMMAND:
+
364  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
365  active_req[tlm::TLM_READ_COMMAND] = nullptr;
+
366  break;
+
367  case tlm::TLM_WRITE_COMMAND:
+
368  SCCTRACE(SCMOD) << "in EndReq for trans " << *fsm_hndl->trans;
+
369  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
370  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
371  fsm_hndl->beat_count++;
+
372  }
+
373  tlm::tlm_phase phase = tlm::END_REQ;
+
374  sc_core::sc_time t = (sc_core::SC_ZERO_TIME); // (clk_if?clk_if->period()-ace::CLK_DELAY-1_ps:sc_core::SC_ZERO_TIME);
+
375  SCCTRACE(SCMOD) << " in EndReq before set_resp";
+
376  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
377  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
378  }
+
379  };
+
380  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
381  if(fsm_hndl->is_snoop) {
+
382  active_resp_beat[SNOOP] = fsm_hndl;
+
383  cd_vl.notify({1, fsm_hndl});
+
384 
+
385  } else {
+
386  // scheduling the response
+
387  assert(fsm_hndl->trans->is_read());
+
388  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
389  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
390  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
391  }
+
392  };
+
393  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
394  SCCTRACE(SCMOD) << "in EndPartRespE of setup_cb ";
+
395  if(fsm_hndl->is_snoop) {
+
396  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
397  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
398  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
399  // why here nullptr??
+
400  active_resp_beat[SNOOP] = nullptr;
+
401  fsm_hndl->beat_count++;
+
402  } else {
+
403  fsm_hndl->beat_count++;
+
404  r_end_resp_evt.notify();
+
405  }
+
406  };
+
407  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
408  SCCTRACE(SCMOD) << "in setup_cb, processing event BegRespE for trans " << *fsm_hndl->trans;
+
409  if(fsm_hndl->is_snoop) {
+
410  active_resp_beat[SNOOP] = fsm_hndl;
+
411  cd_vl.notify({3, fsm_hndl}); // TBD??
+
412  cr_resp_vl.notify({3, fsm_hndl});
+
413 
+
414  } else {
+
415  // scheduling the response
+
416  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
417  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
418  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
419  }
+
420  };
+
421  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
422  SCCTRACE(SCMOD) << "in EndResp of setup_cb for trans" << *fsm_hndl->trans;
+
423  if(fsm_hndl->is_snoop) {
+
424  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
425  tlm::tlm_phase phase = tlm::END_RESP;
+
426  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
427  active_resp_beat[SNOOP] = nullptr;
+
428  // here notify cr_evnt
+
429  fsm_hndl->finish.notify();
+
430  } else {
+
431  if(fsm_hndl->trans->is_read()) {
+
432  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
433  r_end_resp_evt.notify();
+
434  } else if(fsm_hndl->trans->is_write()) {
+
435  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
436  w_end_resp_evt.notify();
+
437  }
+
438  }
+
439  };
+
440  fsm_hndl->fsm->cb[Ack] = [this, fsm_hndl]() -> void {
+
441  SCCTRACE(SCMOD) << "in ACK of setup_cb for " << *fsm_hndl->trans;
+
442  if(fsm_hndl->trans->is_read()) {
+
443  rack_vl.notify(sc_core::SC_ZERO_TIME);
+
444  }
+
445  if(fsm_hndl->trans->is_write()) {
+
446  wack_vl.notify(sc_core::SC_ZERO_TIME);
+
447  }
+
448  };
+
449 }
+
450 
+
451 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::rack_t() {
+
452  this->r_ack.write(false);
+
453  wait(sc_core::SC_ZERO_TIME);
+
454  while(true) {
+
455  wait(rack_vl);
+
456  this->r_ack.write(true);
+
457  wait(clk_i.posedge_event());
+
458  this->r_ack.write(false);
+
459  }
+
460 }
+
461 
+
462 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::wack_t() {
+
463  this->w_ack.write(false);
+
464  wait(sc_core::SC_ZERO_TIME);
+
465  while(true) {
+
466  wait(wack_vl);
+
467  this->w_ack.write(true);
+
468  wait(clk_i.posedge_event());
+
469  this->w_ack.write(false);
+
470  }
+
471 }
+
472 
+
473 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::ar_t() {
+
474  this->ar_valid.write(false);
+
475  wait(sc_core::SC_ZERO_TIME);
+
476  while(true) {
+
477  wait(ar_evt);
+
478  this->ar_valid.write(true);
+
479  do {
+
480  wait(this->ar_ready.posedge_event() | clk_delayed);
+
481  if(this->ar_ready.read())
+
482  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[tlm::TLM_READ_COMMAND]);
+
483  } while(!this->ar_ready.read());
+
484  wait(clk_i.posedge_event());
+
485  this->ar_valid.write(false);
+
486  }
+
487 }
+
488 
+
489 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::r_t() {
+
490  this->r_ready.write(false);
+
491  wait(sc_core::SC_ZERO_TIME);
+
492  while(true) {
+
493  wait(this->r_valid.posedge_event() | clk_delayed);
+
494  if(this->r_valid.event() || (!active_resp[tlm::TLM_READ_COMMAND] && this->r_valid.read())) {
+
495  wait(sc_core::SC_ZERO_TIME);
+
496  auto id = CFG::IS_LITE ? 0U : this->r_id->read().to_uint();
+
497  auto data = this->r_data.read();
+
498  auto resp = this->r_resp.read();
+
499  SCCTRACE(SCMOD) << " r_t() get r_resp = " << resp;
+
500  auto& q = rd_resp_by_id[id];
+
501  sc_assert(q.size());
+
502  auto* fsm_hndl = q.front();
+
503  auto beat_count = fsm_hndl->beat_count;
+
504  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
505  auto byte_offset = beat_count * size;
+
506  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
507  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
508  if(beat_count == 0) {
+
509  auto dptr = fsm_hndl->trans->get_data_ptr();
+
510  if(dptr)
+
511  for(size_t i = offset; i < size; ++i, ++dptr) {
+
512  auto bit_offs = i * 8;
+
513  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
514  }
+
515  } else {
+
516  auto beat_start_idx = beat_count * size - offset;
+
517  auto data_len = fsm_hndl->trans->get_data_length();
+
518  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
519  if(dptr)
+
520  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
521  auto bit_offs = i * 8;
+
522  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
523  }
+
524  }
+
525  } else { // aligned or single beat access
+
526  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
527  if(dptr)
+
528  for(size_t i = 0; i < size; ++i, ++dptr) {
+
529  auto bit_offs = (offset + i) * 8;
+
530  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
531  }
+
532  }
+
533  axi::ace_extension* e;
+
534  fsm_hndl->trans->get_extension(e);
+
535  e->set_cresp(resp);
+
536  e->add_to_response_array(*e);
+
537  /* for Make Trans, Clean Trans and Read barrier Trans, no read data transfer on r_t, only response on r_t
+
538  * */
+
539  if(axi::is_dataless(e)) {
+
540  SCCTRACE(SCMOD) << " r_t() for Make/Clean/Barrier Trans" << *fsm_hndl->trans;
+
541  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
542  } else {
+
543  auto tp = CFG::IS_LITE || this->r_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
544  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
545  react(tp, fsm_hndl);
+
546  }
+
547  wait(r_end_resp_evt);
+
548  this->r_ready->write(true);
+
549  wait(clk_i.posedge_event());
+
550  this->r_ready.write(false);
+
551  }
+
552  }
+
553 }
+
554 
+
555 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::aw_t() {
+
556  this->aw_valid.write(false);
+
557  wait(sc_core::SC_ZERO_TIME);
+
558  while(true) {
+
559  wait(aw_evt);
+
560  this->aw_valid.write(true);
+
561  SCCTRACE(SCMOD) << " aw_t() write aw_valid ";
+
562  do {
+
563  wait(this->aw_ready.posedge_event() | clk_delayed);
+
564  } while(!this->aw_ready.read());
+
565  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
566  if(axi::is_dataless(fsm_hndl->trans->get_extension<axi::ace_extension>()))
+
567  react(axi::fsm::protocol_time_point_e::EndReqE, fsm_hndl);
+
568  wait(clk_i.posedge_event());
+
569  this->aw_valid.write(false);
+
570  }
+
571 }
+
572 
+
573 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::wdata_t() {
+
574  this->w_valid.write(false);
+
575  wait(sc_core::SC_ZERO_TIME);
+
576  while(true) {
+
577  if(!CFG::IS_LITE)
+
578  this->w_last->write(false);
+
579  wait(wdata_vl.default_event());
+
580  auto val = wdata_vl.read();
+
581  SCCTRACE(SCMOD) << "wdata_t() with wdata_vl = " << (uint16_t)val;
+
582  this->w_valid.write(val & 0x1);
+
583  if(!CFG::IS_LITE)
+
584  this->w_last->write(val & 0x2);
+
585  do {
+
586  wait(this->w_ready.posedge_event() | clk_delayed);
+
587  // SCCTRACE(SCMOD) << "wdata_t() received w_ready for " << *active_req[tlm::TLM_WRITE_COMMAND]->trans;
+
588  if(this->w_ready.read()) {
+
589  auto evt =
+
590  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndReqE : axi::fsm::protocol_time_point_e::EndPartReqE;
+
591  react(evt, active_req[tlm::TLM_WRITE_COMMAND]);
+
592  }
+
593  } while(!this->w_ready.read());
+
594  wait(clk_i.posedge_event());
+
595  this->w_valid.write(false);
+
596  }
+
597 }
+
598 
+
599 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::b_t() {
+
600  this->b_ready.write(false);
+
601  wait(sc_core::SC_ZERO_TIME);
+
602  while(true) {
+
603  wait(this->b_valid.posedge_event() | clk_delayed);
+
604  if(this->b_valid.event() || (!active_resp[tlm::TLM_WRITE_COMMAND] && this->b_valid.read())) {
+
605  auto id = !CFG::IS_LITE ? this->b_id->read().to_uint() : 0U;
+
606  auto resp = this->b_resp.read();
+
607  auto& q = wr_resp_by_id[id];
+
608  sc_assert(q.size());
+
609  auto* fsm_hndl = q.front();
+
610  axi::ace_extension* e;
+
611  fsm_hndl->trans->get_extension(e);
+
612  e->set_resp(axi::into<axi::resp_e>(resp));
+
613  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
614  // r_end_req_evt notified in EndResp
+
615  wait(w_end_resp_evt);
+
616  this->b_ready.write(true);
+
617  wait(clk_i.posedge_event());
+
618  this->b_ready.write(false);
+
619  }
+
620  }
+
621 }
+
622 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::ac_t() {
+
623  this->ac_ready.write(false);
+
624  wait(sc_core::SC_ZERO_TIME);
+
625  auto arid = 0U;
+
626  // A snoop transaction must be a full cache line in length,
+
627  // here cachelinesize in byte, -1 because last beat in Resp transmitted
+
628  auto arlen = ((CACHELINE_SZ - 1) / CFG::BUSWIDTH / 8);
+
629  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
630  // here +1 because last beat in Resp transmitted
+
631  auto data_len = (1 << arsize) * (arlen + 1);
+
632  while(true) {
+
633  wait(this->ac_valid.posedge_event() | clk_delayed);
+
634  if(this->ac_valid.read()) {
+
635  SCCTRACE(SCMOD) << "ACVALID detected, for address 0x" << std::hex << this->ac_addr.read();
+
636  SCCTRACE(SCMOD) << "in ac_t(), create snoop trans with data_len= " << data_len;
+
637  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
638  gp->set_address(this->ac_addr.read());
+
639  gp->set_command(tlm::TLM_READ_COMMAND); // snoop command
+
640  gp->set_streaming_width(data_len);
+
641  axi::ace_extension* ext;
+
642  gp->get_extension(ext);
+
643  // if cacheline smaller than buswidth, beat num=1
+
644  if(data_len == (CFG::BUSWIDTH / 8))
+
645  arlen = 1;
+
646  ext->set_length(arlen);
+
647  ext->set_size(arsize);
+
648  ext->set_snoop(axi::into<axi::snoop_e>(this->ac_snoop->read()));
+
649  ext->set_prot(this->ac_prot->read());
+
650  /*snoop transaction of burst length greater than one must be of burst type WRAP.
+
651  * A snoop transaction of burst length one must be of burst type INCR
+
652  */
+
653  ext->set_burst((CACHELINE_SZ * 8) > CFG::BUSWIDTH ? axi::burst_e::WRAP : axi::burst_e::INCR);
+
654  active_req[SNOOP] = find_or_create(gp, true);
+
655  active_req[SNOOP]->is_snoop = true;
+
656  react(axi::fsm::protocol_time_point_e::RequestPhaseBeg, active_req[SNOOP]);
+
657  // ac_end_req_evt notified in EndReqE
+
658  wait(ac_end_req_evt);
+
659  this->ac_ready.write(true);
+
660  wait(clk_i.posedge_event());
+
661  this->ac_ready.write(false);
+
662  }
+
663  }
+
664 }
+
665 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::cd_t() {
+
666  this->cd_valid.write(false);
+
667  wait(sc_core::SC_ZERO_TIME);
+
668  fsm_handle* fsm_hndl;
+
669  uint8_t val;
+
670  while(true) {
+
671  // cd_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
672  std::tie(val, fsm_hndl) = cd_vl.get();
+
673  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat_count = " << fsm_hndl->beat_count;
+
674  SCCTRACE(SCMOD) << __FUNCTION__ << " got snoop beat of trans " << *fsm_hndl->trans;
+
675  // data already packed in Trans in END_REQ via calling operation_cb
+
676  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
677  this->cd_data.write(get_cache_data_for_beat(fsm_hndl));
+
678  this->cd_valid.write(val & 0x1);
+
679  SCCTRACE(SCMOD) << __FUNCTION__ << "() write cd_valid high ";
+
680  this->cd_last->write(val & 0x2);
+
681  do {
+
682  wait(this->cd_ready.posedge_event() | clk_delayed);
+
683  if(this->cd_ready.read()) {
+
684  auto evt =
+
685  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
686 
+
687  // here only schedule EndPartResp for cache data because EndResp is scheduled in cr_resp_t() when last beat is transferred
+
688  if(!(val & 0x2)) { // BEGIN_PARTIAL_REQ ( val=1 ) or in BEG_RESP(val=3)
+
689  SCCTRACE(SCMOD) << __FUNCTION__ << "() receives cd_ready high, schedule evt " << evt2str(evt);
+
690  react(evt, active_resp_beat[SNOOP]);
+
691  }
+
692  }
+
693  } while(!this->cd_ready.read());
+
694  SCCTRACE(SCMOD) << __FUNCTION__ << " finished snoop beat of trans [" << fsm_hndl->trans << "]";
+
695  wait(clk_i.posedge_event());
+
696  this->cd_valid.write(false);
+
697  if(val & 0x2) // if last beat, after one clock cd_last shouldbe low
+
698  this->cd_last->write(false);
+
699  }
+
700 }
+
701 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::cr_resp_t() {
+
702  this->cr_valid.write(false);
+
703  wait(sc_core::SC_ZERO_TIME);
+
704  fsm_handle* fsm_hndl;
+
705  uint8_t val;
+
706  while(true) {
+
707  // cr_resp_vl notified in BEG_RESP(val=3??)
+
708  std::tie(val, fsm_hndl) = cr_resp_vl.get();
+
709  SCCTRACE(SCMOD) << __FUNCTION__ << " (), generate snoop response in cr channel, val = " << (uint16_t)val
+
710  << " total beat_num = " << fsm_hndl->beat_count;
+
711  // data already packed in Trans in END_REQ via bw_o
+
712  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
713  this->cr_resp.write((ext->get_cresp()));
+
714  this->cr_valid.write(true);
+
715  do {
+
716  wait(this->cr_ready.posedge_event() | clk_delayed);
+
717  if(this->cr_ready.read()) {
+
718  auto evt = axi::fsm::protocol_time_point_e::EndRespE;
+
719  SCCTRACE(SCMOD) << __FUNCTION__ << "(), schedule EndRespE ";
+
720  react(evt, active_resp_beat[SNOOP]);
+
721  }
+
722  } while(!this->cr_ready.read());
+
723  SCCTRACE(SCMOD) << "finished snoop response ";
+
724  wait(clk_i.posedge_event());
+
725  this->cr_valid.write(false);
+
726  }
+
727 }
+
728 
+
729 #endif /* _BUS_AXI_PIN_ACE_INITIATOR_H_ */
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+ + +
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ac_ace
snoop address(AC) channel signals
Definition: signal_if.h:629
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace_target_socket< CFG::BUSWIDTH >
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi_extension::add_to_response_array
void add_to_response_array(response &)
add a read response to the response array
Definition: axi_tlm.h:1598
+
axi::b_axi
Definition: signal_if.h:227
+
axi::cd_ace
snoop data(cd) channel signals
Definition: signal_if.h:658
+
axi::cr_ace
snoop response(cr) channel signals
Definition: signal_if.h:680
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::nb_fw
tlm::tlm_sync_enum nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of th...
Definition: base.cpp:190
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
axi::pin::ace_initiator
Definition: ace_initiator.h:48
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::request::get_size
uint8_t get_size() const
set the AxSIZE value of the transaction
Definition: axi_tlm.h:1389
+
axi::response::set_resp
void set_resp(resp_e)
set the response status as POD
Definition: axi_tlm.h:1500
+
axi::rresp_ace
Definition: signal_if.h:344
+
axi::wdata_axi
Definition: signal_if.h:186
+
scc::peq
priority event queue
Definition: peq.h:41
+
+
+ + + + diff --git a/develop/ace__lite__initiator_8h_source.html b/develop/ace__lite__initiator_8h_source.html new file mode 100644 index 00000000..0dfe41b4 --- /dev/null +++ b/develop/ace__lite__initiator_8h_source.html @@ -0,0 +1,613 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_lite_initiator.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_lite_initiator.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_LITE_INITIATOR_H_
+
18 #define _BUS_AXI_PIN_ACE_LITE_INITIATOR_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <tlm_utils/peq_with_cb_and_phase.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 template <typename CFG>
+
34 struct ace_lite_initiator : public sc_core::sc_module,
+
35  public aw_ace_lite<CFG, typename CFG::master_types>,
+
36  public wdata_ace_lite<CFG, typename CFG::master_types>,
+
37  public b_ace_lite<CFG, typename CFG::master_types>,
+
38  public ar_ace_lite<CFG, typename CFG::master_types>,
+
39  public rresp_ace_lite<CFG, typename CFG::master_types>,
+
40  protected axi::fsm::base,
+
41  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
42  SC_HAS_PROCESS(ace_lite_initiator);
+
43 
+
44  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
45  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
46 
+
47  sc_core::sc_in<bool> clk_i{"clk_i"};
+
48 
+
49  axi::axi_target_socket<CFG::BUSWIDTH> tsckt{"tsckt"};
+
50 
+
51  ace_lite_initiator(sc_core::sc_module_name const& nm)
+
52  : sc_core::sc_module(nm)
+
53  // ace_lite has no ack, therefore coherent= false
+
54  , base(CFG::BUSWIDTH, false) {
+
55  instance_name = name();
+
56  tsckt(*this);
+
57  SC_METHOD(clk_delay);
+
58  sensitive << clk_i.pos();
+
59  SC_THREAD(ar_t);
+
60  SC_THREAD(r_t);
+
61  SC_THREAD(aw_t);
+
62  SC_THREAD(wdata_t);
+
63  SC_THREAD(b_t);
+
64  }
+
65 
+
66 private:
+
67  void b_transport(payload_type& trans, sc_core::sc_time& t) override {
+
68  trans.set_dmi_allowed(false);
+
69  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
70  }
+
71 
+
72  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
73  assert(trans.get_extension<axi::ace_extension>() && "missing ACE extension");
+
74  sc_core::sc_time delay; // FIXME: calculate delay correctly
+
75  fw_peq.notify(trans, phase, delay);
+
76  return tlm::TLM_ACCEPTED;
+
77  }
+
78 
+
79  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override {
+
80  trans.set_dmi_allowed(false);
+
81  return false;
+
82  }
+
83 
+
84  unsigned int transport_dbg(payload_type& trans) override { return 0; }
+
85 
+
86  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
87 
+
88  fsm_handle* create_fsm_handle() { return new fsm_handle(); }
+
89 
+
90  void setup_callbacks(fsm_handle* fsm_hndl);
+
91 
+
92  void clk_delay() { clk_delayed.notify(axi::CLK_DELAY); }
+
93 
+
94  void ar_t();
+
95  void r_t();
+
96  void aw_t();
+
97  void wdata_t();
+
98  void b_t();
+
106  static typename CFG::data_t get_cache_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
107  std::array<unsigned, 3> outstanding_cnt{0, 0, 0};
+
108  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
109  std::array<fsm_handle*, 3> active_resp{nullptr, nullptr, nullptr};
+
110  sc_core::sc_clock* clk_if{nullptr};
+
111  sc_core::sc_event clk_delayed, clk_self, r_end_resp_evt, w_end_resp_evt, aw_evt, ar_evt;
+
112  void nb_fw(payload_type& trans, const phase_type& phase) {
+
113  auto t = sc_core::SC_ZERO_TIME;
+
114  base::nb_fw(trans, phase, t);
+
115  }
+
116  tlm_utils::peq_with_cb_and_phase<ace_lite_initiator> fw_peq{this, &ace_lite_initiator::nb_fw};
+
117  std::unordered_map<unsigned, std::deque<fsm_handle*>> rd_resp_by_id, wr_resp_by_id;
+
118  sc_core::sc_buffer<uint8_t> wdata_vl;
+
119  void write_ar(tlm::tlm_generic_payload& trans);
+
120  void write_aw(tlm::tlm_generic_payload& trans);
+
121  void write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last = false);
+
122 };
+
123 
+
124 } // namespace pin
+
125 } // namespace axi
+
126 
+
127 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::write_ar(tlm::tlm_generic_payload& trans) {
+
128  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
129  this->ar_addr.write(addr);
+
130  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
131  this->ar_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
132  this->ar_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
133  this->ar_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
134  this->ar_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
135  if(ext->is_exclusive())
+
136  this->ar_lock->write(true);
+
137  this->ar_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
138  this->ar_prot.write(ext->get_prot());
+
139  this->ar_qos->write(ext->get_qos());
+
140  this->ar_region->write(ext->get_region());
+
141  this->ar_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
142  this->ar_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
143  this->ar_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
144  this->ar_user->write(ext->get_user(axi::common::id_type::CTRL));
+
145  }
+
146 }
+
147 
+
148 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::write_aw(tlm::tlm_generic_payload& trans) {
+
149  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
150  this->aw_addr.write(addr);
+
151  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
152  this->aw_prot.write(ext->get_prot());
+
153  // TBD?? this->aw_lock.write();
+
154  if(this->aw_id.get_interface())
+
155  this->aw_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
156  if(ext->is_exclusive())
+
157  this->aw_lock->write(true);
+
158  this->aw_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
159  this->aw_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
160  this->aw_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
161  this->aw_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
162  this->aw_qos->write(sc_dt::sc_uint<4>(ext->get_qos()));
+
163  this->aw_region->write(sc_dt::sc_uint<4>(ext->get_region()));
+
164  this->aw_user->write(ext->get_user(axi::common::id_type::CTRL));
+
165  this->aw_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
166  this->aw_snoop->write(sc_dt::sc_uint<CFG::AWSNOOPWIDTH>((uint8_t)ext->get_snoop()));
+
167  this->aw_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
168  /* ace_lite doe not have unique* */
+
169  // this->aw_unique->write(ext->get_unique());
+
170  if(ext->is_stash_nid_en()) {
+
171  this->aw_stashniden->write(true);
+
172  this->aw_stashnid->write(sc_dt::sc_uint<11>(ext->get_stash_nid()));
+
173  }
+
174  if(ext->is_stash_lpid_en()) {
+
175  this->aw_stashlpiden->write(true);
+
176  this->aw_stashlpid->write(sc_dt::sc_uint<5>(ext->get_stash_lpid()));
+
177  }
+
178  }
+
179 }
+
180 
+
181 // FIXME: strb not yet correct
+
182 template <typename CFG>
+
183 inline void axi::pin::ace_lite_initiator<CFG>::write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last) {
+
184  typename CFG::data_t data{0};
+
185  sc_dt::sc_uint<CFG::BUSWIDTH / 8> strb{0};
+
186  auto ext = trans.get_extension<axi::ace_extension>();
+
187  auto size = 1u << ext->get_size();
+
188  auto byte_offset = beat * size;
+
189  auto offset = (trans.get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
190  auto beptr = trans.get_byte_enable_length() ? trans.get_byte_enable_ptr() + byte_offset : nullptr;
+
191  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
192  if(beat == 0) {
+
193  auto dptr = trans.get_data_ptr();
+
194  if(dptr)
+
195  for(size_t i = offset; i < size; ++i, ++dptr) {
+
196  auto bit_offs = i * 8;
+
197  data(bit_offs + 7, bit_offs) = *dptr;
+
198  if(beptr) {
+
199  strb[i] = *beptr == 0xff;
+
200  ++beptr;
+
201  } else
+
202  strb[i] = true;
+
203  }
+
204  } else {
+
205  auto beat_start_idx = byte_offset - offset;
+
206  auto data_len = trans.get_data_length();
+
207  auto dptr = trans.get_data_ptr() + beat_start_idx;
+
208  if(dptr)
+
209  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
210  auto bit_offs = i * 8;
+
211  data(bit_offs + 7, bit_offs) = *dptr;
+
212  if(beptr) {
+
213  strb[i] = *beptr == 0xff;
+
214  ++beptr;
+
215  } else
+
216  strb[i] = true;
+
217  }
+
218  }
+
219  } else { // aligned or single beat access
+
220  auto dptr = trans.get_data_ptr() + byte_offset;
+
221  if(dptr)
+
222  for(size_t i = 0; i < size; ++i, ++dptr) {
+
223  auto bit_offs = (offset + i) * 8;
+
224  data(bit_offs + 7, bit_offs) = *dptr;
+
225  if(beptr) {
+
226  strb[offset + i] = *beptr == 0xff;
+
227  ++beptr;
+
228  } else
+
229  strb[offset + i] = true;
+
230  }
+
231  }
+
232  this->w_data.write(data);
+
233  this->w_strb.write(strb);
+
234  if(!CFG::IS_LITE) {
+
235  this->w_id->write(ext->get_id());
+
236  if(this->w_user.get_interface())
+
237  this->w_user->write(ext->get_user(axi::common::id_type::DATA));
+
238  }
+
239 }
+
240 
+
241 template <typename CFG> typename CFG::data_t axi::pin::ace_lite_initiator<CFG>::get_cache_data_for_beat(fsm_handle* fsm_hndl) {
+
242  auto beat_count = fsm_hndl->beat_count;
+
243  // SCCTRACE(SCMOD) << " " ;
+
244  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
245  auto byte_offset = beat_count * size;
+
246  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
247  typename CFG::data_t data{0};
+
248  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
249  if(beat_count == 0) {
+
250  auto dptr = fsm_hndl->trans->get_data_ptr();
+
251  for(size_t i = offset; i < size; ++i, ++dptr) {
+
252  auto bit_offs = i * 8;
+
253  data(bit_offs + 7, bit_offs) = *dptr;
+
254  }
+
255  } else {
+
256  auto beat_start_idx = byte_offset - offset;
+
257  auto data_len = fsm_hndl->trans->get_data_length();
+
258  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
259  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
260  auto bit_offs = i * 8;
+
261  data(bit_offs + 7, bit_offs) = *dptr;
+
262  }
+
263  }
+
264  } else { // aligned or single beat access
+
265  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
266  for(size_t i = 0; i < size; ++i, ++dptr) {
+
267  auto bit_offs = (offset + i) * 8;
+
268  data(bit_offs + 7, bit_offs) = *dptr;
+
269  }
+
270  }
+
271  return data;
+
272 }
+
273 
+
274 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
275  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
276  if(fsm_hndl->is_snoop) {
+
277  SCCTRACE(SCMOD) << " for snoop in RequestPhaseBeg ";
+
278  } else {
+
279  fsm_hndl->beat_count = 0;
+
280  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
281  if(CFG::IS_LITE) {
+
282  auto offset = fsm_hndl->trans->get_address() % (CFG::BUSWIDTH / 8);
+
283  if(offset + fsm_hndl->trans->get_data_length() > CFG::BUSWIDTH / 8) {
+
284  SCCFATAL(SCMOD) << " transaction " << *fsm_hndl->trans << " is not AXI4Lite compliant";
+
285  }
+
286  }
+
287  }
+
288  };
+
289  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
290  sc_assert(fsm_hndl->trans->is_write());
+
291  if(fsm_hndl->beat_count == 0) {
+
292  write_aw(*fsm_hndl->trans);
+
293  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
294  }
+
295  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count);
+
296  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
297  wdata_vl.write(0x1);
+
298  };
+
299  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
300  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
301  tlm::tlm_phase phase = axi::END_PARTIAL_REQ;
+
302  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
303  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
304  fsm_hndl->beat_count++;
+
305  };
+
306  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
307  SCCTRACEALL(SCMOD) << "In BegReqE of setup_cb";
+
308  switch(fsm_hndl->trans->get_command()) {
+
309  case tlm::TLM_READ_COMMAND:
+
310  active_req[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
311  write_ar(*fsm_hndl->trans);
+
312  ar_evt.notify(sc_core::SC_ZERO_TIME);
+
313  break;
+
314  case tlm::TLM_WRITE_COMMAND:
+
315  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
316  if(fsm_hndl->beat_count == 0) {
+
317  write_aw(*fsm_hndl->trans);
+
318  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
319  }
+
320  /* for dataless trans, no data on wdata_t*/
+
321  auto ext = fsm_hndl->trans->get_extension<ace_extension>();
+
322  if(!axi::is_dataless(ext)) {
+
323  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count, true);
+
324  wdata_vl.write(0x3);
+
325  }
+
326  }
+
327  };
+
328  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
329  SCCTRACEALL(SCMOD) << "In EndReqE of setup_cb";
+
330  switch(fsm_hndl->trans->get_command()) {
+
331  case tlm::TLM_READ_COMMAND:
+
332  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
333  active_req[tlm::TLM_READ_COMMAND] = nullptr;
+
334  break;
+
335  case tlm::TLM_WRITE_COMMAND:
+
336  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
337  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
338  fsm_hndl->beat_count++;
+
339  }
+
340  tlm::tlm_phase phase = tlm::END_REQ;
+
341  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
342  SCCTRACE(SCMOD) << " in EndReq before set_resp";
+
343  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
344  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
345  };
+
346 
+
347  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
348  // scheduling the response
+
349  assert(fsm_hndl->trans->is_read());
+
350  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
351  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
352  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
353  };
+
354  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
355  SCCTRACE(SCMOD) << "in EndPartRespE of setup_cb ";
+
356  fsm_hndl->beat_count++;
+
357  r_end_resp_evt.notify();
+
358  };
+
359  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
360  // scheduling the response
+
361  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
362  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
363  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
364  };
+
365  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
366  SCCTRACE(SCMOD) << "in EndResp of setup_cb ";
+
367  if(fsm_hndl->trans->is_read()) {
+
368  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
369  r_end_resp_evt.notify();
+
370  }
+
371  if(fsm_hndl->trans->is_write()) {
+
372  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
373  w_end_resp_evt.notify();
+
374  }
+
375  };
+
376 }
+
377 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::ar_t() {
+
378  this->ar_valid.write(false);
+
379  wait(sc_core::SC_ZERO_TIME);
+
380  while(true) {
+
381  wait(ar_evt);
+
382  this->ar_valid.write(true);
+
383  do {
+
384  wait(this->ar_ready.posedge_event() | clk_delayed);
+
385  if(this->ar_ready.read())
+
386  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[tlm::TLM_READ_COMMAND]);
+
387  } while(!this->ar_ready.read());
+
388  wait(clk_i.posedge_event());
+
389  this->ar_valid.write(false);
+
390  }
+
391 }
+
392 
+
393 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::r_t() {
+
394  this->r_ready.write(false);
+
395  wait(sc_core::SC_ZERO_TIME);
+
396  while(true) {
+
397  wait(this->r_valid.posedge_event() | clk_delayed);
+
398  if(this->r_valid.event() || (!active_resp[tlm::TLM_READ_COMMAND] && this->r_valid.read())) {
+
399  wait(sc_core::SC_ZERO_TIME);
+
400  auto id = CFG::IS_LITE ? 0U : this->r_id->read().to_uint();
+
401  auto data = this->r_data.read();
+
402  auto resp = this->r_resp.read();
+
403  auto& q = rd_resp_by_id[id];
+
404  sc_assert(q.size());
+
405  auto* fsm_hndl = q.front();
+
406  auto beat_count = fsm_hndl->beat_count;
+
407  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
408  auto byte_offset = beat_count * size;
+
409  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
410  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
411  if(beat_count == 0) {
+
412  auto dptr = fsm_hndl->trans->get_data_ptr();
+
413  if(dptr)
+
414  for(size_t i = offset; i < size; ++i, ++dptr) {
+
415  auto bit_offs = i * 8;
+
416  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
417  }
+
418  } else {
+
419  auto beat_start_idx = beat_count * size - offset;
+
420  auto data_len = fsm_hndl->trans->get_data_length();
+
421  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
422  if(dptr)
+
423  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
424  auto bit_offs = i * 8;
+
425  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
426  }
+
427  }
+
428  } else { // aligned or single beat access
+
429  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
430  if(dptr)
+
431  for(size_t i = 0; i < size; ++i, ++dptr) {
+
432  auto bit_offs = (offset + i) * 8;
+
433  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
434  }
+
435  }
+
436  axi::ace_extension* e;
+
437  fsm_hndl->trans->get_extension(e);
+
438  e->set_cresp(resp);
+
439  e->add_to_response_array(*e);
+
440  /* dataless trans * */
+
441  if(axi::is_dataless(e)) {
+
442  SCCTRACE(SCMOD) << " r_t() for Make/Clean/Barrier Trans" << *fsm_hndl->trans;
+
443  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
444  } else {
+
445  auto tp = CFG::IS_LITE || this->r_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
446  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
447  react(tp, fsm_hndl);
+
448  }
+
449 
+
450  // r_end_resp_evt notified in EndPartialResp or Endresp
+
451  wait(r_end_resp_evt);
+
452  this->r_ready->write(true);
+
453  wait(clk_i.posedge_event());
+
454  this->r_ready.write(false);
+
455  }
+
456  }
+
457 }
+
458 
+
459 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::aw_t() {
+
460  this->aw_valid.write(false);
+
461  wait(sc_core::SC_ZERO_TIME);
+
462  while(true) {
+
463  wait(aw_evt);
+
464  this->aw_valid.write(true);
+
465  do {
+
466  wait(this->aw_ready.posedge_event() | clk_delayed);
+
467  } while(!this->aw_ready.read());
+
468  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
469  if(axi::is_dataless(fsm_hndl->trans->get_extension<axi::ace_extension>()))
+
470  react(axi::fsm::protocol_time_point_e::EndReqE, fsm_hndl);
+
471  wait(clk_i.posedge_event());
+
472  this->aw_valid.write(false);
+
473  }
+
474 }
+
475 
+
476 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::wdata_t() {
+
477  this->w_valid.write(false);
+
478  wait(sc_core::SC_ZERO_TIME);
+
479  while(true) {
+
480  if(!CFG::IS_LITE)
+
481  this->w_last->write(false);
+
482  wait(wdata_vl.default_event());
+
483  auto val = wdata_vl.read();
+
484  this->w_valid.write(val & 0x1);
+
485  if(!CFG::IS_LITE)
+
486  this->w_last->write(val & 0x2);
+
487  do {
+
488  wait(this->w_ready.posedge_event() | clk_delayed);
+
489  if(this->w_ready.read()) {
+
490  auto evt =
+
491  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndReqE : axi::fsm::protocol_time_point_e::EndPartReqE;
+
492  react(evt, active_req[tlm::TLM_WRITE_COMMAND]);
+
493  }
+
494  } while(!this->w_ready.read());
+
495  wait(clk_i.posedge_event());
+
496  this->w_valid.write(false);
+
497  }
+
498 }
+
499 
+
500 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::b_t() {
+
501  this->b_ready.write(false);
+
502  wait(sc_core::SC_ZERO_TIME);
+
503  while(true) {
+
504  wait(this->b_valid.posedge_event() | clk_delayed);
+
505  if(this->b_valid.event() || (!active_resp[tlm::TLM_WRITE_COMMAND] && this->b_valid.read())) {
+
506  SCCTRACEALL(SCMOD) << " b_t() received b_valid ";
+
507  auto id = !CFG::IS_LITE ? this->b_id->read().to_uint() : 0U;
+
508  auto resp = this->b_resp.read();
+
509  auto& q = wr_resp_by_id[id];
+
510  sc_assert(q.size());
+
511  auto* fsm_hndl = q.front();
+
512  axi::ace_extension* e;
+
513  fsm_hndl->trans->get_extension(e);
+
514  e->set_resp(axi::into<axi::resp_e>(resp));
+
515  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
516  // w_end_resp_evt notified in Endresp
+
517  wait(w_end_resp_evt);
+
518  this->b_ready.write(true);
+
519  wait(clk_i.posedge_event());
+
520  this->b_ready.write(false);
+
521  }
+
522  }
+
523 }
+
524 #endif /* _BUS_AXI_PIN_ace_lite_INITIATOR_H_ */
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi_extension::add_to_response_array
void add_to_response_array(response &)
add a read response to the response array
Definition: axi_tlm.h:1598
+
axi::axi_target_socket< CFG::BUSWIDTH >
+
axi::b_axi
Definition: signal_if.h:227
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::nb_fw
tlm::tlm_sync_enum nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of th...
Definition: base.cpp:190
+
axi::fsm::base::base
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
the constructor
Definition: base.cpp:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::pin::ace_lite_initiator
Definition: ace_lite_initiator.h:41
+
axi::request::get_size
uint8_t get_size() const
set the AxSIZE value of the transaction
Definition: axi_tlm.h:1389
+
axi::response::set_resp
void set_resp(resp_e)
set the response status as POD
Definition: axi_tlm.h:1500
+
axi::rresp_axi
Definition: signal_if.h:308
+
axi::wdata_axi
Definition: signal_if.h:186
+
+
+ + + + diff --git a/develop/ace__lite__target_8h_source.html b/develop/ace__lite__target_8h_source.html new file mode 100644 index 00000000..6af9d413 --- /dev/null +++ b/develop/ace__lite__target_8h_source.html @@ -0,0 +1,616 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_lite_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_lite_target.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_LITE_TARGET_H_
+
18 #define _BUS_AXI_PIN_ACE_LITE_TARGET_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <util/ities.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_lite_target : public sc_core::sc_module,
+
37  public aw_ace_lite<CFG, typename CFG::slave_types>,
+
38  public wdata_ace_lite<CFG, typename CFG::slave_types>,
+
39  public b_ace_lite<CFG, typename CFG::slave_types>,
+
40  public ar_ace_lite<CFG, typename CFG::slave_types>,
+
41  public rresp_ace_lite<CFG, typename CFG::slave_types>,
+
42  protected axi::fsm::base,
+
43  public axi::axi_bw_transport_if<axi::axi_protocol_types> {
+
44  SC_HAS_PROCESS(ace_lite_target);
+
45 
+
46  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
47  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
48 
+
49  sc_core::sc_in<bool> clk_i{"clk_i"};
+
50 
+
51  axi::axi_initiator_socket<CFG::BUSWIDTH> isckt{"isckt"};
+
52 
+
53  ace_lite_target(sc_core::sc_module_name const& nm)
+
54  : sc_core::sc_module(nm)
+
55  // ace_lite has no ack, therefore coherent= false
+
56  , base(CFG::BUSWIDTH, false) {
+
57  instance_name = name();
+
58  isckt.bind(*this);
+
59  SC_METHOD(clk_delay);
+
60  sensitive << clk_i.pos();
+
61  dont_initialize();
+
62  SC_THREAD(ar_t);
+
63  SC_THREAD(rresp_t);
+
64  SC_THREAD(aw_t);
+
65  SC_THREAD(wdata_t);
+
66  SC_THREAD(bresp_t);
+
67  }
+
68 
+
69 private:
+
70  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
71 
+
72  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override;
+
73 
+
74  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
75 
+
76  axi::fsm::fsm_handle* create_fsm_handle() override { return new fsm_handle(); }
+
77 
+
78  void setup_callbacks(axi::fsm::fsm_handle*) override;
+
79 
+
80  void clk_delay() {
+
81 #ifdef DELTA_SYNC
+
82  if(sc_core::sc_delta_count_at_current_time() < 5) {
+
83  clk_self.notify(sc_core::SC_ZERO_TIME);
+
84  next_trigger(clk_self);
+
85  } else
+
86  clk_delayed.notify(sc_core::SC_ZERO_TIME /*clk_if ? clk_if->period() - 1_ps : 1_ps*/);
+
87 #else
+
88  clk_delayed.notify(axi::CLK_DELAY);
+
89 #endif
+
90  }
+
91  void ar_t();
+
92  void rresp_t();
+
93  void aw_t();
+
94  void wdata_t();
+
95  void bresp_t();
+
96  static typename CFG::data_t get_read_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
97  struct aw_data {
+
98  unsigned id;
+
99  uint64_t addr;
+
100  unsigned prot;
+
101  unsigned size;
+
102  unsigned cache;
+
103  unsigned burst;
+
104  unsigned qos;
+
105  unsigned region;
+
106  unsigned len;
+
107  unsigned domain;
+
108  unsigned snoop;
+
109  unsigned bar;
+
110  unsigned unique;
+
111  unsigned stashnid;
+
112  unsigned stashlpid;
+
113  bool lock;
+
114  uint64_t user;
+
115  };
+
116 
+
117  std::deque<axi::fsm::fsm_handle*> snp_resp_queue;
+
118 
+
119  sc_core::sc_clock* clk_if{nullptr};
+
120  sc_core::sc_event clk_delayed, clk_self, ar_end_req_evt, wdata_end_req_evt;
+
121  std::array<fsm_handle*, 3> active_req_beat{nullptr, nullptr, nullptr};
+
122  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
123  std::array<fsm_handle*, 3> active_resp_beat{nullptr, nullptr, nullptr};
+
124  scc::peq<aw_data> aw_que;
+
125  scc::peq<std::tuple<uint8_t, fsm_handle*>> rresp_vl;
+
126  scc::peq<std::tuple<uint8_t, fsm_handle*>> wresp_vl;
+
127 };
+
128 } // namespace pin
+
129 } // namespace axi
+
130 
+
131 template <typename CFG>
+
132 inline tlm::tlm_sync_enum axi::pin::ace_lite_target<CFG>::nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) {
+
133  auto ret = tlm::TLM_ACCEPTED;
+
134  SCCTRACE(SCMOD) << "nb_transport_bw with " << phase << " with delay= " << t << " of trans " << trans;
+
135  if(phase == END_PARTIAL_REQ || phase == tlm::END_REQ) { // read/write
+
136  schedule(phase == tlm::END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
137  } else if(phase == axi::BEGIN_PARTIAL_RESP || phase == tlm::BEGIN_RESP) { // read/write response
+
138  schedule(phase == tlm::BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
139  } else
+
140  SCCFATAL(SCMOD) << "Illegal phase received: " << phase;
+
141  return ret;
+
142 }
+
143 
+
144 template <typename CFG>
+
145 inline void axi::pin::ace_lite_target<CFG>::invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) {}
+
146 
+
147 template <typename CFG> typename CFG::data_t axi::pin::ace_lite_target<CFG>::get_read_data_for_beat(fsm_handle* fsm_hndl) {
+
148  auto beat_count = fsm_hndl->beat_count;
+
149  // SCCTRACE(SCMOD) << " " ;
+
150  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
151  auto byte_offset = beat_count * size;
+
152  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
153  typename CFG::data_t data{0};
+
154  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
155  if(beat_count == 0) {
+
156  auto dptr = fsm_hndl->trans->get_data_ptr();
+
157  for(size_t i = offset; i < size; ++i, ++dptr) {
+
158  auto bit_offs = i * 8;
+
159  data(bit_offs + 7, bit_offs) = *dptr;
+
160  }
+
161  } else {
+
162  auto beat_start_idx = byte_offset - offset;
+
163  auto data_len = fsm_hndl->trans->get_data_length();
+
164  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
165  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
166  auto bit_offs = i * 8;
+
167  data(bit_offs + 7, bit_offs) = *dptr;
+
168  }
+
169  }
+
170  } else { // aligned or single beat access
+
171  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
172  for(size_t i = 0; i < size; ++i, ++dptr) {
+
173  auto bit_offs = (offset + i) * 8;
+
174  data(bit_offs + 7, bit_offs) = *dptr;
+
175  }
+
176  }
+
177  return data;
+
178 }
+
179 
+
180 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
181  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void { fsm_hndl->beat_count = 0; };
+
182  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
183  sc_assert(fsm_hndl->trans->get_command() == tlm::TLM_WRITE_COMMAND);
+
184  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_REQ;
+
185  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
186  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
187  if(ret == tlm::TLM_UPDATED) {
+
188  schedule(EndPartReqE, fsm_hndl->trans, t, true);
+
189  }
+
190  };
+
191  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
192  wdata_end_req_evt.notify();
+
193  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
194  fsm_hndl->beat_count++;
+
195  };
+
196  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
197  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
198  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
199  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
200  if(ret == tlm::TLM_UPDATED) {
+
201  schedule(EndReqE, fsm_hndl->trans, t, true);
+
202  }
+
203  };
+
204  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
205  switch(fsm_hndl->trans->get_command()) {
+
206  case tlm::TLM_READ_COMMAND:
+
207  ar_end_req_evt.notify();
+
208  active_req_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
209  break;
+
210  case tlm::TLM_WRITE_COMMAND:
+
211  wdata_end_req_evt.notify();
+
212  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
213  fsm_hndl->beat_count++;
+
214  break;
+
215  default:
+
216  break;
+
217  }
+
218  };
+
219  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
220  assert(fsm_hndl->trans->is_read());
+
221  active_resp_beat[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
222  rresp_vl.notify({1, fsm_hndl});
+
223  };
+
224  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
225  // scheduling the response
+
226  assert(fsm_hndl->trans->is_read());
+
227  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
228  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
229  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
230  active_resp_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
231  fsm_hndl->beat_count++;
+
232  };
+
233  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
234  SCCTRACE(SCMOD) << "processing event BegRespE for trans " << *fsm_hndl->trans;
+
235  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
236  active_resp_beat[fsm_hndl->trans->get_command()] = fsm_hndl;
+
237  switch(fsm_hndl->trans->get_command()) {
+
238  case tlm::TLM_READ_COMMAND:
+
239  rresp_vl.notify({3, fsm_hndl});
+
240  break;
+
241  case tlm::TLM_WRITE_COMMAND:
+
242  wresp_vl.notify({3, fsm_hndl});
+
243  break;
+
244  default:
+
245  break;
+
246  }
+
247  };
+
248  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
249  // scheduling the response
+
250  tlm::tlm_phase phase = tlm::END_RESP;
+
251  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
252  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
253  SCCTRACE(SCMOD) << "EndResp of setup_cb with coherent = " << coherent;
+
254  fsm_hndl->finish.notify();
+
255  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
256  };
+
257 }
+
258 
+
259 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::ar_t() {
+
260  this->ar_ready.write(false);
+
261  wait(sc_core::SC_ZERO_TIME);
+
262  auto arid = 0U;
+
263  auto arlen = 0U;
+
264  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
265  auto data_len = (1 << arsize) * (arlen + 1);
+
266  while(true) {
+
267  wait(this->ar_valid.posedge_event() | clk_delayed);
+
268  if(this->ar_valid.read()) {
+
269  SCCTRACE(SCMOD) << "ARVALID detected for 0x" << std::hex << this->ar_addr.read();
+
270  arid = this->ar_id->read().to_uint();
+
271  arlen = this->ar_len->read().to_uint();
+
272  arsize = this->ar_size->read().to_uint();
+
273  data_len = (1 << arsize) * (arlen + 1);
+
274  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len);
+
275  gp->set_address(this->ar_addr.read());
+
276  gp->set_command(tlm::TLM_READ_COMMAND);
+
277  gp->set_streaming_width(data_len);
+
278  axi::ace_extension* ext;
+
279  gp->get_extension(ext);
+
280  ext->set_id(arid);
+
281  ext->set_length(arlen);
+
282  if(this->ar_lock->read())
+
283  ext->set_exclusive(true);
+
284  ext->set_size(arsize);
+
285  ext->set_burst(axi::into<axi::burst_e>(this->ar_burst->read()));
+
286  ext->set_cache(this->ar_cache->read());
+
287  ext->set_prot(this->ar_prot->read());
+
288  ext->set_qos(this->ar_qos->read());
+
289  ext->set_region(this->ar_region->read());
+
290  ext->set_domain(axi::into<axi::domain_e>(this->ar_domain->read())); // ace extension
+
291  ext->set_snoop(axi::into<axi::snoop_e>(this->ar_snoop->read()));
+
292  ext->set_barrier(axi::into<axi::bar_e>(this->ar_bar->read()));
+
293 
+
294  active_req_beat[tlm::TLM_READ_COMMAND] = find_or_create(gp);
+
295  react(axi::fsm::protocol_time_point_e::BegReqE, active_req_beat[tlm::TLM_READ_COMMAND]);
+
296  wait(ar_end_req_evt);
+
297  this->ar_ready.write(true);
+
298  wait(clk_i.posedge_event());
+
299  this->ar_ready.write(false);
+
300  }
+
301  }
+
302 }
+
303 
+
304 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::rresp_t() {
+
305  this->r_valid.write(false);
+
306  wait(sc_core::SC_ZERO_TIME);
+
307  fsm_handle* fsm_hndl;
+
308  uint8_t val;
+
309  while(true) {
+
310  // rresp_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
311  std::tie(val, fsm_hndl) = rresp_vl.get();
+
312  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat count = " << fsm_hndl->beat_count;
+
313  SCCTRACE(SCMOD) << __FUNCTION__ << " got read response beat of trans " << *fsm_hndl->trans;
+
314  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
315  this->r_data.write(get_read_data_for_beat(fsm_hndl));
+
316  this->r_resp.write(ext->get_cresp());
+
317  this->r_valid.write(val & 0x1);
+
318  if(!CFG::IS_LITE) {
+
319  this->r_id->write(ext->get_id());
+
320  this->r_last->write(val & 0x2);
+
321  }
+
322  do {
+
323  wait(this->r_ready.posedge_event() | clk_delayed);
+
324  if(this->r_ready.read()) {
+
325  auto evt =
+
326  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
327  react(evt, active_resp_beat[tlm::TLM_READ_COMMAND]);
+
328  }
+
329  } while(!this->r_ready.read());
+
330  SCCTRACE(SCMOD) << "finished read response beat of trans [" << fsm_hndl->trans << "]";
+
331  wait(clk_i.posedge_event());
+
332  this->r_valid.write(false);
+
333  if(!CFG::IS_LITE)
+
334  this->r_last->write(false);
+
335  }
+
336 }
+
337 
+
338 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::aw_t() {
+
339  this->aw_ready.write(false);
+
340  wait(sc_core::SC_ZERO_TIME);
+
341  const auto awsize = util::ilog2(CFG::BUSWIDTH / 8);
+
342  while(true) {
+
343  wait(this->aw_valid.posedge_event() | clk_delayed);
+
344  if(this->aw_valid.event() || (!active_req_beat[tlm::TLM_IGNORE_COMMAND] && this->aw_valid.read())) {
+
345  SCCTRACE(SCMOD) << "AWVALID detected for 0x" << std::hex << this->aw_addr.read();
+
346  // clang-format off
+
347  aw_data awd = {CFG::IS_LITE ? 0U : this->aw_id->read().to_uint(),
+
348  this->aw_addr.read().to_uint64(),
+
349  this->aw_prot.read().to_uint(),
+
350  this->aw_size->read().to_uint(),
+
351  this->aw_cache->read().to_uint(),
+
352  this->aw_burst->read().to_uint(),
+
353  this->aw_qos->read().to_uint(),
+
354  this->aw_region->read().to_uint(),
+
355  this->aw_len->read().to_uint(),
+
356  this->aw_domain->read().to_uint(),
+
357  this->aw_snoop->read().to_uint(),
+
358  this->aw_bar->read().to_uint(),
+
359  this->aw_unique->read(),
+
360  this->aw_stashniden->read() ? 0U : this->aw_stashnid->read().to_uint(),
+
361  this->aw_stashlpiden->read()? 0U : this->aw_stashlpid->read().to_uint(),
+
362  this->aw_lock->read() ? true : false,
+
363  0};
+
364  // clang-format on
+
365  aw_que.notify(awd);
+
366  this->aw_ready.write(true);
+
367  wait(clk_i.posedge_event());
+
368  this->aw_ready.write(false);
+
369  }
+
370  }
+
371 }
+
372 
+
373 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::wdata_t() {
+
374  this->w_ready.write(false);
+
375  wait(sc_core::SC_ZERO_TIME);
+
376  while(true) {
+
377  wait(this->w_valid.posedge_event() | clk_delayed);
+
378  this->w_ready.write(false);
+
379  if(this->w_valid.event() || (!active_req_beat[tlm::TLM_WRITE_COMMAND] && this->w_valid.read())) {
+
380  if(!active_req[tlm::TLM_WRITE_COMMAND]) {
+
381  if(!aw_que.has_next())
+
382  wait(aw_que.event());
+
383  auto awd = aw_que.get();
+
384  auto data_len = (1 << awd.size) * (awd.len + 1);
+
385  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
386  gp->set_address(awd.addr);
+
387  gp->set_command(tlm::TLM_WRITE_COMMAND);
+
388  axi::ace_extension* ext;
+
389  gp->get_extension(ext);
+
390  ext->set_id(awd.id);
+
391  ext->set_length(awd.len);
+
392  ext->set_size(awd.size);
+
393  ext->set_burst(axi::into<axi::burst_e>(awd.burst));
+
394  ext->set_prot(awd.prot);
+
395  ext->set_qos(awd.qos);
+
396  ext->set_cache(awd.cache);
+
397  ext->set_region(awd.region);
+
398  ext->set_snoop(axi::into<axi::snoop_e>(awd.snoop));
+
399  ext->set_barrier(axi::into<axi::bar_e>(awd.bar));
+
400  // ace_lite does not have aw_unique ext->set_unique(awd.unique);
+
401  ext->set_stash_nid(awd.stashnid);
+
402  ext->set_stash_lpid(awd.stashlpid);
+
403  ext->set_exclusive(awd.lock);
+
404  if(CFG::USERWIDTH)
+
405  ext->set_user(axi::common::id_type::CTRL, awd.user);
+
406  active_req_beat[tlm::TLM_WRITE_COMMAND] = find_or_create(gp);
+
407  active_req[tlm::TLM_WRITE_COMMAND] = active_req_beat[tlm::TLM_WRITE_COMMAND];
+
408  }
+
409  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
410  SCCTRACE(SCMOD) << "WDATA detected for 0x" << std::hex << this->ar_addr.read();
+
411  auto& gp = fsm_hndl->trans;
+
412  auto data = this->w_data.read();
+
413  auto strb = this->w_strb.read();
+
414  auto last = this->w_last->read();
+
415  auto beat_count = fsm_hndl->beat_count;
+
416  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
417  auto byte_offset = beat_count * size;
+
418  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
419  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
420  if(beat_count == 0) {
+
421  auto dptr = fsm_hndl->trans->get_data_ptr();
+
422  auto beptr = fsm_hndl->trans->get_byte_enable_ptr();
+
423  for(size_t i = offset; i < size; ++i, ++dptr, ++beptr) {
+
424  auto bit_offs = i * 8;
+
425  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
426  *beptr = strb[i] ? 0xff : 0;
+
427  }
+
428  } else {
+
429  auto beat_start_idx = byte_offset - offset;
+
430  auto data_len = fsm_hndl->trans->get_data_length();
+
431  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
432  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + beat_start_idx;
+
433  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr, ++beptr) {
+
434  auto bit_offs = i * 8;
+
435  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
436  *beptr = strb[i] ? 0xff : 0;
+
437  }
+
438  }
+
439  } else { // aligned or single beat access
+
440  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
441  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + byte_offset;
+
442  for(size_t i = 0; i < size; ++i, ++dptr, ++beptr) {
+
443  auto bit_offs = (offset + i) * 8;
+
444  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
445  *beptr = strb[offset + i] ? 0xff : 0;
+
446  }
+
447  }
+
448  // TODO: assuming consecutive write (not scattered)
+
449  auto strobe = strb.to_uint();
+
450  if(last) {
+
451  auto act_data_len = CFG::IS_LITE ? util::bit_count(strobe) : (beat_count + 1) * size;
+
452  // if(CFG::IS_LITE && act_data_len<CFG::BUSWIDTH/8) {
+
453  // std::fill(gp->get_byte_enable_ptr(), gp->get_byte_enable_ptr() + act_data_len, 0xff);
+
454  // std::fill(gp->get_byte_enable_ptr() + act_data_len, gp->get_byte_enable_ptr() +
+
455  // gp->get_byte_enable_length(), 0x0);
+
456  // }
+
457  gp->set_data_length(act_data_len);
+
458  gp->set_byte_enable_length(act_data_len);
+
459  gp->set_streaming_width(act_data_len);
+
460  }
+
461  auto tp = this->w_last->read() ? axi::fsm::protocol_time_point_e::BegReqE : axi::fsm::protocol_time_point_e::BegPartReqE;
+
462  react(tp, fsm_hndl);
+
463  // notified in EndPartReqE/EndReq
+
464  wait(wdata_end_req_evt);
+
465  this->w_ready.write(true);
+
466  wait(clk_i.posedge_event());
+
467  this->w_ready.write(false);
+
468  if(last)
+
469  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
470  }
+
471  }
+
472 }
+
473 
+
474 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::bresp_t() {
+
475  this->b_valid.write(false);
+
476  wait(sc_core::SC_ZERO_TIME);
+
477  fsm_handle* fsm_hndl;
+
478  uint8_t val;
+
479  while(true) {
+
480  std::tie(val, fsm_hndl) = wresp_vl.get();
+
481  SCCTRACE(SCMOD) << "got write response of trans " << *fsm_hndl->trans;
+
482  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
483  this->b_resp.write(axi::to_int(ext->get_resp()));
+
484  this->b_valid.write(true);
+
485  if(!CFG::IS_LITE)
+
486  this->b_id->write(ext->get_id());
+
487  SCCTRACE(SCMOD) << "got write response";
+
488  do {
+
489  wait(this->b_ready.posedge_event() | clk_delayed);
+
490  if(this->b_ready.read()) {
+
491  react(axi::fsm::protocol_time_point_e::EndRespE, active_resp_beat[tlm::TLM_WRITE_COMMAND]);
+
492  }
+
493  } while(!this->b_ready.read());
+
494  SCCTRACE(SCMOD) << "finished write response of trans [" << fsm_hndl->trans << "]";
+
495  wait(clk_i.posedge_event());
+
496  this->b_valid.write(false);
+
497  }
+
498 }
+
499 
+
500 #endif /* _BUS_AXI_PIN_ace_lite_TARGET_H_ */
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::axi_bw_transport_if
tlm::tlm_bw_transport_if< TYPES > axi_bw_transport_if
alias declaration for the backward interface:
Definition: axi_tlm.h:918
+
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace::set_barrier
void set_barrier(bar_e)
set the AxBAR value
Definition: axi_tlm.h:1449
+
axi::ace::set_domain
void set_domain(domain_e)
set the AxDOMAIN value
Definition: axi_tlm.h:1441
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi4::set_exclusive
void set_exclusive(bool=true)
get the exclusive bit of AxLOCK (AxLOCK[0])
Definition: axi_tlm.h:1324
+
axi::axi_initiator_socket< CFG::BUSWIDTH >
+
axi::b_axi
Definition: signal_if.h:227
+
axi::common::set_id
void set_id(unsigned int value)
Definition: axi_tlm.h:1252
+
axi::common::set_user
void set_user(id_type chnl, unsigned int value)
Definition: axi_tlm.h:1256
+
axi::common::get_id
unsigned int get_id() const
Definition: axi_tlm.h:1254
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::pin::ace_lite_target
Definition: ace_lite_target.h:43
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_qos
void set_qos(uint8_t)
set the AxQOS (quality of service) value
Definition: axi_tlm.h:1426
+
axi::request::set_cache
void set_cache(uint8_t)
set the AxCACHE value as POD, only value from 0..15 are allowed
Definition: axi_tlm.h:1434
+
axi::request::set_region
void set_region(uint8_t)
set the AxREGION value
Definition: axi_tlm.h:1430
+
axi::request::set_stash_lpid
void set_stash_lpid(uint8_t)
set the raw AWSTASHLPID value
Definition: axi_tlm.h:1467
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::request::set_stash_nid
void set_stash_nid(uint8_t)
set the raw AWSTASHNID value
Definition: axi_tlm.h:1461
+
axi::response::get_resp
resp_e get_resp() const
get the response status as POD
Definition: axi_tlm.h:1502
+
axi::rresp_axi
Definition: signal_if.h:308
+
axi::wdata_axi
Definition: signal_if.h:186
+ +
+
+ + + + diff --git a/develop/ace__target_8h_source.html b/develop/ace__target_8h_source.html new file mode 100644 index 00000000..51daa3bb --- /dev/null +++ b/develop/ace__target_8h_source.html @@ -0,0 +1,822 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_TARGET_H_
+
18 #define _BUS_AXI_PIN_ACE_TARGET_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <util/ities.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_target : public sc_core::sc_module,
+
37  public aw_ace<CFG, typename CFG::slave_types>,
+
38  public wdata_ace<CFG, typename CFG::slave_types>,
+
39  public b_ace<CFG, typename CFG::slave_types>,
+
40  public ar_ace<CFG, typename CFG::slave_types>,
+
41  public rresp_ace<CFG, typename CFG::slave_types>,
+
42 
+
43  public ac_ace<CFG, typename CFG::slave_types>,
+
44  public cr_ace<CFG, typename CFG::slave_types>,
+
45  public cd_ace<CFG, typename CFG::slave_types>,
+
46 
+
47  protected axi::fsm::base,
+
48  public axi::ace_bw_transport_if<axi::axi_protocol_types> {
+
49  SC_HAS_PROCESS(ace_target);
+
50 
+
51  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
52  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
53 
+
54  sc_core::sc_in<bool> clk_i{"clk_i"};
+
55 
+
56  axi::ace_initiator_socket<CFG::BUSWIDTH> isckt{"isckt"};
+
57 
+
58  ace_target(sc_core::sc_module_name const& nm)
+
59  : sc_core::sc_module(nm)
+
60  // coherent= true
+
61  , base(CFG::BUSWIDTH, true) {
+
62  instance_name = name();
+
63  isckt.bind(*this);
+
64  SC_METHOD(clk_delay);
+
65  sensitive << clk_i.pos();
+
66  dont_initialize();
+
67  SC_THREAD(ar_t);
+
68  SC_THREAD(rresp_t);
+
69  SC_THREAD(aw_t);
+
70  SC_THREAD(wdata_t);
+
71  SC_THREAD(bresp_t);
+
72  SC_THREAD(ac_t);
+
73  SC_THREAD(cr_t);
+
74  SC_THREAD(cd_t);
+
75  }
+
76 
+
77 private:
+
78  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
79  void b_snoop(payload_type& trans, sc_core::sc_time& t) override{};
+
80 
+
81  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override;
+
82 
+
83  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
84 
+
85  axi::fsm::fsm_handle* create_fsm_handle() override { return new fsm_handle(); }
+
86 
+
87  void setup_callbacks(axi::fsm::fsm_handle*) override;
+
88 
+
94  unsigned snoop_latency{1};
+
95 
+
96  void clk_delay() {
+
97 #ifdef DELTA_SYNC
+
98  if(sc_core::sc_delta_count_at_current_time() < 5) {
+
99  clk_self.notify(sc_core::SC_ZERO_TIME);
+
100  next_trigger(clk_self);
+
101  } else
+
102  clk_delayed.notify(sc_core::SC_ZERO_TIME /*clk_if ? clk_if->period() - 1_ps : 1_ps*/);
+
103 #else
+
104  clk_delayed.notify(axi::CLK_DELAY);
+
105 #endif
+
106  }
+
107  void ar_t();
+
108  void rresp_t();
+
109  void aw_t();
+
110  void wdata_t();
+
111  void bresp_t();
+
112  void ac_t();
+
113  void cr_t();
+
114  void cd_t();
+
115  static typename CFG::data_t get_read_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
116  struct aw_data {
+
117  unsigned id;
+
118  uint64_t addr;
+
119  unsigned prot;
+
120  unsigned size;
+
121  unsigned cache;
+
122  unsigned burst;
+
123  unsigned qos;
+
124  unsigned region;
+
125  unsigned len;
+
126  unsigned domain;
+
127  unsigned snoop;
+
128  unsigned bar;
+
129  unsigned unique;
+
130  bool lock;
+
131  uint64_t user;
+
132  };
+
133 
+
134  std::deque<axi::fsm::fsm_handle*> snp_resp_queue;
+
135 
+
136  sc_core::sc_clock* clk_if{nullptr};
+
137  sc_core::sc_event clk_delayed, clk_self, ar_end_req_evt, wdata_end_req_evt, ac_evt, cd_end_req_evt, cr_end_req_evt;
+
138  std::array<fsm_handle*, 3> active_req_beat{nullptr, nullptr, nullptr};
+
139  std::array<fsm_handle*, 4> active_req{nullptr, nullptr, nullptr};
+
140  std::array<fsm_handle*, 3> active_resp_beat{nullptr, nullptr, nullptr};
+
141  scc::peq<aw_data> aw_que;
+
142  scc::peq<std::tuple<uint8_t, fsm_handle*>> rresp_vl;
+
143  scc::peq<std::tuple<uint8_t, fsm_handle*>> wresp_vl;
+
144  scc::peq<std::tuple<uint8_t, fsm_handle*>> cr_vl; // snoop response
+
145 
+
146  unsigned int SNOOP = 3; // TBD??
+
147  void write_ac(tlm::tlm_generic_payload& trans);
+
148 };
+
149 
+
150 } // namespace pin
+
151 } // namespace axi
+
152 
+
153 template <typename CFG>
+
154 inline tlm::tlm_sync_enum axi::pin::ace_target<CFG>::nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) {
+
155  auto ret = tlm::TLM_ACCEPTED;
+
156  SCCTRACE(SCMOD) << "nb_transport_bw with " << phase << " with delay= " << t << " of trans " << trans;
+
157  if(phase == END_PARTIAL_REQ || phase == tlm::END_REQ) { // read/write
+
158  schedule(phase == tlm::END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
159  } else if(phase == axi::BEGIN_PARTIAL_RESP || phase == tlm::BEGIN_RESP) { // read/write response
+
160  schedule(phase == tlm::BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
161  } else if(phase == tlm::BEGIN_REQ) { // snoop read
+
162  auto fsm_hndl = find_or_create(&trans, true);
+
163  fsm_hndl->is_snoop = true;
+
164  schedule(BegReqE, &trans, t);
+
165  } else if(phase == END_PARTIAL_RESP || phase == tlm::END_RESP) { // snoop read response
+
166  schedule(phase == tlm::END_RESP ? EndRespE : EndPartRespE, &trans, t);
+
167  }
+
168  return ret;
+
169 }
+
170 
+
171 template <typename CFG>
+
172 inline void axi::pin::ace_target<CFG>::invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) {}
+
173 
+
174 template <typename CFG> typename CFG::data_t axi::pin::ace_target<CFG>::get_read_data_for_beat(fsm_handle* fsm_hndl) {
+
175  auto beat_count = fsm_hndl->beat_count;
+
176  // SCCTRACE(SCMOD) << " " ;
+
177  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
178  auto byte_offset = beat_count * size;
+
179  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
180  typename CFG::data_t data{0};
+
181  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
182  if(beat_count == 0) {
+
183  auto dptr = fsm_hndl->trans->get_data_ptr();
+
184  for(size_t i = offset; i < size; ++i, ++dptr) {
+
185  auto bit_offs = i * 8;
+
186  data(bit_offs + 7, bit_offs) = *dptr;
+
187  }
+
188  } else {
+
189  auto beat_start_idx = byte_offset - offset;
+
190  auto data_len = fsm_hndl->trans->get_data_length();
+
191  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
192  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
193  auto bit_offs = i * 8;
+
194  data(bit_offs + 7, bit_offs) = *dptr;
+
195  }
+
196  }
+
197  } else { // aligned or single beat access
+
198  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
199  for(size_t i = 0; i < size; ++i, ++dptr) {
+
200  auto bit_offs = (offset + i) * 8;
+
201  data(bit_offs + 7, bit_offs) = *dptr;
+
202  }
+
203  }
+
204  return data;
+
205 }
+
206 
+
207 template <typename CFG> inline void axi::pin::ace_target<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
208  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void { fsm_hndl->beat_count = 0; };
+
209  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
210  sc_assert(fsm_hndl->trans->get_command() == tlm::TLM_WRITE_COMMAND);
+
211  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_REQ;
+
212  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
213  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
214  if(ret == tlm::TLM_UPDATED) {
+
215  schedule(EndPartReqE, fsm_hndl->trans, t, true);
+
216  }
+
217  };
+
218  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
219  wdata_end_req_evt.notify();
+
220  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
221  fsm_hndl->beat_count++;
+
222  };
+
223  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
224  if(fsm_hndl->is_snoop) {
+
225  SCCTRACE(SCMOD) << "in BegReq of setup_cb, call write_ac() ";
+
226  active_req[SNOOP] = fsm_hndl;
+
227  write_ac(*fsm_hndl->trans);
+
228  ac_evt.notify(sc_core::SC_ZERO_TIME);
+
229 
+
230  } else {
+
231  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
232  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
233  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
234  if(ret == tlm::TLM_UPDATED) {
+
235  schedule(EndReqE, fsm_hndl->trans, t, true);
+
236  }
+
237  }
+
238  };
+
239 
+
240  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
241  if(fsm_hndl->is_snoop) {
+
242  SCCTRACE(SCMOD) << "snoop with EndReq evt";
+
243  auto latency = 0;
+
244  snp_resp_queue.push_back(fsm_hndl);
+
245  active_req[SNOOP] = nullptr;
+
246  tlm::tlm_phase phase = tlm::END_REQ;
+
247  // ?? here t(delay) should be zero or clock cycle??
+
248  // sc_core::sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : sc_core::SC_ZERO_TIME);
+
249  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
250  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
251  auto exta = fsm_hndl->trans->get_extension<ace_extension>();
+
252  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
253  } else {
+
254  switch(fsm_hndl->trans->get_command()) {
+
255  case tlm::TLM_READ_COMMAND:
+
256  ar_end_req_evt.notify();
+
257  active_req_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
258  break;
+
259  case tlm::TLM_WRITE_COMMAND:
+
260  wdata_end_req_evt.notify();
+
261  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
262  fsm_hndl->beat_count++;
+
263  break;
+
264  default:
+
265  break;
+
266  }
+
267  }
+
268  };
+
269  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
270  if(fsm_hndl->is_snoop) {
+
271  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
272  sc_core::sc_time t;
+
273  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
274 
+
275  } else {
+
276  assert(fsm_hndl->trans->is_read());
+
277  active_resp_beat[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
278  rresp_vl.notify({1, fsm_hndl});
+
279  }
+
280  };
+
281  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
282  if(fsm_hndl->is_snoop) {
+
283  fsm_hndl->beat_count++;
+
284  cd_end_req_evt.notify();
+
285 
+
286  } else {
+
287  // scheduling the response
+
288  assert(fsm_hndl->trans->is_read());
+
289  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
290  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
291  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
292  active_resp_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
293  fsm_hndl->beat_count++;
+
294  }
+
295  };
+
296  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
297  SCCTRACE(SCMOD) << "processing event BegRespE for trans " << *fsm_hndl->trans;
+
298  if(fsm_hndl->is_snoop) {
+
299  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
300  sc_core::sc_time t;
+
301  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
302  } else {
+
303  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
304  active_resp_beat[fsm_hndl->trans->get_command()] = fsm_hndl;
+
305  switch(fsm_hndl->trans->get_command()) {
+
306  case tlm::TLM_READ_COMMAND:
+
307  rresp_vl.notify({3, fsm_hndl});
+
308  break;
+
309  case tlm::TLM_WRITE_COMMAND:
+
310  wresp_vl.notify({3, fsm_hndl});
+
311  break;
+
312  default:
+
313  break;
+
314  }
+
315  }
+
316  };
+
317  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
318  if(fsm_hndl->is_snoop) {
+
319  SCCTRACE(SCMOD) << " in EndRespE ";
+
320  cd_end_req_evt.notify();
+
321  cr_end_req_evt.notify(); // need to check these two event??
+
322  snp_resp_queue.pop_front();
+
323  fsm_hndl->finish.notify();
+
324 
+
325  } else {
+
326  // scheduling the response
+
327  tlm::tlm_phase phase = tlm::END_RESP;
+
328  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
329  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
330  SCCTRACE(SCMOD) << "EndResp of setup_cb with coherent = " << coherent;
+
331  if(coherent)
+
332  schedule(Ack, fsm_hndl->trans, t); // later can add ack_resp_delay to replace t
+
333  else {
+
334  fsm_hndl->finish.notify();
+
335  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
336  }
+
337  }
+
338  };
+
339  fsm_hndl->fsm->cb[Ack] = [this, fsm_hndl]() -> void {
+
340  SCCTRACE(SCMOD) << " in Ack of setup_cb";
+
341  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
342  tlm::tlm_phase phase = axi::ACK;
+
343  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
344  fsm_hndl->finish.notify();
+
345  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
346  };
+
347 }
+
348 
+
349 template <typename CFG> inline void axi::pin::ace_target<CFG>::ar_t() {
+
350  this->ar_ready.write(false);
+
351  wait(sc_core::SC_ZERO_TIME);
+
352  auto arid = 0U;
+
353  auto arlen = 0U;
+
354  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
355 
+
356  auto data_len = (1 << arsize) * (arlen + 1);
+
357  while(true) {
+
358  wait(this->ar_valid.posedge_event() | clk_delayed);
+
359  if(this->ar_valid.read()) {
+
360  SCCTRACE(SCMOD) << "ARVALID detected for 0x" << std::hex << this->ar_addr.read();
+
361  if(!CFG::IS_LITE) {
+
362  arid = this->ar_id->read().to_uint();
+
363  arlen = this->ar_len->read().to_uint();
+
364  arsize = this->ar_size->read().to_uint();
+
365  }
+
366  data_len = (1 << arsize) * (arlen + 1);
+
367  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len);
+
368  gp->set_address(this->ar_addr.read());
+
369  gp->set_command(tlm::TLM_READ_COMMAND);
+
370  gp->set_streaming_width(data_len);
+
371  axi::ace_extension* ext;
+
372  gp->get_extension(ext);
+
373  ext->set_id(arid);
+
374  ext->set_length(arlen);
+
375  ext->set_size(arsize);
+
376  if(this->ar_lock->read())
+
377  ext->set_exclusive(true);
+
378  ext->set_domain(axi::into<axi::domain_e>(this->ar_domain->read())); // ace extension
+
379  ext->set_snoop(axi::into<axi::snoop_e>(this->ar_snoop->read()));
+
380  ext->set_barrier(axi::into<axi::bar_e>(this->ar_bar->read()));
+
381  ext->set_burst(CFG::IS_LITE ? axi::burst_e::INCR : axi::into<axi::burst_e>(this->ar_burst->read()));
+
382  ext->set_cache(this->ar_cache->read());
+
383  ext->set_prot(this->ar_prot->read());
+
384  ext->set_qos(this->ar_qos->read());
+
385  ext->set_region(this->ar_region->read());
+
386 
+
387  active_req_beat[tlm::TLM_READ_COMMAND] = find_or_create(gp);
+
388  react(axi::fsm::protocol_time_point_e::BegReqE, active_req_beat[tlm::TLM_READ_COMMAND]);
+
389  wait(ar_end_req_evt);
+
390  this->ar_ready.write(true);
+
391  wait(clk_i.posedge_event());
+
392  this->ar_ready.write(false);
+
393  }
+
394  }
+
395 }
+
396 
+
397 template <typename CFG> inline void axi::pin::ace_target<CFG>::rresp_t() {
+
398  this->r_valid.write(false);
+
399  wait(sc_core::SC_ZERO_TIME);
+
400  fsm_handle* fsm_hndl;
+
401  uint8_t val;
+
402  while(true) {
+
403  // rresp_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
404  std::tie(val, fsm_hndl) = rresp_vl.get();
+
405  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat count = " << fsm_hndl->beat_count;
+
406  SCCTRACE(SCMOD) << __FUNCTION__ << " got read response beat of trans " << *fsm_hndl->trans;
+
407  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
408  this->r_data.write(get_read_data_for_beat(fsm_hndl));
+
409  this->r_resp.write(ext->get_cresp());
+
410  this->r_valid.write(val & 0x1);
+
411  if(!CFG::IS_LITE) {
+
412  this->r_id->write(ext->get_id());
+
413  this->r_last->write(val & 0x2);
+
414  }
+
415  do {
+
416  wait(this->r_ready.posedge_event() | clk_delayed);
+
417  if(this->r_ready.read()) {
+
418  auto evt =
+
419  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
420  react(evt, active_resp_beat[tlm::TLM_READ_COMMAND]);
+
421  }
+
422  } while(!this->r_ready.read());
+
423  SCCTRACE(SCMOD) << "finished read response beat of trans [" << fsm_hndl->trans << "]";
+
424  wait(clk_i.posedge_event());
+
425  this->r_valid.write(false);
+
426  if(!CFG::IS_LITE)
+
427  this->r_last->write(false);
+
428  }
+
429 }
+
430 
+
431 template <typename CFG> inline void axi::pin::ace_target<CFG>::aw_t() {
+
432  this->aw_ready.write(false);
+
433  wait(sc_core::SC_ZERO_TIME);
+
434  const auto awsize = util::ilog2(CFG::BUSWIDTH / 8);
+
435  while(true) {
+
436  wait(this->aw_valid.posedge_event() | clk_delayed);
+
437  if(this->aw_valid.event() || (!active_req_beat[tlm::TLM_IGNORE_COMMAND] && this->aw_valid.read())) {
+
438  SCCTRACE(SCMOD) << "AWVALID detected for 0x" << std::hex << this->aw_addr.read();
+
439  // clang-format off
+
440  aw_data awd = {CFG::IS_LITE ? 0U : this->aw_id->read().to_uint(),
+
441  this->aw_addr.read().to_uint64(),
+
442  this->aw_prot.read().to_uint(),
+
443  CFG::IS_LITE ? awsize : this->aw_size->read().to_uint(),
+
444  CFG::IS_LITE ? 0U : this->aw_cache->read().to_uint(),
+
445  CFG::IS_LITE ? 0U : this->aw_burst->read().to_uint(),
+
446  CFG::IS_LITE ? 0U : this->aw_qos->read().to_uint(),
+
447  CFG::IS_LITE ? 0U : this->aw_region->read().to_uint(),
+
448  CFG::IS_LITE ? 0U : this->aw_len->read().to_uint(),
+
449  CFG::IS_LITE ? 0U : this->aw_domain->read().to_uint(),
+
450  CFG::IS_LITE ? 0U : this->aw_snoop->read().to_uint(),
+
451  CFG::IS_LITE ? 0U : this->aw_bar->read().to_uint(),
+
452  CFG::IS_LITE ? 0U : this->aw_unique->read(),
+
453  CFG::IS_LITE ? false : this->aw_lock->read(),
+
454  0};
+
455  // clang-format on
+
456  aw_que.notify(awd);
+
457  this->aw_ready.write(true);
+
458  wait(clk_i.posedge_event());
+
459  this->aw_ready.write(false);
+
460  }
+
461  }
+
462 }
+
463 
+
464 template <typename CFG> inline void axi::pin::ace_target<CFG>::wdata_t() {
+
465  this->w_ready.write(false);
+
466  wait(sc_core::SC_ZERO_TIME);
+
467  while(true) {
+
468  wait(this->w_valid.posedge_event() | clk_delayed);
+
469  this->w_ready.write(false);
+
470  if(this->w_valid.event() || (!active_req_beat[tlm::TLM_WRITE_COMMAND] && this->w_valid.read())) {
+
471  if(!active_req[tlm::TLM_WRITE_COMMAND]) {
+
472  if(!aw_que.has_next())
+
473  wait(aw_que.event());
+
474  auto awd = aw_que.get();
+
475  auto data_len = (1 << awd.size) * (awd.len + 1);
+
476  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
477  gp->set_address(awd.addr);
+
478  gp->set_command(tlm::TLM_WRITE_COMMAND);
+
479  axi::ace_extension* ext;
+
480  gp->get_extension(ext);
+
481  ext->set_id(awd.id);
+
482  ext->set_length(awd.len);
+
483  ext->set_size(awd.size);
+
484  ext->set_burst(axi::into<axi::burst_e>(awd.burst));
+
485  ext->set_prot(awd.prot);
+
486  ext->set_qos(awd.qos);
+
487  ext->set_cache(awd.cache);
+
488  ext->set_region(awd.region);
+
489  ext->set_snoop(axi::into<axi::snoop_e>(awd.snoop));
+
490  ext->set_barrier(axi::into<axi::bar_e>(awd.bar));
+
491  ext->set_unique(awd.unique);
+
492  ext->set_exclusive(awd.lock);
+
493  if(CFG::USERWIDTH)
+
494  ext->set_user(axi::common::id_type::CTRL, awd.user);
+
495 
+
496  active_req_beat[tlm::TLM_WRITE_COMMAND] = find_or_create(gp);
+
497  active_req[tlm::TLM_WRITE_COMMAND] = active_req_beat[tlm::TLM_WRITE_COMMAND];
+
498  }
+
499  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
500  SCCTRACE(SCMOD) << "WDATA detected for 0x" << std::hex << this->ar_addr.read();
+
501  auto& gp = fsm_hndl->trans;
+
502  auto data = this->w_data.read();
+
503  auto strb = this->w_strb.read();
+
504  auto last = CFG::IS_LITE ? true : this->w_last->read();
+
505  auto beat_count = fsm_hndl->beat_count;
+
506  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
507  auto byte_offset = beat_count * size;
+
508  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
509  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
510  if(beat_count == 0) {
+
511  auto dptr = fsm_hndl->trans->get_data_ptr();
+
512  auto beptr = fsm_hndl->trans->get_byte_enable_ptr();
+
513  for(size_t i = offset; i < size; ++i, ++dptr, ++beptr) {
+
514  auto bit_offs = i * 8;
+
515  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
516  *beptr = strb[i] ? 0xff : 0;
+
517  }
+
518  } else {
+
519  auto beat_start_idx = byte_offset - offset;
+
520  auto data_len = fsm_hndl->trans->get_data_length();
+
521  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
522  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + beat_start_idx;
+
523  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr, ++beptr) {
+
524  auto bit_offs = i * 8;
+
525  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
526  *beptr = strb[i] ? 0xff : 0;
+
527  }
+
528  }
+
529  } else { // aligned or single beat access
+
530  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
531  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + byte_offset;
+
532  for(size_t i = 0; i < size; ++i, ++dptr, ++beptr) {
+
533  auto bit_offs = (offset + i) * 8;
+
534  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
535  *beptr = strb[offset + i] ? 0xff : 0;
+
536  }
+
537  }
+
538  // TODO: assuming consecutive write (not scattered)
+
539  auto strobe = strb.to_uint();
+
540  if(last) {
+
541  auto act_data_len = CFG::IS_LITE ? util::bit_count(strobe) : (beat_count + 1) * size;
+
542  // if(CFG::IS_LITE && act_data_len<CFG::BUSWIDTH/8) {
+
543  // std::fill(gp->get_byte_enable_ptr(), gp->get_byte_enable_ptr() + act_data_len, 0xff);
+
544  // std::fill(gp->get_byte_enable_ptr() + act_data_len, gp->get_byte_enable_ptr() +
+
545  // gp->get_byte_enable_length(), 0x0);
+
546  // }
+
547  gp->set_data_length(act_data_len);
+
548  gp->set_byte_enable_length(act_data_len);
+
549  gp->set_streaming_width(act_data_len);
+
550  }
+
551  auto tp = CFG::IS_LITE || this->w_last->read() ? axi::fsm::protocol_time_point_e::BegReqE
+
552  : axi::fsm::protocol_time_point_e::BegPartReqE;
+
553  react(tp, fsm_hndl);
+
554  // notifed in EndPartReqE/EndReq
+
555  wait(wdata_end_req_evt);
+
556  this->w_ready.write(true);
+
557  wait(clk_i.posedge_event());
+
558  this->w_ready.write(false);
+
559  if(last)
+
560  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
561  }
+
562  }
+
563 }
+
564 
+
565 template <typename CFG> inline void axi::pin::ace_target<CFG>::bresp_t() {
+
566  this->b_valid.write(false);
+
567  wait(sc_core::SC_ZERO_TIME);
+
568  fsm_handle* fsm_hndl;
+
569  uint8_t val;
+
570  while(true) {
+
571  std::tie(val, fsm_hndl) = wresp_vl.get();
+
572  SCCTRACE(SCMOD) << "got write response of trans " << *fsm_hndl->trans;
+
573  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
574  this->b_resp.write(axi::to_int(ext->get_resp()));
+
575  this->b_valid.write(true);
+
576  if(!CFG::IS_LITE)
+
577  this->b_id->write(ext->get_id());
+
578  SCCTRACE(SCMOD) << "got write response";
+
579  do {
+
580  wait(this->b_ready.posedge_event() | clk_delayed);
+
581  if(this->b_ready.read()) {
+
582  react(axi::fsm::protocol_time_point_e::EndRespE, active_resp_beat[tlm::TLM_WRITE_COMMAND]);
+
583  }
+
584  } while(!this->b_ready.read());
+
585  SCCTRACE(SCMOD) << "finished write response of trans [" << fsm_hndl->trans << "]";
+
586  wait(clk_i.posedge_event());
+
587  this->b_valid.write(false);
+
588  }
+
589 }
+
590 
+
591 // write snoop address
+
592 template <typename CFG> inline void axi::pin::ace_target<CFG>::write_ac(tlm::tlm_generic_payload& trans) {
+
593  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
594  this->ac_addr.write(addr);
+
595  auto ext = trans.get_extension<ace_extension>();
+
596  sc_assert(ext && "No ACE extension found for snoop access");
+
597  this->ac_prot.write(ext->get_prot());
+
598  this->ac_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
599 }
+
600 
+
601 template <typename CFG> inline void axi::pin::ace_target<CFG>::ac_t() {
+
602  this->ac_valid.write(false);
+
603  wait(sc_core::SC_ZERO_TIME);
+
604  while(true) {
+
605  wait(ac_evt);
+
606  this->ac_valid.write(true);
+
607  do {
+
608  wait(this->ac_ready.posedge_event() | clk_delayed);
+
609  if(this->ac_ready.read()) {
+
610  SCCTRACE(SCMOD) << "in ac_t() detect ac_ready high , schedule EndReq";
+
611  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[SNOOP]);
+
612  }
+
613  } while(!this->ac_ready.read());
+
614  wait(clk_i.posedge_event());
+
615  this->ac_valid.write(false);
+
616  }
+
617 }
+
618 
+
619 template <typename CFG> inline void axi::pin::ace_target<CFG>::cd_t() {
+
620  this->cd_ready.write(false);
+
621  wait(sc_core::SC_ZERO_TIME);
+
622  while(true) {
+
623  wait(this->cd_valid.posedge_event() | clk_delayed);
+
624  if(this->cd_valid.read()) {
+
625  SCCTRACE(SCMOD) << "in cd_t(), received cd_valid high ";
+
626  wait(sc_core::SC_ZERO_TIME);
+
627  auto data = this->cd_data.read();
+
628  if(snp_resp_queue.empty())
+
629  sc_assert(" snp_resp_queue empty");
+
630  auto* fsm_hndl = snp_resp_queue.front();
+
631  auto beat_count = fsm_hndl->beat_count;
+
632  SCCTRACE(SCMOD) << "in cd_t(), received beau_count = " << fsm_hndl->beat_count;
+
633  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
634  auto byte_offset = beat_count * size;
+
635  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
636  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
637  if(beat_count == 0) {
+
638  auto dptr = fsm_hndl->trans->get_data_ptr();
+
639  for(size_t i = offset; i < size; ++i, ++dptr) {
+
640  auto bit_offs = i * 8;
+
641  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
642  }
+
643  } else {
+
644  auto beat_start_idx = beat_count * size - offset;
+
645  auto data_len = fsm_hndl->trans->get_data_length();
+
646  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
647  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
648  auto bit_offs = i * 8;
+
649  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
650  }
+
651  }
+
652  } else { // aligned or single beat access
+
653  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
654  for(size_t i = 0; i < size; ++i, ++dptr) {
+
655  auto bit_offs = (offset + i) * 8;
+
656  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
657  }
+
658  }
+
659  /*
+
660  axi::ace_extension* e;
+
661  fsm_hndl->trans->get_extension(e);
+
662  e->set_resp(axi::into<axi::resp_e>(resp));
+
663  e->add_to_response_array(*e);
+
664  */
+
665  auto tp = CFG::IS_LITE || this->cd_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
666  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
667  if(!this->cd_last->read()) // only react BegPartRespE
+
668  react(tp, fsm_hndl);
+
669  // cd_end_req_evt notified in EndPartRespE or EndResp
+
670  wait(cd_end_req_evt);
+
671  this->cd_ready.write(true);
+
672  wait(clk_i.posedge_event());
+
673  this->cd_ready.write(false);
+
674  }
+
675  }
+
676 }
+
677 
+
678 template <typename CFG> inline void axi::pin::ace_target<CFG>::cr_t() {
+
679  this->cr_ready.write(false);
+
680  wait(sc_core::SC_ZERO_TIME);
+
681  while(true) {
+
682  wait(this->cr_valid.posedge_event() | clk_delayed);
+
683  if(this->cr_valid.read()) {
+
684  SCCTRACE(SCMOD) << "in cr_t() received cr_valid high ";
+
685  wait(sc_core::SC_ZERO_TIME);
+
686 
+
687  auto* fsm_hndl = snp_resp_queue.front();
+
688  auto crresp = this->cr_resp.read();
+
689  axi::ace_extension* e;
+
690  fsm_hndl->trans->get_extension(e);
+
691  e->set_cresp(crresp);
+
692 
+
693  SCCTRACE(SCMOD) << " in cr_t() react() with BegRespE ";
+
694  // hongyu TBD?? schedule BegResp??
+
695  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
696  wait(cr_end_req_evt); // notify in EndResp
+
697  this->cr_ready.write(true);
+
698  wait(clk_i.posedge_event());
+
699  this->cr_ready.write(false);
+
700  }
+
701  }
+
702 }
+
703 
+
704 #endif /* _BUS_AXI_PIN_ACE_TARGET_H_ */
+
axi::ace_bw_transport_if
Definition: axi_tlm.h:926
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+ +
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ac_ace
snoop address(AC) channel signals
Definition: signal_if.h:629
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_initiator_socket< CFG::BUSWIDTH >
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace::set_barrier
void set_barrier(bar_e)
set the AxBAR value
Definition: axi_tlm.h:1449
+
axi::ace::set_domain
void set_domain(domain_e)
set the AxDOMAIN value
Definition: axi_tlm.h:1441
+
axi::ace::set_unique
void set_unique(bool)
set the AxUNIQUE value
Definition: axi_tlm.h:1453
+
axi::ace::get_snoop
snoop_e get_snoop() const
get the AxSNOOP value return the snoop value
Definition: axi_tlm.h:1447
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi4::set_exclusive
void set_exclusive(bool=true)
get the exclusive bit of AxLOCK (AxLOCK[0])
Definition: axi_tlm.h:1324
+
axi::b_axi
Definition: signal_if.h:227
+
axi::cd_ace
snoop data(cd) channel signals
Definition: signal_if.h:658
+
axi::common::set_id
void set_id(unsigned int value)
Definition: axi_tlm.h:1252
+
axi::common::set_user
void set_user(id_type chnl, unsigned int value)
Definition: axi_tlm.h:1256
+
axi::common::get_id
unsigned int get_id() const
Definition: axi_tlm.h:1254
+
axi::cr_ace
snoop response(cr) channel signals
Definition: signal_if.h:680
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
axi::pin::ace_target
Definition: ace_target.h:48
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_qos
void set_qos(uint8_t)
set the AxQOS (quality of service) value
Definition: axi_tlm.h:1426
+
axi::request::set_cache
void set_cache(uint8_t)
set the AxCACHE value as POD, only value from 0..15 are allowed
Definition: axi_tlm.h:1434
+
axi::request::set_region
void set_region(uint8_t)
set the AxREGION value
Definition: axi_tlm.h:1430
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::get_prot
uint8_t get_prot() const
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1400
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::response::get_resp
resp_e get_resp() const
get the response status as POD
Definition: axi_tlm.h:1502
+
axi::rresp_ace
Definition: signal_if.h:344
+
axi::wdata_axi
Definition: signal_if.h:186
+ +
+
+ + + + diff --git a/develop/ace__target__pe_8cpp_source.html b/develop/ace__target__pe_8cpp_source.html new file mode 100644 index 00000000..7c8842d6 --- /dev/null +++ b/develop/ace__target__pe_8cpp_source.html @@ -0,0 +1,286 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/ace_target_pe.cpp Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target_pe.cpp
+
+
+
1 /*
+
2  * Copyright 2020 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #ifndef SC_INCLUDE_DYNAMIC_PROCESSES
+
18 #define SC_INCLUDE_DYNAMIC_PROCESSES
+
19 #endif
+
20 
+
21 #include <axi/pe/ace_target_pe.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/fsm/types.h>
+
24 #include <scc/report.h>
+
25 #include <scc/utilities.h>
+
26 #include <systemc>
+
27 #include <tuple>
+
28 
+
29 using namespace sc_core;
+
30 using namespace tlm;
+
31 using namespace axi;
+
32 using namespace axi::fsm;
+
33 using namespace axi::pe;
+
34 
+
35 /******************************************************************************
+
36  * target
+
37  ******************************************************************************/
+
38 struct ace_target_pe::bw_intor_impl : public tlm::scc::pe::intor_bw_nb {
+
39  ace_target_pe* const that;
+
40  bw_intor_impl(ace_target_pe* that)
+
41  : that(that) {}
+
42  unsigned transport(tlm::tlm_generic_payload& payload) override {
+
43  if((payload.is_read() && that->rd_resp_fifo.num_free())){
+
44  that->rd_resp_fifo.write(&payload);
+
45  return 0;
+
46  } else if((payload.is_write() && that->wr_resp_fifo.num_free())){
+
47  that->wr_resp_fifo.write(&payload);
+
48  return 0;
+
49  }
+
50  return std::numeric_limits<unsigned>::max();
+
51  }
+
52 };
+
53 
+
54 SC_HAS_PROCESS(ace_target_pe);
+
55 
+
56 ace_target_pe::ace_target_pe(const sc_core::sc_module_name& nm, size_t transfer_width)
+
57 : sc_module(nm)
+
58 , base(transfer_width, true) // coherent true
+
59 , bw_intor(new bw_intor_impl(this)) {
+
60  isckt_axi.bind(*this);
+
61  instance_name = name();
+
62 
+
63  add_attribute(rd_resp_delay);
+
64  add_attribute(wr_resp_delay);
+
65  bw_i.bind(*bw_intor);
+
66 
+
67  SC_METHOD(fsm_clk_method);
+
68  dont_initialize();
+
69  sensitive << clk_i.pos();
+
70 }
+
71 
+
72 ace_target_pe::~ace_target_pe() = default;
+
73 
+
74 void ace_target_pe::end_of_elaboration() {
+
75  clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface());
+
76 }
+
77 
+
78 void ace_target_pe::start_of_simulation() {
+
79  if (!socket_bw)
+
80  SCCFATAL(SCMOD) << "No backward interface registered!";
+
81 }
+
82 
+
83 
+
84 void ace_target_pe::b_transport(payload_type& trans, sc_time& t) {
+
85  auto latency = operation_cb ? operation_cb(trans) : trans.is_read() ? rd_resp_delay.get_value() : wr_resp_delay.get_value();
+
86  trans.set_dmi_allowed(false);
+
87  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
88  if(clk_if)
+
89  t += clk_if->period() * latency;
+
90 }
+
91 
+
92 tlm_sync_enum ace_target_pe::nb_transport_fw(payload_type& trans, phase_type& phase, sc_time& t) {
+
93  SCCTRACE(SCMOD)<<"in nb_transport_fw receives pahse " << phase;
+
94  auto ret = TLM_ACCEPTED;
+
95  if( phase == END_REQ) { // snoop
+
96  schedule(phase == END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
97  } else if(phase == BEGIN_PARTIAL_RESP || phase == BEGIN_RESP) { // snoop response
+
98  schedule(phase == BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
99  } else { // forward read/Write
+
100  if(phase==axi::ACK)
+
101  return tlm::TLM_COMPLETED;
+
102  SCCTRACE(SCMOD) << " forward via axi_i_sckt, in nb_transport_fw () with phase "<<phase ;
+
103  return isckt_axi->nb_transport_fw(trans, phase, t);
+
104  }
+
105  return ret;
+
106 }
+
107 
+
108 bool ace_target_pe::get_direct_mem_ptr(payload_type& trans, tlm_dmi& dmi_data) {
+
109  trans.set_dmi_allowed(false);
+
110  return false;
+
111 }
+
112 
+
113 unsigned int ace_target_pe::transport_dbg(payload_type& trans) { return 0; }
+
114 
+
115 fsm_handle* ace_target_pe::create_fsm_handle() { return new fsm_handle(); }
+
116 
+
117 void ace_target_pe::setup_callbacks(fsm_handle* fsm_hndl) {
+
118  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
119  fsm_hndl->beat_count = 0;
+
120  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
121  };
+
122  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
123  // for snoop, state will not receive this event
+
124  };
+
125  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
126  // for snoop, state will not receive this event
+
127  };
+
128  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
129  SCCTRACE(SCMOD)<< "in BegReq of setup_cb";
+
130  if(fsm_hndl->is_snoop) {
+
131  sc_time t;
+
132  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
133  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
134  }
+
135  };
+
136  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
137  SCCTRACE(SCMOD)<<" EndReqE in setup_cb";
+
138  };
+
139  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
140  SCCTRACE(SCMOD) <<"in BegPartRespE of setup_cb, ";
+
141  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
142  schedule(EndPartRespE, fsm_hndl->trans, t);
+
143  };
+
144  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
145  SCCTRACE(SCMOD) <<"in EndPartRespE of setup_cb";
+
146  //sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
147  sc_time t(SC_ZERO_TIME);
+
148  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
149  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
150  fsm_hndl->beat_count++;
+
151  };
+
152  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
153  SCCTRACE(SCMOD) <<"in BegRespE of setup_cb";
+
154  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
155  tlm::tlm_phase phase = tlm::END_RESP;
+
156  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
157  t=::scc::time_to_next_posedge(clk_if);
+
158  /* here *3 because after send() of intiator ,there is one cycle wait
+
159  * target here need to wait long cycles so that gp_shared_ptr can be released
+
160  */
+
161  schedule(EndRespE, fsm_hndl->trans, 3*t);
+
162  };
+
163  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
164  /*
+
165  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
166  tlm::tlm_phase phase = tlm::END_RESP;
+
167  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
168  */
+
169  SCCTRACE(SCMOD)<< "notifying finish ";
+
170  fsm_hndl->finish.notify();
+
171  };
+
172  /*TBD threre is ack for snoop_trans
+
173  * */
+
174 }
+
175 
+
176 void ace_target_pe::snoop(payload_type& trans) {
+
177  SCCTRACE(SCMOD) << "got transport snoop trans ";
+
178  bool ace= true;
+
179  fsm_handle* fsm = find_or_create(&trans,true);
+
180  fsm->is_snoop = true;
+
181  react(RequestPhaseBeg, fsm->trans); //
+
182  SCCTRACE(SCMOD) << "started non-blocking protocol";
+
183  sc_core::wait(fsm->finish);
+
184  SCCTRACE(SCMOD) << "finished non-blocking protocol";
+
185 }
+
186 
+
187 
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::ace_target_pe::create_fsm_handle
fsm::fsm_handle * create_fsm_handle() override
Definition: ace_target_pe.cpp:115
+
axi::pe::ace_target_pe::wr_resp_delay
scc::sc_attribute_randomized< int > wr_resp_delay
the latency between request and response phase. Will be overwritten by the return of the callback fun...
Definition: ace_target_pe.h:66
+
axi::pe::ace_target_pe::setup_callbacks
void setup_callbacks(fsm::fsm_handle *) override
Definition: ace_target_pe.cpp:117
+
axi::pe
protocol engine implementations
Definition: ace_target_pe.h:37
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
tlm
SystemC TLM.
Definition: initiator_mixin.h:26
+
axi::pe::ace_target_pe::bw_intor_impl
Definition: ace_target_pe.cpp:38
+
axi::pe::ace_target_pe::bw_intor_impl::transport
unsigned transport(tlm::tlm_generic_payload &payload) override
Definition: ace_target_pe.cpp:42
+ +
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::react
void react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
triggers the FSM with event and given transaction
Definition: base.h:134
+
axi::fsm::base::schedule
void schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling...
Definition: base.h:107
+
axi::fsm::base::find_or_create
axi::fsm::fsm_handle * find_or_create(payload_type *gp=nullptr, bool ace=false)
retrieve the FSM handle based on the transaction passed. If non exist one will be created
Definition: base.cpp:65
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
tlm::scc::pe::intor_bw_nb
Definition: intor_if.h:64
+
+
+ + + + diff --git a/develop/ace__target__pe_8h_source.html b/develop/ace__target__pe_8h_source.html new file mode 100644 index 00000000..000aa57b --- /dev/null +++ b/develop/ace__target__pe_8h_source.html @@ -0,0 +1,227 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/ace_target_pe.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target_pe.h
+
+
+
1 /*
+
2  * Copyright 2020-2022 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #pragma once
+
18 
+
19 #ifndef SC_INCLUDE_DYNAMIC_PROCESSES
+
20 #define SC_INCLUDE_DYNAMIC_PROCESSES
+
21 #endif
+
22 
+
23 #include <array>
+
24 #include <axi/fsm/base.h>
+
25 #include <functional>
+
26 #include <memory>
+
27 #include <scc/ordered_semaphore.h>
+
28 #include <scc/sc_attribute_randomized.h>
+
29 #include <scc/sc_variable.h>
+
30 #include <tlm/scc/pe/intor_if.h>
+
31 #include <tlm_utils/peq_with_cb_and_phase.h>
+
32 #include <unordered_set>
+
33 
+
35 namespace axi {
+
37 namespace pe {
+
41 class ace_target_pe : public sc_core::sc_module,
+
42  protected axi::fsm::base,
+
43  public axi::axi_bw_transport_if<axi::axi_protocol_types>,
+
44  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
45  struct bw_intor_impl;
+
46 public:
+
47 
+
48  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
49  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
50 
+
51  sc_core::sc_in<bool> clk_i{"clk_i"};
+
52 
+
53  // hongyu?? here first hardcoded
+
54  axi::axi_initiator_socket<64> isckt_axi{"isckt_axi"};
+
55 
+
56  sc_core::sc_port<tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND> fw_o{"fw_o"};
+
57 
+
58  sc_core::sc_export<tlm::scc::pe::intor_bw_nb> bw_i{"bw_i"};
+
59 
+
60 
+
61  scc::sc_attribute_randomized<int> rd_resp_delay{"rd_resp_delay", 0};
+
66  scc::sc_attribute_randomized<int> wr_resp_delay{"wr_resp_delay", 0};
+
67 
+
68  void b_transport(payload_type& trans, sc_core::sc_time& t) override;
+
69 
+
70  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
71 
+
72  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override;
+
73 
+
74  unsigned int transport_dbg(payload_type& trans) override;
+
85  void set_operation_cb(std::function<unsigned(payload_type& trans)> cb) { operation_cb = cb; }
+
92  void operation_resp(payload_type& trans, unsigned clk_delay = 0);
+
98  bool is_active() { return !active_fsm.empty(); }
+
104  const sc_core::sc_event& tx_finish_event() { return finish_evt; }
+
105 
+
106  /* overwrite function, defined in axi_bw_transport_if */
+
107  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
108  SCCTRACE(SCMOD) << " in nb_transport_bw () " ;
+
109  return socket_bw->nb_transport_bw(trans, phase, t);
+
110  }
+
111 
+
112  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override {}
+
113 
+
114 
+
115  ~ace_target_pe();
+
116 
+
122  explicit ace_target_pe(const sc_core::sc_module_name& nm, size_t transfer_width);
+
123 
+
124  void set_bw_interface(axi::axi_bw_transport_if<axi_protocol_types>* ifs) {socket_bw=ifs;}
+
125 
+
126  void snoop(payload_type& trans);
+
127 
+
128 protected:
+
129  ace_target_pe() = delete;
+
130 
+
131  ace_target_pe(ace_target_pe const&) = delete;
+
132 
+
133  ace_target_pe(ace_target_pe&&) = delete;
+
134 
+
135  ace_target_pe& operator=(ace_target_pe const&) = delete;
+
136 
+
137  ace_target_pe& operator=(ace_target_pe&&) = delete;
+
138 
+
139  void end_of_elaboration() override;
+
140 
+
141  void start_of_simulation() override;
+
142 
+
143  void fsm_clk_method() { process_fsm_clk_queue(); }
+
147  fsm::fsm_handle* create_fsm_handle() override;
+
151  void setup_callbacks(fsm::fsm_handle*) override;
+
152 
+
153  unsigned operations_callback(payload_type& trans);
+
154 
+
155  axi::axi_bw_transport_if<axi_protocol_types>* socket_bw{nullptr};
+
156  std::function<unsigned(payload_type& trans)> operation_cb;
+
157  sc_core::sc_fifo<payload_type*> rd_resp_fifo{1}, wr_resp_fifo{1};
+
158 
+
159  sc_core::sc_fifo<std::tuple<fsm::fsm_handle*, axi::fsm::protocol_time_point_e>> wr_resp_beat_fifo{128},
+
160  rd_resp_beat_fifo{128};
+
161  scc::ordered_semaphore rd_resp{1}, wr_resp_ch{1}, rd_resp_ch{1};
+
162 
+
163  sc_core::sc_clock* clk_if{nullptr};
+
164  std::unique_ptr<bw_intor_impl> bw_intor;
+
165  std::array<unsigned, 3> outstanding_cnt{{0, 0, 0}}; // count for limiting
+
166 
+
167  void nb_fw(payload_type& trans, const phase_type& phase) {
+
168  auto delay = sc_core::SC_ZERO_TIME;
+
169  base::nb_fw(trans, phase, delay);
+
170  }
+
171  tlm_utils::peq_with_cb_and_phase<ace_target_pe> fw_peq{this, &ace_target_pe::nb_fw};
+
172  std::unordered_set<unsigned> active_rdresp_id;
+
173 
+
174 };
+
175 
+
176 } // namespace pe
+
177 } // namespace axi
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::ace_target_pe::operation_resp
void operation_resp(payload_type &trans, unsigned clk_delay=0)
+
axi::pe::ace_target_pe::create_fsm_handle
fsm::fsm_handle * create_fsm_handle() override
Definition: ace_target_pe.cpp:115
+
axi::pe::ace_target_pe::wr_resp_delay
scc::sc_attribute_randomized< int > wr_resp_delay
the latency between request and response phase. Will be overwritten by the return of the callback fun...
Definition: ace_target_pe.h:66
+
axi::pe::ace_target_pe::set_operation_cb
void set_operation_cb(std::function< unsigned(payload_type &trans)> cb)
Set the operation callback function.
Definition: ace_target_pe.h:85
+
axi::pe::ace_target_pe::ace_target_pe
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)
Definition: ace_target_pe.cpp:56
+
axi::pe::ace_target_pe::setup_callbacks
void setup_callbacks(fsm::fsm_handle *) override
Definition: ace_target_pe.cpp:117
+
axi::pe::ace_target_pe::tx_finish_event
const sc_core::sc_event & tx_finish_event()
Definition: ace_target_pe.h:104
+
axi::pe::ace_target_pe::is_active
bool is_active()
Definition: ace_target_pe.h:98
+
scc::ordered_semaphore
The ordered_semaphore primitive channel class.
Definition: ordered_semaphore.h:44
+
scc::sc_attribute_randomized< int >
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::axi_bw_transport_if
tlm::tlm_bw_transport_if< TYPES > axi_bw_transport_if
alias declaration for the backward interface:
Definition: axi_tlm.h:918
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
axi::pe::ace_target_pe::bw_intor_impl
Definition: ace_target_pe.cpp:38
+
axi::axi_initiator_socket< 64 >
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::process_fsm_clk_queue
void process_fsm_clk_queue()
processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clo...
Definition: base.cpp:107
+
+
+ + + + diff --git a/develop/ahb__tlm_8cpp_source.html b/develop/ahb__tlm_8cpp_source.html new file mode 100644 index 00000000..abde5869 --- /dev/null +++ b/develop/ahb__tlm_8cpp_source.html @@ -0,0 +1,155 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/ahb/ahb_tlm.cpp Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ahb_tlm.cpp
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2019-2023 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #include "ahb_tlm.h"
+
18 
+
19 namespace ahb {
+
20 namespace {
+
21 const std::array<std::string, 3> cmd_str{"R", "W", "I"};
+
22 }
+
23 template <> const char* to_char<burst_e>(burst_e v) {
+
24  switch(v) {
+
25  case burst_e::SINGLE:
+
26  return "SINGLE";
+
27  case burst_e::INCR:
+
28  return "INCR";
+
29  case burst_e::INCR4:
+
30  return "INCR4";
+
31  case burst_e::INCR8:
+
32  return "INCR8";
+
33  case burst_e::INCR16:
+
34  return "INCR16";
+
35  case burst_e::WRAP4:
+
36  return "WRAP4";
+
37  case burst_e::WRAP8:
+
38  return "WRAP8";
+
39  case burst_e::WRAP16:
+
40  return "WRAP16";
+
41  default:
+
42  return "UNKNOWN";
+
43  }
+
44 }
+
45 
+
46 template <> const char* to_char<resp_e>(resp_e v) {
+
47  switch(v) {
+
48  case resp_e::OKAY:
+
49  return "OKAY";
+
50  case resp_e::EXOKAY:
+
51  return "EXOKAY";
+
52  case resp_e::DECERR:
+
53  return "DECERR";
+
54  case resp_e::SLVERR:
+
55  return "SLVERR";
+
56  default:
+
57  return "UNKNOWN";
+
58  }
+
59 }
+
60 
+
61 std::ostream& operator<<(std::ostream& os, const tlm::tlm_generic_payload& t) {
+
62  os << "CMD:" << cmd_str[t.get_command()] << ", "
+
63  << "ADDR:0x" << std::hex << t.get_address() << ", TXLEN:0x" << t.get_data_length();
+
64  if(auto e = t.get_extension<ahb::ahb_extension>()) {
+
65  os << ", "
+
66  << "BURST:" << to_char(e->get_burst()) << ", " << (e->is_seq() ? "SEQ" : "NONSEQ") << ", "
+
67  << "MSTLOCK:" << e->is_locked() << ", "
+
68  << "PROT:0x" << std::hex << static_cast<unsigned>(e->get_protection());
+
69  }
+
70  os << " [ptr:" << &t << "]";
+
71  return os;
+
72 }
+
73 
+
74 } // namespace ahb
+
ahb
TLM2.0 components modeling AHB.
Definition: ahb_tlm.cpp:19
+
ahb::to_char
const char * to_char(E t)
+
ahb::ahb_extension
Definition: ahb_tlm.h:75
+
+
+ + + + diff --git a/develop/cci__param__restricted_8h_source.html b/develop/cci__param__restricted_8h_source.html new file mode 100644 index 00000000..52148620 --- /dev/null +++ b/develop/cci__param__restricted_8h_source.html @@ -0,0 +1,225 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/sysc/scc/cci_param_restricted.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
cci_param_restricted.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2024 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 #ifndef _SCC_CCI_PARAM_RESTRICTED_H_
+
17 #define _SCC_CCI_PARAM_RESTRICTED_H_
+
18 
+
19 #include <cci_cfg/cci_param_typed.h>
+
20 #include <unordered_set>
+
21 
+
22 namespace scc {
+
23 template <typename T> struct _min_max_restriction {
+
24  _min_max_restriction(T min, T max)
+
25  : min(min)
+
26  , max(max) {}
+
27 
+
28  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value >= min && ev.new_value <= max; }
+
29  T const min;
+
30  T const max;
+
31 };
+
32 
+
33 template <typename T> struct _min_max_excl_restriction {
+
34  _min_max_excl_restriction(T min, T max)
+
35  : min(min)
+
36  , max(max) {}
+
37 
+
38  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value > min && ev.new_value < max; }
+
39  T const min;
+
40  T const max;
+
41 };
+
42 
+
43 template <typename T> struct _min_restriction {
+
44  _min_restriction(T min)
+
45  : min(min) {}
+
46 
+
47  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value >= min; }
+
48  T const min;
+
49 };
+
50 
+
51 template <typename T> struct _min_excl_restriction {
+
52  _min_excl_restriction(T min)
+
53  : min(min) {}
+
54 
+
55  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value > min; }
+
56  T const min;
+
57 };
+
58 
+
59 template <typename T> struct _max_restriction {
+
60  _max_restriction(T max)
+
61  : max(max) {}
+
62 
+
63  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value <= max; }
+
64  T const max;
+
65 };
+
66 
+
67 template <typename T> struct _max_excl_restriction {
+
68  _max_excl_restriction(T max)
+
69  : max(max) {}
+
70 
+
71  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value < max; }
+
72  T const max;
+
73 };
+
74 
+
75 template <typename T> struct _discrete_restriction {
+
76  template <typename COLLECTION_TYPE>
+
77  _discrete_restriction(COLLECTION_TYPE values)
+
78  : values(std::begin(values), std::end(values)) {}
+
79 
+
80  bool operator()(cci::cci_param_write_event<T> const& ev) const { return values.count(ev.new_value) > 0; }
+
81  std::unordered_set<T> const values;
+
82 };
+
91 template <typename T> inline _min_max_restriction<T> min_max_restriction(T min, T max) { return _min_max_restriction<T>(min, max); }
+
100 template <typename T> inline _min_max_excl_restriction<T> min_max_excl_restriction(T min, T max) {
+
101  return _min_max_excl_restriction<T>(min, max);
+
102 }
+
110 template <typename T> inline _min_restriction<T> min_restriction(T min) { return _min_restriction<T>(min); }
+
112 template <typename T> inline _min_restriction<T> gte_restriction(T min) { return _min_restriction<T>(min); }
+
120 template <typename T> inline _min_excl_restriction<T> min_excl_restriction(T min) { return _min_excl_restriction<T>(min); }
+
122 template <typename T> inline _min_excl_restriction<T> gt_excl_restriction(T min) { return _min_excl_restriction<T>(min); }
+
130 template <typename T> inline _max_restriction<T> max_restriction(T max) { return _max_restriction<T>(max); }
+
132 template <typename T> inline _max_restriction<T> lte_restriction(T max) { return _max_restriction<T>(max); }
+
140 template <typename T> inline _max_excl_restriction<T> max_excl_restriction(T max) { return _max_excl_restriction<T>(max); }
+
142 template <typename T> inline _max_excl_restriction<T> lt_excl_restriction(T max) { return _max_excl_restriction<T>(max); }
+
150 template <typename T> inline _discrete_restriction<T> discrete_restriction(std::initializer_list<T> values) {
+
151  return _discrete_restriction<T>(values);
+
152 }
+
161 template <typename T, size_t SZ> inline _discrete_restriction<T> discrete_restriction(std::array<T, SZ> values) {
+
162  return _discrete_restriction<T>(values);
+
163 }
+
171 template <typename T> inline _discrete_restriction<T> discrete_restriction(std::vector<T> values) {
+
172  return _discrete_restriction<T>(values);
+
173 }
+
180 template <typename T, cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM> struct cci_param_restricted : public cci::cci_param<T, TM> {
+
181 
+
195  template <typename RESTR>
+
196  cci_param_restricted(const std::string& name, const T& default_value, RESTR const& restr, const std::string& desc = "",
+
197  cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
+
198  const cci::cci_originator& originator = cci::cci_originator())
+
199  : cci::cci_param<T, TM>(name, default_value, desc, name_type, originator) {
+
200  this->template register_pre_write_callback(restr);
+
201  this->template reset();
+
202  }
+
203 
+
216  template <typename RESTR>
+
217  cci_param_restricted(const std::string& name, const T& default_value, RESTR const& restr, cci::cci_broker_handle private_broker,
+
218  const std::string& desc = "", cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
+
219  const cci::cci_originator& originator = cci::cci_originator())
+
220  : cci::cci_param<T, TM>(name, default_value, desc, name_type, originator) {
+
221  this->template register_pre_write_callback(restr);
+
222  this->template reset();
+
223  }
+
225 };
+
226 } // namespace scc
+
227 #endif /* _SCC_CCI_PARAM_RESTRICTED_H_ */
+
scc
SCC SystemC utilities.
Definition: clock_if_mixins.h:25
+
scc::max_excl_restriction
_max_excl_restriction< T > max_excl_restriction(T max)
creates a maximum restriction excluding the maximum value
Definition: cci_param_restricted.h:140
+
scc::max_restriction
_max_restriction< T > max_restriction(T max)
creates a maximum restriction including the maximum value
Definition: cci_param_restricted.h:130
+
scc::gte_restriction
_min_restriction< T > gte_restriction(T min)
alias for min_restriction(T min)
Definition: cci_param_restricted.h:112
+
scc::min_max_restriction
_min_max_restriction< T > min_max_restriction(T min, T max)
creates a min/max restriction with including the limits
Definition: cci_param_restricted.h:91
+
scc::gt_excl_restriction
_min_excl_restriction< T > gt_excl_restriction(T min)
alias for min_excl_restriction(T min)
Definition: cci_param_restricted.h:122
+
scc::discrete_restriction
_discrete_restriction< T > discrete_restriction(std::initializer_list< T > values)
creates a restriction for a discrete values set
Definition: cci_param_restricted.h:150
+
scc::min_restriction
_min_restriction< T > min_restriction(T min)
creates a minimum restriction including the minimum value
Definition: cci_param_restricted.h:110
+
scc::min_excl_restriction
_min_excl_restriction< T > min_excl_restriction(T min)
creates a minimum restriction excluding the minimum value
Definition: cci_param_restricted.h:120
+
scc::lt_excl_restriction
_max_excl_restriction< T > lt_excl_restriction(T max)
alias for max_excl_restriction(T max)
Definition: cci_param_restricted.h:142
+
scc::lte_restriction
_max_restriction< T > lte_restriction(T max)
alias for max_restriction(T max)
Definition: cci_param_restricted.h:132
+
scc::min_max_excl_restriction
_min_max_excl_restriction< T > min_max_excl_restriction(T min, T max)
creates a min/max restriction with excluding the limits
Definition: cci_param_restricted.h:100
+
scc::_discrete_restriction
Definition: cci_param_restricted.h:75
+
scc::_max_excl_restriction
Definition: cci_param_restricted.h:67
+
scc::_max_restriction
Definition: cci_param_restricted.h:59
+
scc::_min_excl_restriction
Definition: cci_param_restricted.h:51
+
scc::_min_max_excl_restriction
Definition: cci_param_restricted.h:33
+
scc::_min_max_restriction
Definition: cci_param_restricted.h:23
+
scc::_min_restriction
Definition: cci_param_restricted.h:43
+
scc::cci_param_restricted
extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values ...
Definition: cci_param_restricted.h:180
+
scc::cci_param_restricted::cci_param_restricted
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
Definition: cci_param_restricted.h:196
+
scc::cci_param_restricted::cci_param_restricted
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
Definition: cci_param_restricted.h:217
+
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1ace__target__pe-members.html b/develop/classaxi_1_1pe_1_1ace__target__pe-members.html new file mode 100644 index 00000000..be21b741 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1ace__target__pe-members.html @@ -0,0 +1,153 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+ + + + + + +
+
scc +  2022.4.0 +
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SystemC components library
+
+
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+
+
+
axi::pe::ace_target_pe Member List
+
+
+ +

This is the complete list of members for axi::pe::ace_target_pe, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)axi::pe::ace_target_peexplicit
ace_target_pe()=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
active_rdresp_id (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
b_transport(payload_type &trans, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bw_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
bw_intor (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
clk_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
clk_if (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
create_fsm_handle() overrideaxi::pe::ace_target_peprotectedvirtual
end_of_elaboration() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_method() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fw_o (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
fw_peq (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
get_direct_mem_ptr(payload_type &trans, tlm::tlm_dmi &dmi_data) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
is_active()axi::pe::ace_target_peinline
isckt_axi (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, const phase_type &phase) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_transport_bw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
nb_transport_fw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
operation_cb (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operation_resp(payload_type &trans, unsigned clk_delay=0)axi::pe::ace_target_pe
operations_callback(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
outstanding_cnt (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
payload_type typedef (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
phase_type typedef (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
rd_resp (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_delay (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
rd_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
set_bw_interface(axi::axi_bw_transport_if< axi_protocol_types > *ifs) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
set_operation_cb(std::function< unsigned(payload_type &trans)> cb)axi::pe::ace_target_peinline
setup_callbacks(fsm::fsm_handle *) overrideaxi::pe::ace_target_peprotectedvirtual
snoop(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
socket_bw (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
start_of_simulation() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
transport_dbg(payload_type &trans) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
tx_finish_event()axi::pe::ace_target_peinline
wr_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_delayaxi::pe::ace_target_pe
wr_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~ace_target_pe() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1ace__target__pe.html b/develop/classaxi_1_1pe_1_1ace__target__pe.html new file mode 100644 index 00000000..2fa5a71f --- /dev/null +++ b/develop/classaxi_1_1pe_1_1ace__target__pe.html @@ -0,0 +1,618 @@ + + + + + + + +scc: axi::pe::ace_target_pe Class Reference + + + + + + + + + + + +
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axi::pe::ace_target_pe Class Reference
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#include <ace_target_pe.h>

+
+Inheritance diagram for axi::pe::ace_target_pe:
+
+
Inheritance graph
+ + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::ace_target_pe:
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+ + + + +

+Classes

struct  bw_intor_impl
 
+ + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+void b_transport (payload_type &trans, sc_core::sc_time &t) override
 
+tlm::tlm_sync_enum nb_transport_fw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+bool get_direct_mem_ptr (payload_type &trans, tlm::tlm_dmi &dmi_data) override
 
+unsigned int transport_dbg (payload_type &trans) override
 
void set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
 Set the operation callback function. More...
 
void operation_resp (payload_type &trans, unsigned clk_delay=0)
 
bool is_active ()
 
const sc_core::sc_event & tx_finish_event ()
 
+tlm::tlm_sync_enum nb_transport_bw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+void invalidate_direct_mem_ptr (sc_dt::uint64 start_range, sc_dt::uint64 end_range) override
 
 ace_target_pe (const sc_core::sc_module_name &nm, size_t transfer_width)
 
+void set_bw_interface (axi::axi_bw_transport_if< axi_protocol_types > *ifs)
 
+void snoop (payload_type &trans)
 
+ + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< 64 > isckt_axi {"isckt_axi"}
 
+sc_core::sc_port< tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND > fw_o {"fw_o"}
 
+sc_core::sc_export< tlm::scc::pe::intor_bw_nb > bw_i {"bw_i"}
 
+scc::sc_attribute_randomized< int > rd_resp_delay {"rd_resp_delay", 0}
 
+scc::sc_attribute_randomized< int > wr_resp_delay {"wr_resp_delay", 0}
 the latency between request and response phase. Will be overwritten by the return of the callback function (if registered) -> BV
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Member Functions

+ ace_target_pe (ace_target_pe const &)=delete
 
+ ace_target_pe (ace_target_pe &&)=delete
 
+ace_target_pe & operator= (ace_target_pe const &)=delete
 
+ace_target_pe & operator= (ace_target_pe &&)=delete
 
+void end_of_elaboration () override
 
+void start_of_simulation () override
 
+void fsm_clk_method ()
 
fsm::fsm_handle * create_fsm_handle () override
 
void setup_callbacks (fsm::fsm_handle *) override
 
+unsigned operations_callback (payload_type &trans)
 
+void nb_fw (payload_type &trans, const phase_type &phase)
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Attributes

+axi::axi_bw_transport_if< axi_protocol_types > * socket_bw {nullptr}
 
+std::function< unsigned(payload_type &trans)> operation_cb
 
+sc_core::sc_fifo< payload_type * > rd_resp_fifo {1}
 
+sc_core::sc_fifo< payload_type * > wr_resp_fifo {1}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > wr_resp_beat_fifo {128}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > rd_resp_beat_fifo {128}
 
+scc::ordered_semaphore rd_resp {1}
 
+scc::ordered_semaphore wr_resp_ch {1}
 
+scc::ordered_semaphore rd_resp_ch {1}
 
+sc_core::sc_clock * clk_if {nullptr}
 
+std::unique_ptr< bw_intor_impl > bw_intor
 
+std::array< unsigned, 3 > outstanding_cnt {{0, 0, 0}}
 
+tlm_utils::peq_with_cb_and_phase< ace_target_pe > fw_peq {this, &ace_target_pe::nb_fw}
 
+std::unordered_set< unsigned > active_rdresp_id
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+ + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+

Detailed Description

+

the target protocol engine base class

+ +

Definition at line 41 of file ace_target_pe.h.

+

Constructor & Destructor Documentation

+ +

◆ ace_target_pe()

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
ace_target_pe::ace_target_pe (const sc_core::sc_module_name & nm,
size_t transfer_width 
)
+ 		+explicit
+
+

the constructor. Protected as it should only be called by derived classes

Parameters
+ + + +
port
transfer_width
+
+
+ +

Definition at line 56 of file ace_target_pe.cpp.

+ +
+
+

Member Function Documentation

+ +

◆ create_fsm_handle()

+ +
+
+ + + + + +
+ + + + + + + +
fsm_handle * ace_target_pe::create_fsm_handle ()
+ 		+overrideprotectedvirtual
+
+
See also
base::create_fsm_handle()
+ +

Implements axi::fsm::base.

+ +

Definition at line 115 of file ace_target_pe.cpp.

+ +
+
+ +

◆ is_active()

+ +
+
+ + + + + +
+ + + + + + + +
bool axi::pe::ace_target_pe::is_active ()
+ 		+inline
+
+

returns true if any transaction is still in flight

+
Returns
+ +

Definition at line 98 of file ace_target_pe.h.

+ +
+
+ +

◆ operation_resp()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void axi::pe::ace_target_pe::operation_resp (payload_type & trans,
unsigned clk_delay = 0 
)
+
+

start the response from an operation callback if latency is not set by the callback

+
Parameters
+ + + +
trans
sync
+
+
+ +
+
+ +

◆ set_operation_cb()

+ +
+
+ + + + + +
+ + + + + + + + +
void axi::pe::ace_target_pe::set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
+ 		+inline
+
+ +

Set the operation callback function.

+

This callback is invoked once a transaction arrives. This function is not allowed to block and returns the latency of the operation i.e. the duration until the reponse phase starts

Todo:
refine API
+
Parameters
+ + +
cbthe callback function
+
+
+ +

Definition at line 85 of file ace_target_pe.h.

+ +
+
+ +

◆ setup_callbacks()

+ +
+
+ + + + + +
+ + + + + + + + +
void ace_target_pe::setup_callbacks (fsm::fsm_handle * fsm_hndl)
+ 		+overrideprotectedvirtual
+
+
See also
base::setup_callbacks(fsm::fsm_handle*)
+ +

Implements axi::fsm::base.

+ +

Definition at line 117 of file ace_target_pe.cpp.

+ +
+
+ +

◆ tx_finish_event()

+ +
+
+ + + + + +
+ + + + + + + +
const sc_core::sc_event& axi::pe::ace_target_pe::tx_finish_event ()
+ 		+inline
+
+

get the event being notfied upon the finishing of a transaction

+
Returns
reference to sc_event
+ +

Definition at line 104 of file ace_target_pe.h.

+ +
+
+
The documentation for this class was generated from the following files: +
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1ace__target__pe.js b/develop/classaxi_1_1pe_1_1ace__target__pe.js new file mode 100644 index 00000000..387cc5da --- /dev/null +++ b/develop/classaxi_1_1pe_1_1ace__target__pe.js @@ -0,0 +1,52 @@ +var classaxi_1_1pe_1_1ace__target__pe = +[ + [ "bw_intor_impl", "structace__target__pe_1_1bw__intor__impl.html", "structace__target__pe_1_1bw__intor__impl" ], + [ "payload_type", "classaxi_1_1pe_1_1ace__target__pe.html#ae889973eb131a8543f875092f70598cb", null ], + [ "phase_type", "classaxi_1_1pe_1_1ace__target__pe.html#a9d0786e799837fae2fe45b2cef0df1d9", null ], + [ "~ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#a2656ccc3d9d7bb084f00d0f7b4c730d7", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#a82790b1a10222ec1ba65ba11d4d176ee", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#aecde5dc99c5532dd8b686129cbee2bb7", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#ad3c15b4d3f2a7b5aa936af058e927200", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#ab69463b27a55bc1e38eebe542182184e", null ], + [ "b_transport", "classaxi_1_1pe_1_1ace__target__pe.html#aee6de2689874daf44969119e7fe666a0", null ], + [ "create_fsm_handle", "classaxi_1_1pe_1_1ace__target__pe.html#a3ea7193538db51859e6389130e185686", null ], + [ "end_of_elaboration", "classaxi_1_1pe_1_1ace__target__pe.html#a56e215e2f32c1b25b0ec3ce060b59a1d", null ], + [ "fsm_clk_method", "classaxi_1_1pe_1_1ace__target__pe.html#a3e54ff4ab8f6e7265efe51939e8ef7df", null ], + [ "get_direct_mem_ptr", "classaxi_1_1pe_1_1ace__target__pe.html#ab04d4d967c53804ae54bdae8f715e4d8", null ], + [ "invalidate_direct_mem_ptr", "classaxi_1_1pe_1_1ace__target__pe.html#a9d15f27415ffccf2f95cd45329793d1b", null ], + [ "is_active", "classaxi_1_1pe_1_1ace__target__pe.html#aff66caa477d0b90a7bd4eb32d928616c", null ], + [ "nb_fw", "classaxi_1_1pe_1_1ace__target__pe.html#a770f06a11beac1d1742b2b1b22dacd5a", null ], + [ "nb_transport_bw", "classaxi_1_1pe_1_1ace__target__pe.html#a7b44dab1263ee848a00578ca38ec8c67", null ], + [ "nb_transport_fw", "classaxi_1_1pe_1_1ace__target__pe.html#a5c12487466121a9165dc1f21c1f3a1e2", null ], + [ "operation_resp", "classaxi_1_1pe_1_1ace__target__pe.html#a008c71cd290c6e88971ba71b0a36835b", null ], + [ "operations_callback", "classaxi_1_1pe_1_1ace__target__pe.html#a891e960ad36c3430146d53af89fb8380", null ], + [ "operator=", "classaxi_1_1pe_1_1ace__target__pe.html#ada34ebbd220cafcedfa653cfa3211eb0", null ], + [ "operator=", "classaxi_1_1pe_1_1ace__target__pe.html#a4f8a7e54ccdbb8e39e8d47531a75dbbc", null ], + [ "set_bw_interface", "classaxi_1_1pe_1_1ace__target__pe.html#a6c7abb59dea0220e00a8171cc0b284ad", null ], + [ "set_operation_cb", "classaxi_1_1pe_1_1ace__target__pe.html#a5efdb0544aea6dc9e2dd105b86480e54", null ], + [ "setup_callbacks", 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b/develop/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.md5 new file mode 100644 index 00000000..d3e8defc --- /dev/null +++ b/develop/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.md5 @@ -0,0 +1 @@ +2b27ac6a6195b0400e8cede87aca3ac2 \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png b/develop/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png new file mode 100644 index 00000000..5f803794 Binary files /dev/null and b/develop/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png differ diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target-members.html b/develop/classaxi_1_1pe_1_1simple__ace__target-members.html new file mode 100644 index 00000000..fbef6487 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target-members.html @@ -0,0 +1,162 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Member List
+
+
+ +

This is the complete list of members for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)axi::pe::ace_target_peexplicit
ace_target_pe()=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
active_rdresp_id (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
b_transport(payload_type &trans, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
base typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
axi::pe::ace_target_pe::base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::base
bw_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
bw_intor (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
clk_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
clk_if (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
create_fsm_handle() overrideaxi::pe::ace_target_peprotectedvirtual
end_of_elaboration() (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inlineprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_method() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fw_o (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
fw_peq (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
get_direct_mem_ptr(payload_type &trans, tlm::tlm_dmi &dmi_data) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
is_active()axi::pe::ace_target_peinline
isckt_axi (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, const phase_type &phase) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_transport_bw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
nb_transport_fw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
operation_cb (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operation_resp(payload_type &trans, unsigned clk_delay=0)axi::pe::ace_target_pe
operations_callback(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(simple_ace_target const &)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
operator=(simple_ace_target &&)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
operator=(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
outstanding_cnt (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
payload_type typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
phase_type typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
rd_resp (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_delay (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
rd_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
set_bw_interface(axi::axi_bw_transport_if< axi_protocol_types > *ifs) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
set_operation_cb(std::function< unsigned(payload_type &trans)> cb)axi::pe::ace_target_peinline
setup_callbacks(fsm::fsm_handle *) overrideaxi::pe::ace_target_peprotectedvirtual
simple_ace_target(axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inline
simple_ace_target(const sc_core::sc_module_name &nm, axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket) (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inline
simple_ace_target()=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
simple_ace_target(simple_ace_target const &)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
simple_ace_target(simple_ace_target &&)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
snoop(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
socket (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >protected
socket_bw (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
start_of_simulation() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
transport_dbg(payload_type &trans) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
tx_finish_event()axi::pe::ace_target_peinline
wr_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_delayaxi::pe::ace_target_pe
wr_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~ace_target_pe() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target.html b/develop/classaxi_1_1pe_1_1simple__ace__target.html new file mode 100644 index 00000000..93271e3b --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target.html @@ -0,0 +1,448 @@ + + + + + + + +scc: axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
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+
+
+Public Types | +Public Member Functions | +Protected Member Functions | +Protected Attributes | +List of all members
+
+
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Class Template Reference
+
+
+
+Inheritance diagram for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >:
+
+
Inheritance graph
+ + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + + + + + + + + +

+Public Types

+using base = ace_target_pe
 
+using payload_type = base::payload_type
 
+using phase_type = base::phase_type
 
- Public Types inherited from axi::pe::ace_target_pe
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

 simple_ace_target (axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
 the constructor More...
 
+ simple_ace_target (const sc_core::sc_module_name &nm, axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
 
+ simple_ace_target (simple_ace_target const &)=delete
 
+ simple_ace_target (simple_ace_target &&)=delete
 
+simple_ace_target & operator= (simple_ace_target const &)=delete
 
+simple_ace_target & operator= (simple_ace_target &&)=delete
 
- Public Member Functions inherited from axi::pe::ace_target_pe
+void b_transport (payload_type &trans, sc_core::sc_time &t) override
 
+tlm::tlm_sync_enum nb_transport_fw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+bool get_direct_mem_ptr (payload_type &trans, tlm::tlm_dmi &dmi_data) override
 
+unsigned int transport_dbg (payload_type &trans) override
 
void set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
 Set the operation callback function. More...
 
void operation_resp (payload_type &trans, unsigned clk_delay=0)
 
bool is_active ()
 
const sc_core::sc_event & tx_finish_event ()
 
+tlm::tlm_sync_enum nb_transport_bw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+void invalidate_direct_mem_ptr (sc_dt::uint64 start_range, sc_dt::uint64 end_range) override
 
 ace_target_pe (const sc_core::sc_module_name &nm, size_t transfer_width)
 
+void set_bw_interface (axi::axi_bw_transport_if< axi_protocol_types > *ifs)
 
+void snoop (payload_type &trans)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Member Functions

+void end_of_elaboration ()
 
- Protected Member Functions inherited from axi::pe::ace_target_pe
+ ace_target_pe (ace_target_pe const &)=delete
 
+ ace_target_pe (ace_target_pe &&)=delete
 
+ace_target_pe & operator= (ace_target_pe const &)=delete
 
+ace_target_pe & operator= (ace_target_pe &&)=delete
 
+void end_of_elaboration () override
 
+void start_of_simulation () override
 
+void fsm_clk_method ()
 
fsm::fsm_handle * create_fsm_handle () override
 
void setup_callbacks (fsm::fsm_handle *) override
 
+unsigned operations_callback (payload_type &trans)
 
+void nb_fw (payload_type &trans, const phase_type &phase)
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Attributes

+axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > & socket
 
- Protected Attributes inherited from axi::pe::ace_target_pe
+axi::axi_bw_transport_if< axi_protocol_types > * socket_bw {nullptr}
 
+std::function< unsigned(payload_type &trans)> operation_cb
 
+sc_core::sc_fifo< payload_type * > rd_resp_fifo {1}
 
+sc_core::sc_fifo< payload_type * > wr_resp_fifo {1}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > wr_resp_beat_fifo {128}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > rd_resp_beat_fifo {128}
 
+scc::ordered_semaphore rd_resp {1}
 
+scc::ordered_semaphore wr_resp_ch {1}
 
+scc::ordered_semaphore rd_resp_ch {1}
 
+sc_core::sc_clock * clk_if {nullptr}
 
+std::unique_ptr< bw_intor_impl > bw_intor
 
+std::array< unsigned, 3 > outstanding_cnt {{0, 0, 0}}
 
+tlm_utils::peq_with_cb_and_phase< ace_target_pe > fw_peq {this, &ace_target_pe::nb_fw}
 
+std::unordered_set< unsigned > active_rdresp_id
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+ + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Public Attributes inherited from axi::pe::ace_target_pe
+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< 64 > isckt_axi {"isckt_axi"}
 
+sc_core::sc_port< tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND > fw_o {"fw_o"}
 
+sc_core::sc_export< tlm::scc::pe::intor_bw_nb > bw_i {"bw_i"}
 
+scc::sc_attribute_randomized< int > rd_resp_delay {"rd_resp_delay", 0}
 
+scc::sc_attribute_randomized< int > wr_resp_delay {"wr_resp_delay", 0}
 the latency between request and response phase. Will be overwritten by the return of the callback function (if registered) -> BV
 
- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+

Detailed Description

+

template<unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1, sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+class axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >

+ + +

Definition at line 29 of file simple_ace_target.h.

+

Constructor & Destructor Documentation

+ +

◆ simple_ace_target()

+ +
+
+
+template<unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1, sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+ + + + + +
+ + + + + + + + +
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >::simple_ace_target (axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > & socket)
+ 		+inline
+
+ +

the constructor

+
Parameters
+ + +
socketreference to the initiator socket used to send and receive transactions
+
+
+ +

Definition at line 39 of file simple_ace_target.h.

+ +
+
+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target.js b/develop/classaxi_1_1pe_1_1simple__ace__target.js new file mode 100644 index 00000000..09248d4a --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target.js @@ -0,0 +1,15 @@ +var classaxi_1_1pe_1_1simple__ace__target = +[ + [ "base", "classaxi_1_1pe_1_1simple__ace__target.html#acbf23f74d25717850fbe7f7489364977", null ], + [ "payload_type", "classaxi_1_1pe_1_1simple__ace__target.html#a9df478707657e5a90f828699d6e48346", null ], + [ "phase_type", "classaxi_1_1pe_1_1simple__ace__target.html#a1650fcfd05a074a1e13161957c275885", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a6ba3fdb7ad9c049d876814d0fe836926", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a969b78419fad753207f7e05f3dd7c63b", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#afaa647f336a95cb1945f02ce3521b45a", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a2a16bd1c0fc796edab64a59d9f1a7fb3", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a5d7cf470b870bfc0d6b8907f510db5a4", null ], + [ "end_of_elaboration", "classaxi_1_1pe_1_1simple__ace__target.html#a012e11d501b45cb3d3e5bc7e78ad1a16", null ], + [ "operator=", "classaxi_1_1pe_1_1simple__ace__target.html#a9133a9faccf7333b1e7852cc2d1dc51a", null ], + [ "operator=", "classaxi_1_1pe_1_1simple__ace__target.html#afabb06b5476d1e0c0b0ed2d717ee0921", null ], + [ "socket", "classaxi_1_1pe_1_1simple__ace__target.html#a640b57953b23173cc21e741a7a46d26c", null ] +]; \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map new file mode 100644 index 00000000..a93561df --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 new file mode 100644 index 00000000..a7eaaadd --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 @@ -0,0 +1 @@ +6832e2357653c11f914534647c5b4f4b \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png new file mode 100644 index 00000000..b25a1bb3 Binary files /dev/null and b/develop/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png differ diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map new file mode 100644 index 00000000..109f5af3 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 new file mode 100644 index 00000000..0756c513 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 @@ -0,0 +1 @@ +9fec7f3567501f2e02831df2e72aefdc \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png new file mode 100644 index 00000000..580dae2f Binary files /dev/null and b/develop/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png differ diff --git a/develop/classaxi_1_1pe_1_1target__info__if-members.html b/develop/classaxi_1_1pe_1_1target__info__if-members.html new file mode 100644 index 00000000..8237411a --- /dev/null +++ b/develop/classaxi_1_1pe_1_1target__info__if-members.html @@ -0,0 +1,82 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+
+
axi::pe::target_info_if Member List
+
+
+ +

This is the complete list of members for axi::pe::target_info_if, including all inherited members.

+ + + +
get_outstanding_tx_count()=0 (defined in axi::pe::target_info_if)axi::pe::target_info_ifpure virtual
~target_info_if()=default (defined in axi::pe::target_info_if)axi::pe::target_info_ifvirtual
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1target__info__if.html b/develop/classaxi_1_1pe_1_1target__info__if.html new file mode 100644 index 00000000..4a5f53ca --- /dev/null +++ b/develop/classaxi_1_1pe_1_1target__info__if.html @@ -0,0 +1,106 @@ + + + + + + + +scc: axi::pe::target_info_if Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
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+
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+ +
+
+
+Public Member Functions | +List of all members
+
+
axi::pe::target_info_if Class Referenceabstract
+
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+
+Inheritance diagram for axi::pe::target_info_if:
+
+
Inheritance graph
+ + + + + + + +
[legend]
+ + + + +

+Public Member Functions

+virtual size_t get_outstanding_tx_count ()=0
 
+

Detailed Description

+
+

Definition at line 14 of file target_info_if.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classaxi_1_1pe_1_1target__info__if.js b/develop/classaxi_1_1pe_1_1target__info__if.js new file mode 100644 index 00000000..fd4edc94 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1target__info__if.js @@ -0,0 +1,5 @@ +var classaxi_1_1pe_1_1target__info__if = +[ + [ "~target_info_if", "classaxi_1_1pe_1_1target__info__if.html#aaaf50a3ff1ded66912de03102a103d85", null ], + [ "get_outstanding_tx_count", "classaxi_1_1pe_1_1target__info__if.html#a1ccb7acff97230b07b1e9efca056176a", null ] +]; \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.map b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.map new file mode 100644 index 00000000..fe302287 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 new file mode 100644 index 00000000..52acb5a6 --- /dev/null +++ b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 @@ -0,0 +1 @@ +5c3a1e0994aebf684f6705c04b654039 \ No newline at end of file diff --git a/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.png b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.png new file mode 100644 index 00000000..4f9a26dc Binary files /dev/null and b/develop/classaxi_1_1pe_1_1target__info__if__inherit__graph.png differ diff --git a/develop/classscc_1_1sc__in__opt-members.html b/develop/classscc_1_1sc__in__opt-members.html new file mode 100644 index 00000000..1b7b0a10 --- /dev/null +++ b/develop/classscc_1_1sc__in__opt-members.html @@ -0,0 +1,115 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
scc::sc_in_opt< T > Member List
+
+
+ +

This is the complete list of members for scc::sc_in_opt< T >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
base_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
data_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
default_event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
in_if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
in_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
inout_if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
inout_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
kind() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlinevirtual
operator const data_type &() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
read() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt() (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
this_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
value_changed_event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
~sc_in_opt() (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlinevirtual
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt.html b/develop/classscc_1_1sc__in__opt.html new file mode 100644 index 00000000..cdb5b451 --- /dev/null +++ b/develop/classscc_1_1sc__in__opt.html @@ -0,0 +1,215 @@ + + + + + + + +scc: scc::sc_in_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
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+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< T >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< T >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+virtual const char * kind () const
 
+

Detailed Description

+

template<class T>
+class scc::sc_in_opt< T >

+ + +

Definition at line 39 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt.js b/develop/classscc_1_1sc__in__opt.js new file mode 100644 index 00000000..fcffb63b --- /dev/null +++ b/develop/classscc_1_1sc__in__opt.js @@ -0,0 +1,38 @@ +var classscc_1_1sc__in__opt = +[ + [ "base_port_type", "classscc_1_1sc__in__opt.html#a4382df3bdfb762af71f0f39b7b9b91d2", null ], + [ "base_type", "classscc_1_1sc__in__opt.html#a358ffb2ce8eff5c84b81b20d369bcd3f", null ], + [ "data_type", "classscc_1_1sc__in__opt.html#a11f1f6cc1a56682fbd8f0d37d9d7f5ef", null ], + [ "if_type", "classscc_1_1sc__in__opt.html#a7f23aaf7fa0e4694d42e55b9125912af", null ], + [ "in_if_type", "classscc_1_1sc__in__opt.html#a5b8c1f663e569931451a4236106578ca", null ], + [ "in_port_type", "classscc_1_1sc__in__opt.html#a3e2a03eb9e8eff9e6c956457326d1c8f", null ], + [ "inout_if_type", "classscc_1_1sc__in__opt.html#a36754774d16cddaaac87bc624fea5c98", null ], + [ "inout_port_type", "classscc_1_1sc__in__opt.html#a3878d27e2cce111fcce61b5993fb8c50", null ], + [ "this_type", "classscc_1_1sc__in__opt.html#acac46ff317b8e84689cb0bbc6377df03", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a7a7860e661cb59b2b1519efe4a583311", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#ae3357731d9f210f6d2a25ae488900cf2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a663090a84c2ccc04c282ab13345541c5", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a74a2ae1e0f6af24804d3d086855932e8", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a334f6df18e92f7e7d55ca15b75339e61", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a65f5bf71da783339c780c145a562c2f2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a7c3a0f0008219ef34a8e3e1f287edc73", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a2bbcfc30d6b466bf05bb395901f0fb12", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#aee0c8591eef251f2100d143995dffc07", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#aef05b7102e651b5ea2d831f26502812f", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a06d2218c1398c5bd3b0f8aee91405cff", null ], + [ "~sc_in_opt", "classscc_1_1sc__in__opt.html#a4f39aa4cc01a847cf3aa1258a3c69393", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a34594ba85e2acdeb7b72bff03ba83097", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a24b9e9ab9a30a9f296a8630c6bc4ed0d", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a978ec8e6940ab222456acba4a3f3de70", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a44d52e1d90722a1881b6fd68e307c0cd", null ], + [ "default_event", "classscc_1_1sc__in__opt.html#af9bfec8ff248bdaa246f7772de9b7fff", null ], + [ "event", "classscc_1_1sc__in__opt.html#ac263423ca1866bee1d670ba6eaad539e", null ], + [ "kind", "classscc_1_1sc__in__opt.html#a62f47a6a5e71645ff5ad96c3220dde7d", null ], + [ "operator const data_type &", "classscc_1_1sc__in__opt.html#adf6da12c8ffe8ed8390dcf4c2e368cfa", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#a11ce8221e4cd00709eff5c58392109fb", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#adbed146f319e78d6b748c6b1e80e7db3", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#a319e4f48d38bfe8d7cd4db983514e646", null ], + [ "operator=", "classscc_1_1sc__in__opt.html#aa2f4d1e4219e87af1de23e9aec72125f", null ], + [ "read", "classscc_1_1sc__in__opt.html#a974d2a0ad850d85addbd85ce1b89e50b", null ], + [ "value_changed_event", "classscc_1_1sc__in__opt.html#ad76a9e660a5cc6887d9442ab90fad9f8", null ] +]; \ No newline at end of file diff --git a/develop/classscc_1_1sc__in__opt_3_01bool_01_4-members.html b/develop/classscc_1_1sc__in__opt_3_01bool_01_4-members.html new file mode 100644 index 00000000..b1cbdf1c --- /dev/null +++ b/develop/classscc_1_1sc__in__opt_3_01bool_01_4-members.html @@ -0,0 +1,119 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_in_opt< bool > Member List
+
+
+ +

This is the complete list of members for scc::sc_in_opt< bool >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
base_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
data_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
default_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
in_if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
in_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
inout_if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
inout_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
kind() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlinevirtual
negedge() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
negedge_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator const data_type &() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
posedge() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
posedge_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
read() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt() (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
this_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
value_changed_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
~sc_in_opt()=default (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >virtual
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt_3_01bool_01_4.html b/develop/classscc_1_1sc__in__opt_3_01bool_01_4.html new file mode 100644 index 00000000..3711c38d --- /dev/null +++ b/develop/classscc_1_1sc__in__opt_3_01bool_01_4.html @@ -0,0 +1,224 @@ + + + + + + + +scc: scc::sc_in_opt< bool > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< bool > Class Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< bool >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< bool >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef bool data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+virtual const char * kind () const
 
+

Detailed Description

+
+

Definition at line 127 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt_3_01bool_01_4.js b/develop/classscc_1_1sc__in__opt_3_01bool_01_4.js new file mode 100644 index 00000000..7bc6bfcf --- /dev/null +++ b/develop/classscc_1_1sc__in__opt_3_01bool_01_4.js @@ -0,0 +1,42 @@ +var classscc_1_1sc__in__opt_3_01bool_01_4 = +[ + [ "base_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a56745c49991c34fd2f49f29d05683dbf", null ], + [ "base_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#af9c315123f7f84f8e125cdef76b0ef63", null ], + [ "data_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aaea19fdc3a66fd8758fb8a7702a59a15", null ], + [ "if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a1091f706cf5b1d9163c025a7173789b0", null ], + [ "in_if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#af21b2f97c8c486ff7d87d5541fdd0c50", null ], + [ "in_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a3ee5ac9543ebee2c8968ac7cedbaf0a3", null ], + [ "inout_if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad6837ba41d15342486e8cbb69fc2ca75", null ], + [ "inout_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab8a71fecaaa3b607c1aa5689146ed14a", null ], + [ "this_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a8696d9c4c7e6586f649748ea4b7f3291", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aed0d010e7cc571d06337d903b29c2372", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab1cbdb8d1db15cb0b6d636dcf5d347f1", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a36d87c0655ca88706fc2002dd59f90c2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aa45a419f804da5dc9f30542939b943dc", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#abe192d0fc1170cd2fd20bf9a80ba8228", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a248c8585852372987673aa3091f1bcd7", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a1ce6f1376c868e7b6c44dd7e54e12b90", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aa8f014172c70653d04f34ede343eb5bd", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ae4e44b5f5dcb17b5e09779bb2e05a157", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad4ce350770155c9ba364f767960c9466", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a0dc23df0bc6b68d884a6d9c05e150346", null ], + [ "~sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ae51f6057db2cae6bade028c9b624ca06", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a8b7f6b48de0bccd9630033f29f4675d6", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad7fafb46d604a4e65153fe29f0c2192e", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2065d43e6c8c61a7c2575ebe9381f7c3", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a888ae8b3fbd0d661fd7dc2c431c0c039", null ], + [ "default_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2ad682aef251761e033ec88641376ffd", null ], + [ "event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a3284dc277e10907814ecee3cd749e5ec", null ], + [ "kind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a446f74238bf06597df7970f8a8078228", null ], + [ "negedge", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab080709e85a15533eaadbf87673c472a", null ], + [ "negedge_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a9acbe36c4e446757ab22803ad5499d72", null ], + [ "operator const data_type &", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a19d36daeafa1a67a2fec097500c09a35", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a59e2dceb06486a1173ff9af0ecaf5109", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a61249c3c155be89cdbf683c643a1ef6a", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ac30742b34ad035eecba8130fd5028ea5", null ], + [ "operator=", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2e26724c90388ecbf1f79a8b2b28597c", null ], + [ "posedge", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad24d71f08d0ed12b70b4dc6dbfb7d47a", null ], + [ "posedge_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a882d42f88020a78d7b484de2954dcdb6", null ], + [ "read", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a636bd1df276252e2af659b45f0c95160", null ], + [ "value_changed_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a4456ba9eedde54aa91627c550202799e", null ] +]; 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+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_in_opt< sc_dt::sc_logic > Member List
+
+
+ +

This is the complete list of members for scc::sc_in_opt< sc_dt::sc_logic >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
base_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
data_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
default_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
in_if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
in_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
inout_if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
inout_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
kind() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlinevirtual
negedge() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
negedge_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator const data_type &() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
posedge() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
posedge_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
read() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt() (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
this_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
value_changed_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
~sc_in_opt()=default (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >virtual
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html b/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html new file mode 100644 index 00000000..61b58ef8 --- /dev/null +++ b/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html @@ -0,0 +1,224 @@ + + + + + + + +scc: scc::sc_in_opt< sc_dt::sc_logic > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< sc_dt::sc_logic > Class Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< sc_dt::sc_logic >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< sc_dt::sc_logic >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef sc_dt::sc_logic data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+virtual const char * kind () const
 
+

Detailed Description

+
+

Definition at line 223 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js b/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js new file mode 100644 index 00000000..4d4ae737 --- /dev/null +++ b/develop/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js @@ -0,0 +1,42 @@ +var classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4 = +[ + [ "base_port_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#aa84e5227a01388b8357514d8145e94c9", null ], + [ "base_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a615d83ba4d4d1f2ca6ea75e9c14f9e78", null ], + [ "data_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a7283a171a666a3f68757e989c85e3c93", null ], + [ "if_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a20f837fcc144564d5c82dafb3420ff61", null ], + [ "in_if_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#aa42f6bbfe19b676cb38d21dc1e6e9a08", null ], + [ "in_port_type", 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b/develop/classscc_1_1sc__in__opt__inherit__graph.png differ diff --git a/develop/classscc_1_1sc__inout__opt-members.html b/develop/classscc_1_1sc__inout__opt-members.html new file mode 100644 index 00000000..75a79f0a --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt-members.html @@ -0,0 +1,114 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< T > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< T >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
data_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
default_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_port_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
inout_if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
inout_port_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
kind() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >protected
operator const data_type &() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
read() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt() (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
this_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
value_changed_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >virtual
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt.html b/develop/classscc_1_1sc__inout__opt.html new file mode 100644 index 00000000..63c26916 --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt.html @@ -0,0 +1,218 @@ + + + + + + + +scc: scc::sc_inout_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< T >:
+
+
Inheritance graph
+ + + + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< T >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+

template<class T>
+class scc::sc_inout_opt< T >

+ + +

Definition at line 314 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt.js b/develop/classscc_1_1sc__inout__opt.js new file mode 100644 index 00000000..f389399c --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt.js @@ -0,0 +1,37 @@ +var classscc_1_1sc__inout__opt = +[ + [ "base_type", "classscc_1_1sc__inout__opt.html#af285a031936bae6f608ba67e6a7ef77d", null ], + [ "data_type", "classscc_1_1sc__inout__opt.html#a41430f6efc502149b8e3b6ad695769d8", null ], + [ "if_type", "classscc_1_1sc__inout__opt.html#a234939be32081957f5c5c1cf8322ba36", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt.html#a0b7dd44918a468585d66285430dac129", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt.html#a3f18aa4eae4da8c3fe3c826fd0433db3", null ], + [ "inout_if_type", "classscc_1_1sc__inout__opt.html#ab5a054fa7031d4e50e3dbd37e9cb3448", null ], + [ "inout_port_type", "classscc_1_1sc__inout__opt.html#a64ca3502a5534eec3a5e70056744771a", null ], + [ "this_type", "classscc_1_1sc__inout__opt.html#ac8a108aca04c2c503fce90e62c949047", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a7716f1859642b4c01f27247284ac3cc3", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a526b55a33226798050ef7ad82ac03aef", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a969eda7bc3a02031664302a2907e0245", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#afe1b6d6446f231b8eda67ae187225882", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a2738d7d28fbe0f1e1c0f64e4ac0daa6c", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a5c1281be3833562e106094a5df25735b", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#aeeb235f7fc678d4915d7033fff4f0c2d", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a7f4fc6310bded783c228c552889d33ac", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a45e14b3ab30dee3a39fc692d5a567841", null ], + [ "~sc_inout_opt", "classscc_1_1sc__inout__opt.html#a81b73209c4283d2e47e42eee0f762843", null ], + [ "default_event", "classscc_1_1sc__inout__opt.html#a12f0b446329367dcca450701b8693c3c", null ], + [ "end_of_elaboration", "classscc_1_1sc__inout__opt.html#a016fa8a6fc5e187aa52fb609f14889a3", null ], + [ "event", "classscc_1_1sc__inout__opt.html#ab0b1fba3844d25d347e2b2be552940ec", null ], + [ "initialize", "classscc_1_1sc__inout__opt.html#a1f044189e16aab8bf98de880b638a68c", null ], + [ "initialize", "classscc_1_1sc__inout__opt.html#ab1a6aef6ad5a51c82723a74c24b3b0b0", null ], + [ "kind", "classscc_1_1sc__inout__opt.html#aaead6c067289ec4afd623106cb12b92a", null ], + [ "operator const data_type &", "classscc_1_1sc__inout__opt.html#af47b867524b650867fc41b411ca4ee04", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a009c1e98f720c21586c544f53fd217ba", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#aba8814b31b8165a93f26dcd53fe30be4", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a95bc49a4da2cfbf41645628e61f3958d", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a31263843e83964719447551716a4a0f9", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#aa07066c21c0d5dc6feed74d14817a76f", null ], + [ "read", "classscc_1_1sc__inout__opt.html#aef88e80fcc2a3aef497b7856a6f08b00", null ], + [ "value_changed_event", "classscc_1_1sc__inout__opt.html#a9298ba5a89b9c4fabba531cd1ffe42cf", null ], + [ "write", "classscc_1_1sc__inout__opt.html#ac39bc6165ff428d942619b5853d8df9a", null ], + [ "m_init_val", "classscc_1_1sc__inout__opt.html#a34955da8b061b2f331387a394ab2fc3c", null ] +]; \ No newline at end of file diff --git a/develop/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html new file mode 100644 index 00000000..8b1f2816 --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html @@ -0,0 +1,118 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< bool > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< bool >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
data_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
default_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
in_if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
in_port_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
inout_if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
inout_port_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
kind() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >protected
negedge() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
negedge_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator const data_type &() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
posedge() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
posedge_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
read() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt() (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
this_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
value_changed_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >virtual
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.html b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.html new file mode 100644 index 00000000..cfd74ace --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.html @@ -0,0 +1,225 @@ + + + + + + + +scc: scc::sc_inout_opt< bool > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
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+
+
+ +
+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< bool > Class Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< bool >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< bool >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef bool data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+
+

Definition at line 440 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.js b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.js new file mode 100644 index 00000000..a740cd3e --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt_3_01bool_01_4.js @@ -0,0 +1,41 @@ +var classscc_1_1sc__inout__opt_3_01bool_01_4 = +[ + [ "base_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac06302b2655cd63054b02b17914f19b7", null ], + [ "data_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a73af6e1fcbedeaf67d821b5a62b730f2", null ], + [ "if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a8c2e707e9a82051244ee6bebcccf2e76", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ab46aa025fdf0754ee3c24cda67e7cc18", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a0cf8561f5c33a952fb91347eb2655198", null ], + [ "inout_if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a49c3b60c6d6c763018cfc298c0a04fff", null ], + [ "inout_port_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a4f44adc09b4c1c73189c5befe054df76", null ], + [ "this_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a359383a2bfed11eea866e1c702b6d574", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a79bb2267f5419a7d93cd5f11777bf659", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae2579559af35b24e395e99d5d12c4f21", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ad7a5433305d4e336f58acde36ecabff4", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a800968ea8895cbca8dd91092c96a4813", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7d38f2b51eb7bae0f4a677d1f9f53d62", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae47daae279119b189bb77cd1f9e1a023", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a17bc12b0c5c5ec6228f609bada3018b4", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a84a9eecffeb0238d8979abe180551fb6", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#aee86aa895f7c707700c4518ca35a40cb", null ], + [ "~sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a5b2029cb58031cbb56070c0fabe1f0b2", null ], + [ "default_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a805979f1ac4a3d31b29013f4511acdba", null ], + [ "end_of_elaboration", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a12620bd0f1cddb179cece7bdcde3ca80", null ], + [ "event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7b2cca8c1fe4e76da7b9c5354281f91f", null ], + [ "initialize", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac4c8f786acabc874f3b4b5f3458eb1e5", null ], + [ "initialize", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a131c79bbf4ebeb32c3afa59a05b40fdb", null ], + [ "kind", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ad3db89100bb4c9eac4bf92ccb24f1b37", null ], + [ "negedge", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae986972cfdb52472aea3179a719aa2ee", null ], + [ "negedge_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a720f33c501e4a420d51e1bb5b9d4cf58", null ], + [ "operator const data_type &", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a980968def660224555a78ea196e86c10", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a9d5dd105fca7bda0e6d4d50f03dd43d6", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#acc2c199ee9c84dd4f0a8d27f54ca5f2a", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7ef52c5ebe3c1178ce4126cbded4a471", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a1a7e561cfc77abeb7ecf0ae198c52946", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#abad433d53b0886ff432d1576a0d897af", null ], + [ "posedge", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a951b30e353938feb999b31686f3b2360", null ], + [ "posedge_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a16a5e567d3cb0c9768c6b94ef26ea6c3", null ], + [ "read", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a6dba440040f34e34a51864f80a700ad6", null ], + [ "value_changed_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a690f36bd2a27f3c80196a82bf953eaec", null ], + [ "write", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac95ce8fbef6cafe44dcf088b92e1a13c", null ], + [ "m_init_val", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a71332131c3871ef2ab7336e42d43e03a", null ] +]; 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+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< sc_dt::sc_logic > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< sc_dt::sc_logic >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
data_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
default_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
in_if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
in_port_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
inout_if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
inout_port_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
kind() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >protected
negedge() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
negedge_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator const data_type &() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
posedge() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
posedge_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
read() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt() (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
this_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
value_changed_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
~sc_inout_opt() (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >virtual
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html b/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html new file mode 100644 index 00000000..a81e662d --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html @@ -0,0 +1,225 @@ + + + + + + + +scc: scc::sc_inout_opt< sc_dt::sc_logic > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< sc_dt::sc_logic > Class Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< sc_dt::sc_logic >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< sc_dt::sc_logic >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef sc_dt::sc_logic data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+
+

Definition at line 558 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js b/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js new file mode 100644 index 00000000..c6c51951 --- /dev/null +++ b/develop/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js @@ -0,0 +1,41 @@ +var classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4 = +[ + [ "base_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a9063b2c9a086d2d32984e7dddbb39a3c", null ], + [ "data_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#ab01bc331e110c98481f5e15099ef2c77", null ], + [ "if_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a03f30d59ead3401572807533f583f0ed", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#ae844b461209c984714dd9637d45cdef5", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a45445992e8be53330b9c4ad8834d629f", null ], + [ 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+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_out_opt< T > Member List
+
+
+ +

This is the complete list of members for scc::sc_out_opt< T >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
data_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
default_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_if_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
in_port_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
inout_if_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
inout_port_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
kind() const (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >protected
operator const data_type &() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const data_type &value_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const in_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const in_port_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const inout_port_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const this_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
read() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt() (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
sc_out_opt() (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(const char *name_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(inout_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(inout_port_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(this_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(const char *name_, this_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
this_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
value_changed_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >virtual
~sc_out_opt() (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlinevirtual
+
+ + + + diff --git a/develop/classscc_1_1sc__out__opt.html b/develop/classscc_1_1sc__out__opt.html new file mode 100644 index 00000000..e74901dc --- /dev/null +++ b/develop/classscc_1_1sc__out__opt.html @@ -0,0 +1,277 @@ + + + + + + + +scc: scc::sc_out_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_out_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_out_opt< T >:
+
+
Inheritance graph
+ + + + + +
[legend]
+
+Collaboration diagram for scc::sc_out_opt< T >:
+
+
Collaboration graph
+ + + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_out_opt< data_type > this_type
 
+typedef sc_inout_opt< data_type > base_type
 
+typedef base_type::in_if_type in_if_type
 
+typedef base_type::in_port_type in_port_type
 
+typedef base_type::inout_if_type inout_if_type
 
+typedef base_type::inout_port_type inout_port_type
 
- Public Types inherited from scc::sc_inout_opt< T >
+typedef T data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_out_opt (const char *name_)
 
+ sc_out_opt (inout_if_type &interface_)
 
+ sc_out_opt (const char *name_, inout_if_type &interface_)
 
+ sc_out_opt (inout_port_type &parent_)
 
+ sc_out_opt (const char *name_, inout_port_type &parent_)
 
+ sc_out_opt (this_type &parent_)
 
+ sc_out_opt (const char *name_, this_type &parent_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+virtual const char * kind () const
 
- Public Member Functions inherited from scc::sc_inout_opt< T >
+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+ + + + +

+Additional Inherited Members

- Protected Attributes inherited from scc::sc_inout_opt< T >
+data_type * m_init_val
 
+

Detailed Description

+

template<class T>
+class scc::sc_out_opt< T >

+ + +

Definition at line 673 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
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+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
signal_opt_ports.cpp
+
+
+
1 #include "signal_opt_ports.h"
+
2 template class sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
3 template class sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
4 template class sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
5 template class sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
+
+ + + + diff --git a/develop/signal__opt__ports_8h_source.html b/develop/signal__opt__ports_8h_source.html new file mode 100644 index 00000000..84fa24b8 --- /dev/null +++ b/develop/signal__opt__ports_8h_source.html @@ -0,0 +1,856 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/sysc/scc/signal_opt_ports.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
signal_opt_ports.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2001 - 2023 Accellera Systems Initiative Inc. (Accellera)
+
3  * Copyright 2023 MINRES Technologies GmbH
+
4  *
+
5  * Licensed under the Apache License, Version 2.0 (the "License");
+
6  * you may not use this file except in compliance with the License.
+
7  * You may obtain a copy of the License at
+
8  *
+
9  * http://www.apache.org/licenses/LICENSE-2.0
+
10  *
+
11  * Unless required by applicable law or agreed to in writing, software
+
12  * distributed under the License is distributed on an "AS IS" BASIS,
+
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
14  * See the License for the specific language governing permissions and
+
15  * limitations under the License.
+
16  *******************************************************************************/
+
17 /*
+
18  * Created on: Dec 17, 2023
+
19  * Author: eyck
+
20  */
+
21 
+
22 #ifndef _SYSC_SCC_OPT_SIGNAL_PORTS_H_
+
23 #define _SYSC_SCC_OPT_SIGNAL_PORTS_H_
+
24 
+
25 #include "sysc/communication/sc_event_finder.h"
+
26 #include "sysc/communication/sc_port.h"
+
27 #include "sysc/communication/sc_signal_ifs.h"
+
28 #include "sysc/datatypes/bit/sc_logic.h"
+
29 #include "sysc/tracing/sc_trace.h"
+
30 
+
31 #if !defined(SC_DISABLE_VIRTUAL_BIND)
+
32 #define SCC_VIRT virtual
+
33 #else
+
34 #define SCC_VIRT /* non-virtual */
+
35 #endif
+
36 
+
37 namespace scc {
+
38 
+
39 template <class T> class sc_in_opt : public sc_core::sc_port<sc_core::sc_signal_in_if<T>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
40 public:
+
41  typedef T data_type;
+
42 
+
43  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
44  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
45  typedef sc_in_opt<data_type> this_type;
+
46  typedef typename base_type::port_type base_port_type;
+
47 
+
48  typedef if_type in_if_type;
+
49  typedef base_type in_port_type;
+
50  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
51  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
52 
+
53 public:
+
54  sc_in_opt()
+
55  : base_type() {}
+
56 
+
57  explicit sc_in_opt(const char* name_)
+
58  : base_type(name_) {}
+
59 
+
60  explicit sc_in_opt(const in_if_type& interface_)
+
61  : base_type(const_cast<in_if_type&>(interface_)) {}
+
62 
+
63  sc_in_opt(const char* name_, const in_if_type& interface_)
+
64  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
65 
+
66  explicit sc_in_opt(in_port_type& parent_)
+
67  : base_type(parent_) {}
+
68 
+
69  sc_in_opt(const char* name_, in_port_type& parent_)
+
70  : base_type(name_, parent_) {}
+
71 
+
72  explicit sc_in_opt(inout_port_type& parent_)
+
73  : base_type() {
+
74  sc_core::sc_port_base::bind(parent_);
+
75  }
+
76 
+
77  sc_in_opt(const char* name_, inout_port_type& parent_)
+
78  : base_type(name_) {
+
79  sc_core::sc_port_base::bind(parent_);
+
80  }
+
81 
+
82  sc_in_opt(this_type& parent_)
+
83  : base_type(parent_) {}
+
84 
+
85  sc_in_opt(const char* name_, this_type& parent_)
+
86  : base_type(name_, parent_) {}
+
87 
+
88  sc_in_opt(const this_type&) = delete;
+
89 
+
90  virtual ~sc_in_opt() {}
+
91 
+
92  this_type& operator=(const this_type&) = delete;
+
93 
+
94  SCC_VIRT void bind(const in_if_type& interface_) { sc_core::sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
95 
+
96  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
97 
+
98  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
99 
+
100  SCC_VIRT void bind(in_port_type& parent_) { sc_core::sc_port_base::bind(parent_); }
+
101 
+
102  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
103 
+
104  SCC_VIRT void bind(inout_port_type& parent_) { sc_core::sc_port_base::bind(parent_); }
+
105 
+
106  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
107 
+
108  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
109 
+
110  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
111 
+
112  const data_type& read() const { return (*this)->read(); }
+
113 
+
114  operator const data_type&() const { return (*this)->read(); }
+
115 
+
116  bool event() const { return (*this)->event(); }
+
117 
+
118  virtual const char* kind() const { return "sc_in"; }
+
119 };
+
120 
+
121 template <typename T>::std::ostream& operator<<(::std::ostream& os, const sc_in_opt<T>& a) { return os << a->read(); }
+
122 } // namespace scc
+
123 
+
124 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
125 
+
126 namespace scc {
+
127 template <> class SC_API sc_in_opt<bool> : public sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
128 public:
+
129  typedef bool data_type;
+
130 
+
131  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
132  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
133  typedef sc_in_opt<data_type> this_type;
+
134  typedef /* typename */ base_type::port_type base_port_type;
+
135 
+
136  typedef if_type in_if_type;
+
137  typedef base_type in_port_type;
+
138  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
139  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
140 
+
141 public:
+
142  sc_in_opt()
+
143  : base_type() {}
+
144 
+
145  explicit sc_in_opt(const char* name_)
+
146  : base_type(name_) {}
+
147 
+
148  explicit sc_in_opt(const in_if_type& interface_)
+
149  : base_type(const_cast<in_if_type&>(interface_)) {}
+
150 
+
151  sc_in_opt(const char* name_, const in_if_type& interface_)
+
152  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
153 
+
154  explicit sc_in_opt(in_port_type& parent_)
+
155  : base_type(parent_) {}
+
156 
+
157  sc_in_opt(const char* name_, in_port_type& parent_)
+
158  : base_type(name_, parent_) {}
+
159 
+
160  explicit sc_in_opt(inout_port_type& parent_)
+
161  : base_type() {
+
162  sc_port_base::bind(parent_);
+
163  }
+
164 
+
165  sc_in_opt(const char* name_, inout_port_type& parent_)
+
166  : base_type(name_) {
+
167  sc_port_base::bind(parent_);
+
168  }
+
169 
+
170  sc_in_opt(this_type& parent_)
+
171  : base_type(parent_) {}
+
172 
+
173  sc_in_opt(const char* name_, this_type& parent_)
+
174  : base_type(name_, parent_) {}
+
175 
+
176  sc_in_opt(const this_type&) = delete;
+
177 
+
178  virtual ~sc_in_opt() = default;
+
179 
+
180  this_type& operator=(const this_type&) = delete;
+
181 
+
182  SCC_VIRT void bind(const in_if_type& interface_) { sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
183 
+
184  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
185 
+
186  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
187 
+
188  SCC_VIRT void bind(in_port_type& parent_) { sc_port_base::bind(parent_); }
+
189 
+
190  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
191 
+
192  SCC_VIRT void bind(inout_port_type& parent_) { sc_port_base::bind(parent_); }
+
193 
+
194  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
195 
+
196  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
197 
+
198  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
199 
+
200  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
201 
+
202  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
203 
+
204  const data_type& read() const { return (*this)->read(); }
+
205 
+
206  operator const data_type&() const { return (*this)->read(); }
+
207 
+
208  bool event() const { return (*this)->event(); }
+
209 
+
210  bool posedge() const { return (*this)->posedge(); }
+
211 
+
212  bool negedge() const { return (*this)->negedge(); }
+
213 
+
214  virtual const char* kind() const { return "sc_in"; }
+
215 };
+
216 
+
217 } // namespace scc
+
218 
+
219 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
220 
+
221 namespace scc {
+
222 template <>
+
223 class SC_API sc_in_opt<sc_dt::sc_logic>
+
224 : public sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
225 public:
+
226  typedef sc_dt::sc_logic data_type;
+
227 
+
228  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
229  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
230  typedef sc_in_opt<data_type> this_type;
+
231  typedef /* typename */ base_type::port_type base_port_type;
+
232 
+
233  typedef if_type in_if_type;
+
234  typedef base_type in_port_type;
+
235  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
236  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
237 
+
238 public:
+
239  sc_in_opt()
+
240  : base_type() {}
+
241 
+
242  explicit sc_in_opt(const char* name_)
+
243  : base_type(name_) {}
+
244 
+
245  explicit sc_in_opt(const in_if_type& interface_)
+
246  : base_type(const_cast<in_if_type&>(interface_)) {}
+
247 
+
248  sc_in_opt(const char* name_, const in_if_type& interface_)
+
249  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
250 
+
251  explicit sc_in_opt(in_port_type& parent_)
+
252  : base_type(parent_) {}
+
253 
+
254  sc_in_opt(const char* name_, in_port_type& parent_)
+
255  : base_type(name_, parent_) {}
+
256 
+
257  explicit sc_in_opt(inout_port_type& parent_)
+
258  : base_type() {
+
259  sc_port_base::bind(parent_);
+
260  }
+
261 
+
262  sc_in_opt(const char* name_, inout_port_type& parent_)
+
263  : base_type(name_) {
+
264  sc_port_base::bind(parent_);
+
265  }
+
266 
+
267  sc_in_opt(this_type& parent_)
+
268  : base_type(parent_) {}
+
269 
+
270  sc_in_opt(const char* name_, this_type& parent_)
+
271  : base_type(name_, parent_) {}
+
272 
+
273  sc_in_opt(const this_type&) = delete;
+
274 
+
275  virtual ~sc_in_opt() = default;
+
276 
+
277  this_type& operator=(const this_type&) = delete;
+
278 
+
279  SCC_VIRT void bind(const in_if_type& interface_) { sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
280 
+
281  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
282 
+
283  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
284 
+
285  SCC_VIRT void bind(in_port_type& parent_) { sc_port_base::bind(parent_); }
+
286 
+
287  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
288 
+
289  SCC_VIRT void bind(inout_port_type& parent_) { sc_port_base::bind(parent_); }
+
290 
+
291  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
292 
+
293  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
294 
+
295  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
296 
+
297  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
298 
+
299  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
300 
+
301  const data_type& read() const { return (*this)->read(); }
+
302 
+
303  operator const data_type&() const { return (*this)->read(); }
+
304 
+
305  bool event() const { return (*this)->event(); }
+
306 
+
307  bool posedge() const { return (*this)->posedge(); }
+
308 
+
309  bool negedge() const { return (*this)->negedge(); }
+
310 
+
311  virtual const char* kind() const { return "sc_in"; }
+
312 };
+
313 
+
314 template <class T> class sc_inout_opt : public sc_core::sc_port<sc_core::sc_signal_inout_if<T>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
315 public:
+
316  typedef T data_type;
+
317 
+
318  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
319  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
320  typedef sc_inout_opt<data_type> this_type;
+
321 
+
322  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
323  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
324  typedef if_type inout_if_type;
+
325  typedef base_type inout_port_type;
+
326 
+
327 public:
+
328  sc_inout_opt()
+
329  : base_type()
+
330  , m_init_val(0) {}
+
331 
+
332  explicit sc_inout_opt(const char* name_)
+
333  : base_type(name_)
+
334  , m_init_val(0) {}
+
335 
+
336  explicit sc_inout_opt(inout_if_type& interface_)
+
337  : base_type(interface_)
+
338  , m_init_val(0) {}
+
339 
+
340  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
341  : base_type(name_, interface_)
+
342  , m_init_val(0) {}
+
343 
+
344  explicit sc_inout_opt(inout_port_type& parent_)
+
345  : base_type(parent_)
+
346  , m_init_val(0) {}
+
347 
+
348  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
349  : base_type(name_, parent_)
+
350  , m_init_val(0) {}
+
351 
+
352  sc_inout_opt(this_type& parent_)
+
353  : base_type(parent_)
+
354  , m_init_val(0) {}
+
355 
+
356  sc_inout_opt(const char* name_, this_type& parent_)
+
357  : base_type(name_, parent_)
+
358  , m_init_val(0) {}
+
359 
+
360  sc_inout_opt(const this_type&) = delete;
+
361 
+
362  virtual ~sc_inout_opt() = default;
+
363 
+
364  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
365 
+
366  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
367 
+
368  const data_type& read() const { return (*this)->read(); }
+
369 
+
370  operator const data_type&() const { return (*this)->read(); }
+
371 
+
372  bool event() const { return (*this)->event(); }
+
373 
+
374  void write(const data_type& value_) { (*this)->write(value_); }
+
375 
+
376  this_type& operator=(const data_type& value_) {
+
377  (*this)->write(value_);
+
378  return *this;
+
379  }
+
380 
+
381  this_type& operator=(const in_if_type& interface_) {
+
382  (*this)->write(interface_.read());
+
383  return *this;
+
384  }
+
385 
+
386  this_type& operator=(const in_port_type& port_) {
+
387  (*this)->write(port_->read());
+
388  return *this;
+
389  }
+
390 
+
391  this_type& operator=(const inout_port_type& port_) {
+
392  (*this)->write(port_->read());
+
393  return *this;
+
394  }
+
395 
+
396  this_type& operator=(const this_type& port_) {
+
397  (*this)->write(port_->read());
+
398  return *this;
+
399  }
+
400 
+
401  void initialize(const data_type& value_);
+
402 
+
403  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
404 
+
405  void end_of_elaboration() override;
+
406 
+
407  virtual const char* kind() const { return "sc_inout"; }
+
408 
+
409 protected:
+
410  data_type* m_init_val;
+
411 };
+
412 
+
413 template <typename T>::std::ostream& operator<<(::std::ostream& os, const sc_inout_opt<T>& a) { return os << a->read(); }
+
414 
+
415 template <class T> inline void sc_inout_opt<T>::initialize(const data_type& value_) {
+
416  inout_if_type* iface = dynamic_cast<inout_if_type*>(this->get_interface());
+
417  if(iface != 0) {
+
418  iface->write(value_);
+
419  } else {
+
420  if(m_init_val == 0) {
+
421  m_init_val = new data_type;
+
422  }
+
423  *m_init_val = value_;
+
424  }
+
425 }
+
426 
+
427 template <class T> inline void sc_inout_opt<T>::end_of_elaboration() {
+
428  if(m_init_val != 0) {
+
429  write(*m_init_val);
+
430  delete m_init_val;
+
431  m_init_val = 0;
+
432  }
+
433 }
+
434 } // namespace scc
+
435 
+
436 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
437 
+
438 namespace scc {
+
439 template <>
+
440 class SC_API sc_inout_opt<bool> : public sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
441 public:
+
442  typedef bool data_type;
+
443 
+
444  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
445  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
446  typedef sc_inout_opt<data_type> this_type;
+
447 
+
448  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
449  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
450  typedef if_type inout_if_type;
+
451  typedef base_type inout_port_type;
+
452 
+
453 public:
+
454  sc_inout_opt()
+
455  : base_type()
+
456  , m_init_val(0) {}
+
457 
+
458  explicit sc_inout_opt(const char* name_)
+
459  : base_type(name_)
+
460  , m_init_val(0) {}
+
461 
+
462  explicit sc_inout_opt(inout_if_type& interface_)
+
463  : base_type(interface_)
+
464  , m_init_val(0) {}
+
465 
+
466  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
467  : base_type(name_, interface_)
+
468  , m_init_val(0) {}
+
469 
+
470  explicit sc_inout_opt(inout_port_type& parent_)
+
471  : base_type(parent_)
+
472  , m_init_val(0) {}
+
473 
+
474  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
475  : base_type(name_, parent_)
+
476  , m_init_val(0) {}
+
477 
+
478  sc_inout_opt(this_type& parent_)
+
479  : base_type(parent_)
+
480  , m_init_val(0) {}
+
481 
+
482  sc_inout_opt(const char* name_, this_type& parent_)
+
483  : base_type(name_, parent_)
+
484  , m_init_val(0) {}
+
485 
+
486  sc_inout_opt(const this_type&) = delete;
+
487 
+
488  virtual ~sc_inout_opt() = default;
+
489 
+
490  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
491 
+
492  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
493 
+
494  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
495 
+
496  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
497 
+
498  const data_type& read() const { return (*this)->read(); }
+
499 
+
500  operator const data_type&() const { return (*this)->read(); }
+
501 
+
502  bool event() const { return (*this)->event(); }
+
503 
+
504  bool posedge() const { return (*this)->posedge(); }
+
505 
+
506  bool negedge() const { return (*this)->negedge(); }
+
507 
+
508  void write(const data_type& value_) { (*this)->write(value_); }
+
509 
+
510  this_type& operator=(const data_type& value_) {
+
511  (*this)->write(value_);
+
512  return *this;
+
513  }
+
514 
+
515  this_type& operator=(const in_if_type& interface_) {
+
516  (*this)->write(interface_.read());
+
517  return *this;
+
518  }
+
519 
+
520  this_type& operator=(const in_port_type& port_) {
+
521  (*this)->write(port_->read());
+
522  return *this;
+
523  }
+
524 
+
525  this_type& operator=(const inout_port_type& port_) {
+
526  (*this)->write(port_->read());
+
527  return *this;
+
528  }
+
529 
+
530  this_type& operator=(const this_type& port_) {
+
531  (*this)->write(port_->read());
+
532  return *this;
+
533  }
+
534 
+
535  void initialize(const data_type& value_);
+
536 
+
537  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
538 
+
539  void end_of_elaboration() override {
+
540  if(m_init_val != 0) {
+
541  write(*m_init_val);
+
542  delete m_init_val;
+
543  m_init_val = 0;
+
544  }
+
545  }
+
546 
+
547  virtual const char* kind() const { return "sc_inout"; }
+
548 
+
549 protected:
+
550  data_type* m_init_val;
+
551 };
+
552 } // namespace scc
+
553 
+
554 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
555 
+
556 namespace scc {
+
557 template <>
+
558 class SC_API sc_inout_opt<sc_dt::sc_logic>
+
559 : public sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
560 public:
+
561  typedef sc_dt::sc_logic data_type;
+
562 
+
563  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
564  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
565  typedef sc_inout_opt<data_type> this_type;
+
566 
+
567  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
568  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
569  typedef if_type inout_if_type;
+
570  typedef base_type inout_port_type;
+
571 
+
572 public:
+
573  sc_inout_opt()
+
574  : base_type()
+
575  , m_init_val(0) {}
+
576 
+
577  explicit sc_inout_opt(const char* name_)
+
578  : base_type(name_)
+
579  , m_init_val(0) {}
+
580 
+
581  explicit sc_inout_opt(inout_if_type& interface_)
+
582  : base_type(interface_)
+
583  , m_init_val(0) {}
+
584 
+
585  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
586  : base_type(name_, interface_)
+
587  , m_init_val(0) {}
+
588 
+
589  explicit sc_inout_opt(inout_port_type& parent_)
+
590  : base_type(parent_)
+
591  , m_init_val(0) {}
+
592 
+
593  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
594  : base_type(name_, parent_)
+
595  , m_init_val(0) {}
+
596 
+
597  sc_inout_opt(this_type& parent_)
+
598  : base_type(parent_)
+
599  , m_init_val(0) {}
+
600 
+
601  sc_inout_opt(const char* name_, this_type& parent_)
+
602  : base_type(name_, parent_)
+
603  , m_init_val(0) {}
+
604 
+
605  sc_inout_opt(const this_type&) = delete;
+
606 
+
607  virtual ~sc_inout_opt();
+
608 
+
609  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
610 
+
611  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
612 
+
613  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
614 
+
615  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
616 
+
617  const data_type& read() const { return (*this)->read(); }
+
618 
+
619  operator const data_type&() const { return (*this)->read(); }
+
620 
+
621  bool event() const { return (*this)->event(); }
+
622 
+
623  bool posedge() const { return (*this)->posedge(); }
+
624 
+
625  bool negedge() const { return (*this)->negedge(); }
+
626 
+
627  void write(const data_type& value_) { (*this)->write(value_); }
+
628 
+
629  this_type& operator=(const data_type& value_) {
+
630  (*this)->write(value_);
+
631  return *this;
+
632  }
+
633 
+
634  this_type& operator=(const in_if_type& interface_) {
+
635  (*this)->write(interface_.read());
+
636  return *this;
+
637  }
+
638 
+
639  this_type& operator=(const in_port_type& port_) {
+
640  (*this)->write(port_->read());
+
641  return *this;
+
642  }
+
643 
+
644  this_type& operator=(const inout_port_type& port_) {
+
645  (*this)->write(port_->read());
+
646  return *this;
+
647  }
+
648 
+
649  this_type& operator=(const this_type& port_) {
+
650  (*this)->write(port_->read());
+
651  return *this;
+
652  }
+
653 
+
654  void initialize(const data_type& value_);
+
655 
+
656  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
657 
+
658  // called when elaboration is done
+
659  void end_of_elaboration() override {
+
660  if(m_init_val != 0) {
+
661  write(*m_init_val);
+
662  delete m_init_val;
+
663  m_init_val = 0;
+
664  }
+
665  }
+
666 
+
667  virtual const char* kind() const { return "sc_inout"; }
+
668 
+
669 protected:
+
670  data_type* m_init_val;
+
671 };
+
672 
+
673 template <class T> class sc_out_opt : public sc_inout_opt<T> {
+
674 public:
+
675  typedef T data_type;
+
676 
+
677  typedef sc_out_opt<data_type> this_type;
+
678  typedef sc_inout_opt<data_type> base_type;
+
679 
+
680  typedef typename base_type::in_if_type in_if_type;
+
681  typedef typename base_type::in_port_type in_port_type;
+
682  typedef typename base_type::inout_if_type inout_if_type;
+
683  typedef typename base_type::inout_port_type inout_port_type;
+
684 
+
685 public:
+
686  sc_out_opt()
+
687  : base_type() {}
+
688 
+
689  explicit sc_out_opt(const char* name_)
+
690  : base_type(name_) {}
+
691 
+
692  explicit sc_out_opt(inout_if_type& interface_)
+
693  : base_type(interface_) {}
+
694 
+
695  sc_out_opt(const char* name_, inout_if_type& interface_)
+
696  : base_type(name_, interface_) {}
+
697 
+
698  explicit sc_out_opt(inout_port_type& parent_)
+
699  : base_type(parent_) {}
+
700 
+
701  sc_out_opt(const char* name_, inout_port_type& parent_)
+
702  : base_type(name_, parent_) {}
+
703 
+
704  sc_out_opt(this_type& parent_)
+
705  : base_type(parent_) {}
+
706 
+
707  sc_out_opt(const char* name_, this_type& parent_)
+
708  : base_type(name_, parent_) {}
+
709 
+
710  virtual ~sc_out_opt() {}
+
711 
+
712  this_type& operator=(const data_type& value_) {
+
713  (*this)->write(value_);
+
714  return *this;
+
715  }
+
716 
+
717  this_type& operator=(const in_if_type& interface_) {
+
718  (*this)->write(interface_.read());
+
719  return *this;
+
720  }
+
721 
+
722  this_type& operator=(const in_port_type& port_) {
+
723  (*this)->write(port_->read());
+
724  return *this;
+
725  }
+
726 
+
727  this_type& operator=(const inout_port_type& port_) {
+
728  (*this)->write(port_->read());
+
729  return *this;
+
730  }
+
731 
+
732  this_type& operator=(const this_type& port_) {
+
733  (*this)->write(port_->read());
+
734  return *this;
+
735  }
+
736 
+
737  virtual const char* kind() const { return "sc_out"; }
+
738 
+
739 private:
+
740  sc_out_opt(const this_type&) = delete;
+
741 };
+
742 
+
743 template <class T> inline void sc_trace(sc_core::sc_trace_file* tf, const sc_in_opt<T>& port, const std::string& name) {
+
744  const sc_core::sc_signal_in_if<T>* iface = 0;
+
745  if(sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+
746  iface = dynamic_cast<const sc_core::sc_signal_in_if<T>*>(port.get_interface());
+
747  }
+
748  if(iface)
+
749  sc_trace(tf, iface->read(), name);
+
750  else
+
751  port.add_trace_internal(tf, name);
+
752 }
+
753 
+
754 template <class T> inline void sc_trace(sc_core::sc_trace_file* tf, const sc_inout_opt<T>& port, const std::string& name) {
+
755  const sc_core::sc_signal_in_if<T>* iface = 0;
+
756  if(sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+
757  iface = dynamic_cast<const sc_core::sc_signal_in_if<T>*>(port.get_interface());
+
758  }
+
759 
+
760  if(iface)
+
761  sc_trace(tf, iface->read(), name);
+
762  else
+
763  port.add_trace_internal(tf, name);
+
764 }
+
765 
+
766 } // namespace scc
+
767 
+
768 #undef SCC_VIRT
+
769 
+
770 #if defined(_MSC_VER) && !defined(SC_WIN_DLL_WARN)
+
771 #pragma warning(pop)
+
772 #endif
+
773 #endif /* SCC_SRC_SYSC_SCC_OPT_SIGNAL_PORTS_H_ */
+
scc::sc_in_opt
Definition: signal_opt_ports.h:39
+
scc::sc_inout_opt
Definition: signal_opt_ports.h:314
+
scc::sc_out_opt
Definition: signal_opt_ports.h:673
+
scc
SCC SystemC utilities.
Definition: clock_if_mixins.h:25
+
scc::operator<<
std::ostream & operator<<(std::ostream &os, log const &val)
output the textual representation of the log level
Definition: report.h:124
+
+
+ + + + diff --git a/develop/simple__ace__target_8h_source.html b/develop/simple__ace__target_8h_source.html new file mode 100644 index 00000000..ccdcbc48 --- /dev/null +++ b/develop/simple__ace__target_8h_source.html @@ -0,0 +1,149 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/simple_ace_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
simple_ace_target.h
+
+
+
1 /*
+
2  * Copyright 2020 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #pragma once
+
18 
+
19 #include <axi/pe/ace_target_pe.h>
+
20 
+
22 namespace axi {
+
24 namespace pe {
+
25 
+
26 
+
27 template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
+
28  sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+
29 class simple_ace_target : public ace_target_pe {
+
30 public:
+
31  using base = ace_target_pe;
+
32  using payload_type = base::payload_type;
+
33  using phase_type = base::phase_type;
+
34 
+
39  simple_ace_target(axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket)
+
40  : // @suppress("Class members should be properly initialized")
+
41  simple_ace_target(sc_core::sc_gen_unique_name("simple_ace_target"), socket) {}
+
42 
+
43  simple_ace_target(const sc_core::sc_module_name& nm, axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket)
+
44  : ace_target_pe(nm, BUSWIDTH)
+
45  , socket(socket) {
+
46  socket(*this);
+
47  this->instance_name = name();
+
48  }
+
49 
+
50  simple_ace_target() = delete;
+
51 
+
52  simple_ace_target(simple_ace_target const&) = delete;
+
53 
+
54  simple_ace_target(simple_ace_target&&) = delete;
+
55 
+
56  simple_ace_target& operator=(simple_ace_target const&) = delete;
+
57 
+
58  simple_ace_target& operator=(simple_ace_target&&) = delete;
+
59 
+
60 protected:
+
61  axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket;
+
62 
+
63  void end_of_elaboration(){
+
64  base::end_of_elaboration();
+
65  set_bw_interface(socket.get_base_port().operator -> ());
+
66  }
+
67 };
+
68 
+
69 } // namespace pe
+
70 } // namespace axi
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::simple_ace_target
Definition: simple_ace_target.h:29
+
axi::pe::simple_ace_target::simple_ace_target
simple_ace_target(axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
the constructor
Definition: simple_ace_target.h:39
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::ace_target_socket
Definition: axi_tlm.h:1031
+
axi::axi_protocol_types
The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicate...
Definition: axi_tlm.h:890
+
axi::fsm::base::payload_type
axi::axi_protocol_types::tlm_payload_type payload_type
aliases used in the class
Definition: base.h:45
+
+
+ + + + diff --git a/develop/structace__target__pe_1_1bw__intor__impl-members.html b/develop/structace__target__pe_1_1bw__intor__impl-members.html new file mode 100644 index 00000000..7c0130e4 --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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This is the complete list of members for axi::pe::ace_target_pe::bw_intor_impl, including all inherited members.

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bw_intor_impl(ace_target_pe *that) (defined in axi::pe::ace_target_pe::bw_intor_impl)axi::pe::ace_target_pe::bw_intor_implinline
that (defined in axi::pe::ace_target_pe::bw_intor_impl)axi::pe::ace_target_pe::bw_intor_impl
transport(tlm::tlm_generic_payload &payload) overrideaxi::pe::ace_target_pe::bw_intor_implinlinevirtual
+
+ + + + diff --git a/develop/structace__target__pe_1_1bw__intor__impl.html b/develop/structace__target__pe_1_1bw__intor__impl.html new file mode 100644 index 00000000..36066abd --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl.html @@ -0,0 +1,179 @@ + + + + + + + +scc: axi::pe::ace_target_pe::bw_intor_impl Struct Reference + + + + + + + + + + + +
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axi::pe::ace_target_pe::bw_intor_impl Struct Reference
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+Inheritance diagram for axi::pe::ace_target_pe::bw_intor_impl:
+
+
Inheritance graph
+ + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::ace_target_pe::bw_intor_impl:
+
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Collaboration graph
+ + + + + + + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Member Functions

+ bw_intor_impl (ace_target_pe *that)
 
unsigned transport (tlm::tlm_generic_payload &payload) override
 
+ + + +

+Public Attributes

+ace_target_pe *const that
 
+

Detailed Description

+
+

Definition at line 38 of file ace_target_pe.cpp.

+

Member Function Documentation

+ +

◆ transport()

+ +
+
+ + + + + +
+ + + + + + + + +
unsigned axi::pe::ace_target_pe::bw_intor_impl::transport (tlm::tlm_generic_payload & payload)
+ 		+inlineoverridevirtual
+
+

callback from the pe top if there is a backward transaction e.g. a snoop

+
Parameters
+ + +
payloadobject with (optional) extensions return the latency until reponse is sent by the protocol engine
+
+
+ +

Implements tlm::scc::pe::intor_bw< type::NB >.

+ +

Definition at line 42 of file ace_target_pe.cpp.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structace__target__pe_1_1bw__intor__impl.js b/develop/structace__target__pe_1_1bw__intor__impl.js new file mode 100644 index 00000000..ce1949ac --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl.js @@ -0,0 +1,6 @@ +var structace__target__pe_1_1bw__intor__impl = +[ + [ "bw_intor_impl", "structace__target__pe_1_1bw__intor__impl.html#a99569fc326770365b9844b3ce154cfe4", null ], + [ "transport", "structace__target__pe_1_1bw__intor__impl.html#a90ed1a3696a519297b09babd152dd046", null ], + [ "that", "structace__target__pe_1_1bw__intor__impl.html#aebe7f1b2a24d09f05ed1691c08a239ba", null ] +]; \ No newline at end of file diff --git a/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.map b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.map new file mode 100644 index 00000000..f7da658a --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.map @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 new file mode 100644 index 00000000..f104b799 --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 @@ -0,0 +1 @@ +82ac6046c0e9c7e3fc1a54c7d9f8a466 \ No newline at end of file diff --git a/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.png b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.png new file mode 100644 index 00000000..bdcb251e Binary files /dev/null and b/develop/structace__target__pe_1_1bw__intor__impl__coll__graph.png differ diff --git a/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.map b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.map new file mode 100644 index 00000000..0c30f2e7 --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 new file mode 100644 index 00000000..7f21655e --- /dev/null +++ b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 @@ -0,0 +1 @@ +82cb9a46a71dc54713dfbe73ce543aea \ No newline at end of file diff --git a/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.png b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.png new file mode 100644 index 00000000..7de8ba40 Binary files /dev/null and b/develop/structace__target__pe_1_1bw__intor__impl__inherit__graph.png differ diff --git a/develop/structahb_1_1enable__for__enum-members.html b/develop/structahb_1_1enable__for__enum-members.html new file mode 100644 index 00000000..13a8785e --- /dev/null +++ b/develop/structahb_1_1enable__for__enum-members.html @@ -0,0 +1,81 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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#include <ahb_tlm.h>

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+Static Public Attributes

+static const bool value = false
 
+

Detailed Description

+

template<typename Enum>
+struct ahb::enable_for_enum< Enum >

+ +

helper function to allow SFINAE

+ +

Definition at line 30 of file ahb_tlm.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ac__ace-members.html b/develop/structaxi_1_1ac__ace-members.html new file mode 100644 index 00000000..b872da6b --- /dev/null +++ b/develop/structaxi_1_1ac__ace-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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ac_ace()=default (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >inline
ac_addr (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_prot (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_ready (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_snoop (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_trace (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_valid (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_vmidext (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1ac__ace.html b/develop/structaxi_1_1ac__ace.html new file mode 100644 index 00000000..4684e1fd --- /dev/null +++ b/develop/structaxi_1_1ac__ace.html @@ -0,0 +1,132 @@ + + + + + + + +scc: axi::ac_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
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axi::ac_ace< CFG, TYPES > Struct Template Reference
+
+
+ +

snoop address(AC) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ ac_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ac (ac_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > ac_valid {"ac_valid"}
 
+TYPES::template m2s_t< bool > ac_ready {"ac_ready"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr {"ac_addr"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop {"ac_snoop"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot {"ac_prot"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext {"ac_vmidext"}
 
+TYPES::template s2m_opt_t< bool > ac_trace {"ac_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ac_ace< CFG, TYPES >

+ +

snoop address(AC) channel signals

+ +

Definition at line 629 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ac__ace.js b/develop/structaxi_1_1ac__ace.js new file mode 100644 index 00000000..78d6b7a5 --- /dev/null +++ b/develop/structaxi_1_1ac__ace.js @@ -0,0 +1,13 @@ +var structaxi_1_1ac__ace = +[ + [ "ac_ace", "structaxi_1_1ac__ace.html#a7f12a6f26a78eb889b8781f3b628807a", null ], + [ "ac_ace", "structaxi_1_1ac__ace.html#a205a0442d29ba62d0091e87db7456fee", null ], + [ "bind_ac", "structaxi_1_1ac__ace.html#a99c00143c3549fbe9243150371eed801", null ], + [ "ac_addr", "structaxi_1_1ac__ace.html#a12e62c4e4093cd4781a72044c1fc41d9", null ], + [ "ac_prot", "structaxi_1_1ac__ace.html#ac7c27ec04577d0403244e8d1b0b384d7", null ], + [ "ac_ready", "structaxi_1_1ac__ace.html#a481ba2d3cfb5ba45c25c91280819397c", null ], + [ "ac_snoop", "structaxi_1_1ac__ace.html#abbdc4b67011cb8c1233e4620c4a8eac4", null ], + [ "ac_trace", "structaxi_1_1ac__ace.html#a1ca7353b7d234a60cd312c16d8d5dca0", null ], + [ "ac_valid", "structaxi_1_1ac__ace.html#a41e8de8b8cad6c59c90ec3ce22db01d7", null ], + [ "ac_vmidext", "structaxi_1_1ac__ace.html#abaad313f5f0621be668749e31b03fd26", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1ace__cfg-members.html b/develop/structaxi_1_1ace__cfg-members.html new file mode 100644 index 00000000..a7a099d8 --- /dev/null +++ b/develop/structaxi_1_1ace__cfg-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Member List
+
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+ +

This is the complete list of members for axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >, including all inherited members.

+ + + + + + + + + + + +
ADDRWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
AWSNOOPWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
BUSWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
data_t typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
IDWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
IS_LITE (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
master_types typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
RESPWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
slave_types typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
USERWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
+
+ + + + diff --git a/develop/structaxi_1_1ace__cfg.html b/develop/structaxi_1_1ace__cfg.html new file mode 100644 index 00000000..1291f722 --- /dev/null +++ b/develop/structaxi_1_1ace__cfg.html @@ -0,0 +1,140 @@ + + + + + + + +scc: axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Struct Template Reference + + + + + + + + + + + +
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axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Struct Template Reference
+
+
+ +

#include <signal_if.h>

+ + + + + + + + +

+Public Types

+using data_t = typename select_if< BUSWDTH<=64, sc_dt::sc_uint< BUSWIDTH >, sc_dt::sc_biguint< BUSWIDTH > >::type
 
+using slave_types = ::axi::slave_types
 
+using master_types = ::axi::master_types
 
+ + + + + + + + + + + + + + + +

+Static Public Attributes

+constexpr static bool IS_LITE = false
 
+constexpr static unsigned int BUSWIDTH = BUSWDTH
 
+constexpr static unsigned int ADDRWIDTH = ADDRWDTH
 
+constexpr static unsigned int IDWIDTH = IDWDTH
 
+constexpr static unsigned int USERWIDTH = USERWDTH
 
+constexpr static unsigned int AWSNOOPWIDTH = AWSNOOPWDTH
 
+constexpr static unsigned int RESPWIDTH = RESPWDTH
 
+

Detailed Description

+

template<unsigned int BUSWDTH = 32, unsigned int ADDRWDTH = 32, unsigned int IDWDTH = 32, unsigned int USERWDTH = 1, unsigned int AWSNOOPWDTH = 3, unsigned int RESPWDTH = 4>
+struct axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >

+ +
Template Parameters
+ + + + + + +
BUSWDTH
ADDRWDTH
IDWDTH
USERWDTH
CACHELINEcacheline size in Bytes, defaults value is 64 bytes
+
+
+ +

Definition at line 113 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ace__cfg.js b/develop/structaxi_1_1ace__cfg.js new file mode 100644 index 00000000..b0332d08 --- /dev/null +++ b/develop/structaxi_1_1ace__cfg.js @@ -0,0 +1,6 @@ +var structaxi_1_1ace__cfg = +[ + [ "data_t", "structaxi_1_1ace__cfg.html#aaa70a4bef1d89a1f227fe6c01d47c3b2", null ], + [ "master_types", "structaxi_1_1ace__cfg.html#acb32c494beb36754cc37b59f5d6d19ad", null ], + [ "slave_types", "structaxi_1_1ace__cfg.html#a78a51e9fafdc11aa1c95fe096288a8b5", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1ar__ace-members.html b/develop/structaxi_1_1ar__ace-members.html new file mode 100644 index 00000000..25817697 --- /dev/null +++ b/develop/structaxi_1_1ar__ace-members.html @@ -0,0 +1,101 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1ar__ace.html b/develop/structaxi_1_1ar__ace.html new file mode 100644 index 00000000..4b35d7b4 --- /dev/null +++ b/develop/structaxi_1_1ar__ace.html @@ -0,0 +1,169 @@ + + + + + + + +scc: axi::ar_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_ace< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::ar_ace< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + +

+Public Member Functions

+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ar_ace< CFG, TYPES >

+ + +

Definition at line 488 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ar__ace.js b/develop/structaxi_1_1ar__ace.js new file mode 100644 index 00000000..65af5b95 --- /dev/null +++ b/develop/structaxi_1_1ar__ace.js @@ -0,0 +1,24 @@ +var structaxi_1_1ar__ace = +[ + [ "ar_ace", "structaxi_1_1ar__ace.html#a90b881d35bc3488833b6cd55a98d4c4f", null ], + [ "ar_ace", "structaxi_1_1ar__ace.html#aecc3da273e810265e10acde32e938080", null ], + [ "bind_ar", "structaxi_1_1ar__ace.html#a537d522808054c2a6fda2d670b4d1cb9", null ], + [ "ar_addr", "structaxi_1_1ar__ace.html#a0ea04250093710e45ff17b00f75212b4", null ], + [ "ar_bar", "structaxi_1_1ar__ace.html#a5816b68546b33fbacced3b8dbde34b59", null ], + [ "ar_burst", "structaxi_1_1ar__ace.html#a17eb2d5684c969e223346b02d21e3836", null ], + [ "ar_cache", "structaxi_1_1ar__ace.html#a9ca24e158c57ac4907a62e1277e2b4df", null ], + [ "ar_domain", "structaxi_1_1ar__ace.html#a448022ff0d7125cc951e1cebe5846b64", null ], + [ "ar_id", "structaxi_1_1ar__ace.html#a1dfadab2afde4f4dc8051b3e9bdc4b0a", null ], + [ "ar_len", "structaxi_1_1ar__ace.html#a2eb71a5b9e3472016b25da6a341ce339", null ], + [ "ar_lock", "structaxi_1_1ar__ace.html#a67f5551e5b440323b0b27e5b1176507e", null ], + [ "ar_prot", "structaxi_1_1ar__ace.html#a5135b590c14902d99574caddb9dc53fc", null ], + [ "ar_qos", "structaxi_1_1ar__ace.html#a53d7554423db040830f93e63b7eb83d6", null ], + [ "ar_ready", "structaxi_1_1ar__ace.html#a93458ad756a0ba69d7a41ee02cd7f0df", null ], + [ "ar_region", "structaxi_1_1ar__ace.html#a3d5af287233effc36acd3e2c56347b8e", null ], + [ "ar_size", "structaxi_1_1ar__ace.html#a5857dbefcb30209dfbb5a8a1d5c790d1", null ], + [ "ar_snoop", "structaxi_1_1ar__ace.html#af14c027656574ad6f5b9574d7c4baf42", null ], + [ "ar_trace", "structaxi_1_1ar__ace.html#a6f8b3e19c552127f973c606eba66937b", null ], + [ "ar_user", "structaxi_1_1ar__ace.html#a6f41cad331ee6365c58190f423c3c7dc", null ], + [ "ar_valid", "structaxi_1_1ar__ace.html#a6309b646ad504d6b406dc75d3d0b9366", null ], + [ "ar_vmidext", "structaxi_1_1ar__ace.html#ac239789e2bc9463280c2f06774c39c8b", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1ar__ace__inherit__graph.map b/develop/structaxi_1_1ar__ace__inherit__graph.map new file mode 100644 index 00000000..059f8ef9 --- /dev/null +++ b/develop/structaxi_1_1ar__ace__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/develop/structaxi_1_1ar__ace__inherit__graph.md5 b/develop/structaxi_1_1ar__ace__inherit__graph.md5 new file mode 100644 index 00000000..430384b8 --- /dev/null +++ b/develop/structaxi_1_1ar__ace__inherit__graph.md5 @@ -0,0 +1 @@ +dff80b7d67681589801b80cd072c9aba \ No newline at end of file diff --git a/develop/structaxi_1_1ar__ace__inherit__graph.png b/develop/structaxi_1_1ar__ace__inherit__graph.png new file mode 100644 index 00000000..3102a9af Binary files /dev/null and b/develop/structaxi_1_1ar__ace__inherit__graph.png differ diff --git a/develop/structaxi_1_1ar__axi-members.html b/develop/structaxi_1_1ar__axi-members.html new file mode 100644 index 00000000..92a32ec9 --- /dev/null +++ b/develop/structaxi_1_1ar__axi-members.html @@ -0,0 +1,97 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
axi::ar_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::ar_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
ar_addr (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_axi()=default (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_axi(const char *prefix) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
ar_burst (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_cache (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_id (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_len (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_lock (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_prot (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_qos (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_ready (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_region (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_size (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_user (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_valid (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
bind_ar(ar_axi< CFG, OTYPES > &o) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
bind_ar(ar_axi_lite< CFG, OTYPES > &o) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1ar__axi.html b/develop/structaxi_1_1ar__axi.html new file mode 100644 index 00000000..a0cced52 --- /dev/null +++ b/develop/structaxi_1_1ar__axi.html @@ -0,0 +1,148 @@ + + + + + + + +scc: axi::ar_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_axi< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ ar_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_ar (ar_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_full_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ar_axi< CFG, TYPES >

+ + +

Definition at line 257 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ar__axi.js b/develop/structaxi_1_1ar__axi.js new file mode 100644 index 00000000..ef561e1a --- /dev/null +++ b/develop/structaxi_1_1ar__axi.js @@ -0,0 +1,20 @@ +var structaxi_1_1ar__axi = +[ + [ "ar_axi", "structaxi_1_1ar__axi.html#a3d195e95fdbc646ec15d0bdc0b32b496", null ], + [ "ar_axi", "structaxi_1_1ar__axi.html#a88f351ac148f13a7d15db8d3087179f6", null ], + [ "bind_ar", "structaxi_1_1ar__axi.html#a1c92de6db75ee6be9d107b1d183ea025", null ], + [ "bind_ar", "structaxi_1_1ar__axi.html#a7b81c3af189dc0b86fa2dd50707057bf", null ], + [ "ar_addr", "structaxi_1_1ar__axi.html#af7a334ef7ad2a7d378df2e1c98f88b54", null ], + [ "ar_burst", "structaxi_1_1ar__axi.html#a36d4e904cba5fb734690635cd8c733c2", null ], + [ "ar_cache", "structaxi_1_1ar__axi.html#a5446d572d85ddcd34454b8f5a51c55e0", null ], + [ "ar_id", "structaxi_1_1ar__axi.html#ab7ba8d1f07e6509b54538820025629fe", null ], + [ "ar_len", "structaxi_1_1ar__axi.html#a96f91b9fe4f0ede97b7cd7021789e6e0", null ], + [ "ar_lock", "structaxi_1_1ar__axi.html#ae080cabb8f779ad17eaef647968cbd34", null ], + [ "ar_prot", "structaxi_1_1ar__axi.html#a050a8869e3931ef03ab7907d5073fa4e", null ], + [ "ar_qos", "structaxi_1_1ar__axi.html#ace6839efc234fb3f41de97fa8d6b1365", null ], + [ "ar_ready", "structaxi_1_1ar__axi.html#a2e34821f1ed6f199613f3bca9d1a82e4", null ], + [ "ar_region", "structaxi_1_1ar__axi.html#a6374ac4e68b9d3fb489bf62e9fb06b91", null ], + [ "ar_size", "structaxi_1_1ar__axi.html#a75477f2b16d8c58eafd30a145216b1c6", null ], + [ "ar_user", "structaxi_1_1ar__axi.html#a1eb42419f6809b929b604f67f95bc56d", null ], + [ "ar_valid", "structaxi_1_1ar__axi.html#a56f558bc72b0439837e4bf9e649908d9", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1ar__axi__lite-members.html b/develop/structaxi_1_1ar__axi__lite-members.html new file mode 100644 index 00000000..b857d501 --- /dev/null +++ b/develop/structaxi_1_1ar__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::ar_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::ar_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
ar_addr (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_axi_lite()=default (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_axi_lite(const char *prefix) (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >inline
ar_prot (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_ready (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_valid (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
bind_ar(ar_axi< CFG, OTYPES > &o) (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1ar__axi__lite.html b/develop/structaxi_1_1ar__axi__lite.html new file mode 100644 index 00000000..c06c556d --- /dev/null +++ b/develop/structaxi_1_1ar__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::ar_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

read address channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ ar_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::ar_axi_lite< CFG, TYPES >

+ +

read address channel signals

+ +

Definition at line 445 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1ar__axi__lite.js b/develop/structaxi_1_1ar__axi__lite.js new file mode 100644 index 00000000..8c8dc75f --- /dev/null +++ b/develop/structaxi_1_1ar__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1ar__axi__lite = +[ + [ "ar_axi_lite", "structaxi_1_1ar__axi__lite.html#acc231e9b1de65fe2617694e002441f90", null ], + [ "ar_axi_lite", "structaxi_1_1ar__axi__lite.html#a9147e4184e018b567f6bbcd4309a5981", null ], + [ "bind_ar", "structaxi_1_1ar__axi__lite.html#a3b1a092a6041f144398a215a5cda1bde", null ], + [ "ar_addr", "structaxi_1_1ar__axi__lite.html#a001192fae236f6a7904e2a014f0603cc", null ], + [ "ar_prot", "structaxi_1_1ar__axi__lite.html#abf9619f836bf24ce99e25164e1ab7190", null ], + [ "ar_ready", "structaxi_1_1ar__axi__lite.html#a80e012a3eafa442047977c4b938d738e", null ], + [ "ar_valid", "structaxi_1_1ar__axi__lite.html#adce67c05ec447d5b9fa1381b64229178", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1aw__ace-members.html b/develop/structaxi_1_1aw__ace-members.html new file mode 100644 index 00000000..1bfed79e --- /dev/null +++ b/develop/structaxi_1_1aw__ace-members.html @@ -0,0 +1,106 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::aw_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1aw__ace.html b/develop/structaxi_1_1aw__ace.html new file mode 100644 index 00000000..dbdb8748 --- /dev/null +++ b/develop/structaxi_1_1aw__ace.html @@ -0,0 +1,184 @@ + + + + + + + +scc: axi::aw_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_ace< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::aw_ace< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + +

+Public Member Functions

+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::aw_ace< CFG, TYPES >

+ + +

Definition at line 550 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1aw__ace.js b/develop/structaxi_1_1aw__ace.js new file mode 100644 index 00000000..89dd9d5f --- /dev/null +++ b/develop/structaxi_1_1aw__ace.js @@ -0,0 +1,29 @@ +var structaxi_1_1aw__ace = +[ + [ "aw_ace", "structaxi_1_1aw__ace.html#a8ee008f32c5bad39b223590ff99c1671", null ], + [ "aw_ace", "structaxi_1_1aw__ace.html#a11230182f78eaf3f14a076742c761bd5", null ], + [ "bind_aw", "structaxi_1_1aw__ace.html#a2920186581f940ac01a8cf6e65e332e8", null ], + [ "aw_addr", "structaxi_1_1aw__ace.html#a227425ac3a4a9059a55f4b9cd2e08645", null ], + [ "aw_atop", "structaxi_1_1aw__ace.html#a6120844e144f5096d90c43b2f4cd49fd", null ], + [ "aw_bar", "structaxi_1_1aw__ace.html#af35c8a880ac498e46b8408a99e2b1215", null ], + [ "aw_burst", "structaxi_1_1aw__ace.html#a66a26a833eac2a5a2c923bd99e822560", null ], + [ "aw_cache", "structaxi_1_1aw__ace.html#a0abb831248bd51a87cab07e5bfa5326c", null ], + [ "aw_domain", "structaxi_1_1aw__ace.html#a1e1d9b044a7d2c93fc23e182043d0b4c", null ], + [ "aw_id", "structaxi_1_1aw__ace.html#a6e6e4bdea813509885c202405576425a", null ], + [ "aw_len", "structaxi_1_1aw__ace.html#a75f8e6386453d35c47f3242263260159", null ], + [ "aw_lock", "structaxi_1_1aw__ace.html#ae22068addc19cb0d5333928de7657657", null ], + [ "aw_prot", "structaxi_1_1aw__ace.html#acf0b2cba1d81ea66aa17aa46bea138e3", null ], + [ "aw_qos", "structaxi_1_1aw__ace.html#a8d59ed12058ef90947f89e12957d24ed", null ], + [ "aw_ready", "structaxi_1_1aw__ace.html#a737c40bb0af91ed2b5423a9e6e0500d8", null ], + [ "aw_region", "structaxi_1_1aw__ace.html#aee512fbdbbf76668bd4a7d5df0398236", null ], + [ "aw_size", "structaxi_1_1aw__ace.html#a8adc53ed71650ae6176bbfffd282849f", null ], + [ "aw_snoop", "structaxi_1_1aw__ace.html#a278a0012a959e89bd53b4529b3e31f6d", null ], + [ "aw_stashlpid", "structaxi_1_1aw__ace.html#a46e59beaec42e5d591f7ee10510d0cc4", null ], + [ "aw_stashlpiden", "structaxi_1_1aw__ace.html#aee71386e70c4067ecfe5a83bc845aef7", null ], + [ "aw_stashnid", "structaxi_1_1aw__ace.html#a8aec42a4e6c64ffdd8e0e3be6999be31", null ], + [ "aw_stashniden", "structaxi_1_1aw__ace.html#a06f156cb8a10a0b9242fe3dcacb67a81", null ], + [ "aw_trace", "structaxi_1_1aw__ace.html#a6adb34349525bbbb298b7d193563e29f", null ], + [ "aw_unique", "structaxi_1_1aw__ace.html#aaf3e6c9c513c53f08d6b2c9ad28b8f94", null ], + [ "aw_user", "structaxi_1_1aw__ace.html#ad8d4f3e1467b8d39c11cb8b12cf555d9", null ], + [ "aw_valid", "structaxi_1_1aw__ace.html#ac0f33b39f6092d7292f4867b0c3e146f", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1aw__ace__inherit__graph.map b/develop/structaxi_1_1aw__ace__inherit__graph.map new file mode 100644 index 00000000..6a175d4c --- /dev/null +++ b/develop/structaxi_1_1aw__ace__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/develop/structaxi_1_1aw__ace__inherit__graph.md5 b/develop/structaxi_1_1aw__ace__inherit__graph.md5 new file mode 100644 index 00000000..715376fa --- /dev/null +++ b/develop/structaxi_1_1aw__ace__inherit__graph.md5 @@ -0,0 +1 @@ +fbf849779eef827ae547685ae28b43ec \ No newline at end of file diff --git a/develop/structaxi_1_1aw__ace__inherit__graph.png b/develop/structaxi_1_1aw__ace__inherit__graph.png new file mode 100644 index 00000000..b41f12d5 Binary files /dev/null and b/develop/structaxi_1_1aw__ace__inherit__graph.png differ diff --git a/develop/structaxi_1_1aw__axi-members.html b/develop/structaxi_1_1aw__axi-members.html new file mode 100644 index 00000000..5793ddc8 --- /dev/null +++ b/develop/structaxi_1_1aw__axi-members.html @@ -0,0 +1,97 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::aw_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
aw_addr (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_axi()=default (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_axi(const char *prefix) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
aw_burst (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_cache (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_id (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_len (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_lock (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_prot (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_qos (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_ready (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_region (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_size (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_user (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_valid (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
bind_aw(aw_axi< CFG, OTYPES > &o) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
bind_aw(aw_axi_lite< CFG, OTYPES > &o) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1aw__axi.html b/develop/structaxi_1_1aw__axi.html new file mode 100644 index 00000000..beeeffe5 --- /dev/null +++ b/develop/structaxi_1_1aw__axi.html @@ -0,0 +1,148 @@ + + + + + + + +scc: axi::aw_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_axi< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ aw_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_aw (aw_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_full_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::aw_axi< CFG, TYPES >

+ + +

Definition at line 135 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1aw__axi.js b/develop/structaxi_1_1aw__axi.js new file mode 100644 index 00000000..76e90546 --- /dev/null +++ b/develop/structaxi_1_1aw__axi.js @@ -0,0 +1,20 @@ +var structaxi_1_1aw__axi = +[ + [ "aw_axi", "structaxi_1_1aw__axi.html#a1ae93639fa8f621657d69356d2b35324", null ], + [ "aw_axi", "structaxi_1_1aw__axi.html#ad4ed11f8b322a5e0547aea12cafc647a", null ], + [ "bind_aw", "structaxi_1_1aw__axi.html#a06386e5df3ec241ae73754d4d29deeed", null ], + [ "bind_aw", "structaxi_1_1aw__axi.html#a1b945e5d450793b96dbded157dc023f0", null ], + [ "aw_addr", "structaxi_1_1aw__axi.html#a95a93f2d5500c2ca9400d4acbee084b4", null ], + [ "aw_burst", "structaxi_1_1aw__axi.html#a8ef8cd22ff3ede0a331a09778f65e9e2", null ], + [ "aw_cache", "structaxi_1_1aw__axi.html#a69784a13ffeb6cd87a5dc1c4d24b46ab", null ], + [ "aw_id", "structaxi_1_1aw__axi.html#af184c6dbb307ee13984dcf07d5c3dd16", null ], + [ "aw_len", "structaxi_1_1aw__axi.html#a5378c903a0efeb261545ec42d003cf0b", null ], + [ "aw_lock", "structaxi_1_1aw__axi.html#a32f51690a61b12b1096a768f15ba1e1c", null ], + [ "aw_prot", "structaxi_1_1aw__axi.html#aa86baacec21734c5b925100c873f49c4", null ], + [ "aw_qos", "structaxi_1_1aw__axi.html#ae22c275884bb540adc44a6a87e429d31", null ], + [ "aw_ready", "structaxi_1_1aw__axi.html#a41eb358c188d504cdcc4e2e1ef8a5e27", null ], + [ "aw_region", "structaxi_1_1aw__axi.html#a746f5b3bb1578552b1594f111e08c2b2", null ], + [ "aw_size", "structaxi_1_1aw__axi.html#ac616e988c71577925667f6b4a9b7ce65", null ], + [ "aw_user", "structaxi_1_1aw__axi.html#a5ad9cabdddca274251a5262bb6bb0a89", null ], + [ "aw_valid", "structaxi_1_1aw__axi.html#a52fe9d89ec42d12567530fed5f4f25e9", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1aw__axi__lite-members.html b/develop/structaxi_1_1aw__axi__lite-members.html new file mode 100644 index 00000000..7ef4af29 --- /dev/null +++ b/develop/structaxi_1_1aw__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
axi::aw_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
aw_addr (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_axi_lite()=default (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_axi_lite(const char *prefix) (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >inline
aw_prot (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_ready (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_valid (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
bind_aw(aw_axi< CFG, OTYPES > &o) (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1aw__axi__lite.html b/develop/structaxi_1_1aw__axi__lite.html new file mode 100644 index 00000000..7668756a --- /dev/null +++ b/develop/structaxi_1_1aw__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::aw_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

Write address channel signals. + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ aw_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::aw_axi_lite< CFG, TYPES >

+ +

Write address channel signals.

+ +

Definition at line 382 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1aw__axi__lite.js b/develop/structaxi_1_1aw__axi__lite.js new file mode 100644 index 00000000..ffbf7a15 --- /dev/null +++ b/develop/structaxi_1_1aw__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1aw__axi__lite = +[ + [ "aw_axi_lite", "structaxi_1_1aw__axi__lite.html#a6d89a287f208379c2ffbc61ac659311e", null ], + [ "aw_axi_lite", "structaxi_1_1aw__axi__lite.html#a3f955b7919c8445f760e6b34fa50af16", null ], + [ "bind_aw", "structaxi_1_1aw__axi__lite.html#a2215df66981d5092a8d042e6cb4b4081", null ], + [ "aw_addr", "structaxi_1_1aw__axi__lite.html#a7a883a2e12c40851edb1392040c7be24", null ], + [ "aw_prot", "structaxi_1_1aw__axi__lite.html#a2cd35c3d538e7c5c67c352e6f2341ef2", null ], + [ "aw_ready", "structaxi_1_1aw__axi__lite.html#ad2c3880d655c73a5dacb55eac53c7812", null ], + [ "aw_valid", "structaxi_1_1aw__axi__lite.html#a00c5c087758f4deed41eb9b37f634685", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1b__axi-members.html b/develop/structaxi_1_1b__axi-members.html new file mode 100644 index 00000000..fbd85dd9 --- /dev/null +++ b/develop/structaxi_1_1b__axi-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::b_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::b_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + +
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1b__axi.html b/develop/structaxi_1_1b__axi.html new file mode 100644 index 00000000..feb4eb8c --- /dev/null +++ b/develop/structaxi_1_1b__axi.html @@ -0,0 +1,139 @@ + + + + + + + +scc: axi::b_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Public Member Functions | +Public Attributes | +List of all members
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axi::b_axi< CFG, TYPES > Struct Template Reference
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+Inheritance diagram for axi::b_axi< CFG, TYPES >:
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Inheritance graph
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[legend]
+ + + + + + + + + + +

+Public Member Functions

+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::b_axi< CFG, TYPES >

+ + +

Definition at line 227 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1b__axi.js b/develop/structaxi_1_1b__axi.js new file mode 100644 index 00000000..a2f3ad47 --- /dev/null +++ b/develop/structaxi_1_1b__axi.js @@ -0,0 +1,13 @@ +var structaxi_1_1b__axi = +[ + [ "b_axi", "structaxi_1_1b__axi.html#ac8b64af8a73506bbd755d3e2355de575", null ], + [ "b_axi", "structaxi_1_1b__axi.html#a2f0552ce13ab10650d258017b9f6d499", null ], + [ "bind_b", "structaxi_1_1b__axi.html#a5384501b6dd4d2fd4ad9a22120b89b4e", null ], + [ "bind_b", "structaxi_1_1b__axi.html#ab71b6877ad0df31c81ac916faedfd04e", null ], + [ "b_id", "structaxi_1_1b__axi.html#ad778ea1b2d6c4f86aad167a4ee2b5e1a", null ], + [ "b_ready", "structaxi_1_1b__axi.html#ac3e7e99f64569f52ab1450b226b5d5e3", null ], + [ "b_resp", "structaxi_1_1b__axi.html#ac8fb04c79763f46cf5bfdb7fe8f627f2", null ], + [ "b_trace", "structaxi_1_1b__axi.html#adf4625698a24b9d4611b6b086fa07e53", null ], + [ "b_user", "structaxi_1_1b__axi.html#ad526d28d79c2e1c67b197e864b71124f", null ], + [ "b_valid", "structaxi_1_1b__axi.html#a59d42372be2059cf18737170bfc0e52f", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1b__axi__inherit__graph.map b/develop/structaxi_1_1b__axi__inherit__graph.map new file mode 100644 index 00000000..e4edc223 --- /dev/null +++ b/develop/structaxi_1_1b__axi__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/develop/structaxi_1_1b__axi__inherit__graph.md5 b/develop/structaxi_1_1b__axi__inherit__graph.md5 new file mode 100644 index 00000000..dcd12e29 --- /dev/null +++ b/develop/structaxi_1_1b__axi__inherit__graph.md5 @@ -0,0 +1 @@ +4db927dc6c0fd526952e19b3bd8d5ff5 \ No newline at end of file diff --git a/develop/structaxi_1_1b__axi__inherit__graph.png b/develop/structaxi_1_1b__axi__inherit__graph.png new file mode 100644 index 00000000..fc0ba9e7 Binary files /dev/null and b/develop/structaxi_1_1b__axi__inherit__graph.png differ diff --git a/develop/structaxi_1_1b__axi__lite-members.html b/develop/structaxi_1_1b__axi__lite-members.html new file mode 100644 index 00000000..1a8e694a --- /dev/null +++ b/develop/structaxi_1_1b__axi__lite-members.html @@ -0,0 +1,86 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::b_axi_lite< CFG, TYPES > Member List
+
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+ +

This is the complete list of members for axi::b_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + +
b_axi_lite()=default (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_axi_lite(const char *prefix) (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >inline
b_ready (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_resp (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_valid (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1b__axi__lite.html b/develop/structaxi_1_1b__axi__lite.html new file mode 100644 index 00000000..76b88eaf --- /dev/null +++ b/develop/structaxi_1_1b__axi__lite.html @@ -0,0 +1,120 @@ + + + + + + + +scc: axi::b_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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axi::b_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

write response channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ b_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+ + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::b_axi_lite< CFG, TYPES >

+ +

write response channel signals

+ +

Definition at line 426 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1b__axi__lite.js b/develop/structaxi_1_1b__axi__lite.js new file mode 100644 index 00000000..78963aa2 --- /dev/null +++ b/develop/structaxi_1_1b__axi__lite.js @@ -0,0 +1,9 @@ +var structaxi_1_1b__axi__lite = +[ + [ "b_axi_lite", "structaxi_1_1b__axi__lite.html#a4b31a8b0dbf6f7c81d8ff4ec0a172b4a", null ], + [ "b_axi_lite", "structaxi_1_1b__axi__lite.html#a5eed554019dc9cdf02cf49d3f79ff4c8", null ], + [ "bind_b", "structaxi_1_1b__axi__lite.html#a4870cdf806fce130c00c47c28bcdf65b", null ], + [ "b_ready", "structaxi_1_1b__axi__lite.html#aaa75388c9fde2795604c5d02aa2ba93f", null ], + [ "b_resp", "structaxi_1_1b__axi__lite.html#ae70877ef1a3ed10b950a9f68c19dc83c", null ], + [ "b_valid", "structaxi_1_1b__axi__lite.html#ad4d5afb18405db41942c158db9900f7f", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1cd__ace-members.html b/develop/structaxi_1_1cd__ace-members.html new file mode 100644 index 00000000..e6cd4e2a --- /dev/null +++ b/develop/structaxi_1_1cd__ace-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
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+
+
axi::cd_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::cd_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >inline
cd_ace()=default (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >inline
cd_data (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_last (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_ready (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_valid (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
+
+ + + + diff --git a/develop/structaxi_1_1cd__ace.html b/develop/structaxi_1_1cd__ace.html new file mode 100644 index 00000000..7c331430 --- /dev/null +++ b/develop/structaxi_1_1cd__ace.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::cd_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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axi::cd_ace< CFG, TYPES > Struct Template Reference
+
+
+ +

snoop data(cd) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ cd_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_cd (cd_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< bool > cd_valid {"cd_valid"}
 
+TYPES::template s2m_t< bool > cd_ready {"cd_ready"}
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data {"cd_data"}
 
+TYPES::template m2s_full_t< bool > cd_last {"cd_last"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::cd_ace< CFG, TYPES >

+ +

snoop data(cd) channel signals

+ +

Definition at line 658 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1cd__ace.js b/develop/structaxi_1_1cd__ace.js new file mode 100644 index 00000000..aed6ccbb --- /dev/null +++ b/develop/structaxi_1_1cd__ace.js @@ -0,0 +1,10 @@ +var structaxi_1_1cd__ace = +[ + [ "cd_ace", "structaxi_1_1cd__ace.html#a3d53f0b6b46f592b722c61d02c4ba92a", null ], + [ "cd_ace", "structaxi_1_1cd__ace.html#aae1cd6099a2dcd6abdbeb67d8249c722", null ], + [ "bind_cd", "structaxi_1_1cd__ace.html#a7dec2b4407bfaa57eb5a085f8d3f3812", null ], + [ "cd_data", "structaxi_1_1cd__ace.html#a00284bf066c2c49329287071dd739609", null ], + [ "cd_last", "structaxi_1_1cd__ace.html#a431355e2ad70a5f63b5ea43a3f3af178", null ], + [ "cd_ready", "structaxi_1_1cd__ace.html#ad2946289ea7761c5f0b90694452ae674", null ], + [ "cd_valid", "structaxi_1_1cd__ace.html#a39db9eb2463e91e8098cb72def40323c", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1cr__ace-members.html b/develop/structaxi_1_1cr__ace-members.html new file mode 100644 index 00000000..a366e6e4 --- /dev/null +++ b/develop/structaxi_1_1cr__ace-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
+
axi::cr_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::cr_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >inline
cr_ace()=default (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >inline
cr_ready (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_resp (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_trace (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_valid (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
+
+ + + + diff --git a/develop/structaxi_1_1cr__ace.html b/develop/structaxi_1_1cr__ace.html new file mode 100644 index 00000000..0c063e74 --- /dev/null +++ b/develop/structaxi_1_1cr__ace.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::cr_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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axi::cr_ace< CFG, TYPES > Struct Template Reference
+
+
+ +

snoop response(cr) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ cr_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_cr (cr_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< bool > cr_valid {"cr_valid"}
 
+TYPES::template s2m_t< bool > cr_ready {"cr_ready"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp {"cr_resp"}
 
+TYPES::template m2s_opt_t< bool > cr_trace {"cr_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::cr_ace< CFG, TYPES >

+ +

snoop response(cr) channel signals

+ +

Definition at line 680 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1cr__ace.js b/develop/structaxi_1_1cr__ace.js new file mode 100644 index 00000000..394158a9 --- /dev/null +++ b/develop/structaxi_1_1cr__ace.js @@ -0,0 +1,10 @@ +var structaxi_1_1cr__ace = +[ + [ "cr_ace", "structaxi_1_1cr__ace.html#a7f57b89834f5f20169c3cae39c2b5fd3", null ], + [ "cr_ace", "structaxi_1_1cr__ace.html#a756a5dfcc5423df7dd22bf23f7a388d4", null ], + [ "bind_cr", "structaxi_1_1cr__ace.html#ac5960e32578fb91509ae62abb41a9a9a", null ], + [ "cr_ready", "structaxi_1_1cr__ace.html#ab6d7c05c328f52372f888aae360160df", null ], + [ "cr_resp", "structaxi_1_1cr__ace.html#a925927830e3bb5264db0b7f5a022bde3", null ], + [ "cr_trace", "structaxi_1_1cr__ace.html#a80dcfde5dd8cfd0aa895564346901bad", null ], + [ "cr_valid", "structaxi_1_1cr__ace.html#acfc5e6ca6da8ef7281ae3df05b41a924", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__initiator-members.html b/develop/structaxi_1_1pin_1_1ace__initiator-members.html new file mode 100644 index 00000000..9ad1ae9b --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator-members.html @@ -0,0 +1,221 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+ +
+
+
+ +
+
+
+
axi::pin::ace_initiator< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_initiator< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ac_ace()=default (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >inline
ac_addr (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_prot (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_ready (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_snoop (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_trace (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_valid (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_vmidext (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ace_initiator(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >inline
ar_addr (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_bar (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_burst (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_cache (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_domain (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_id (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_len (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_lock (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_prot (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_qos (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_ready (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_region (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_size (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_snoop (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_trace (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_user (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_valid (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_vmidext (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
aw_ace()=default (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >inline
aw_addr (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_atop (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_bar (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_burst (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_cache (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_domain (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_id (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_len (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_lock (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_prot (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_qos (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_ready (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_region (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_size (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_snoop (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashlpid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashlpiden (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashnid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashniden (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_trace (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_unique (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_user (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_valid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >inline
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >inline
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >inline
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
CACHELINE_SZ enum value (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
cd_ace()=default (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >inline
cd_data (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_last (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_ready (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_valid (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
clk_i (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
cr_ace()=default (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >inline
cr_ready (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_resp (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_trace (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_valid (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
phase_type typedef (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_ack (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_data (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_id (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_last (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_ready (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_resp (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_trace (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_user (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_valid (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_ace()=default (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
SC_HAS_PROCESS(ace_initiator) (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
tsckt (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__initiator.html b/develop/structaxi_1_1pin_1_1ace__initiator.html new file mode 100644 index 00000000..0d2fe920 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator.html @@ -0,0 +1,585 @@ + + + + + + + +scc: axi::pin::ace_initiator< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_initiator< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_initiator< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_initiator< CFG >:
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+
Collaboration graph
+ + + + + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + + + +

+Public Types

enum  { CACHELINE_SZ = 64 + }
 
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_initiator)
 
+ ace_initiator (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, CFG::master_types >
+ aw_ace (const char *prefix)
 
+void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, CFG::master_types >
+ ar_ace (const char *prefix)
 
+void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_ace< CFG, CFG::master_types >
+ rresp_ace (const char *prefix)
 
+void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ac_ace< CFG, CFG::master_types >
+ ac_ace (const char *prefix)
 
+void bind_ac (ac_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cr_ace< CFG, CFG::master_types >
+ cr_ace (const char *prefix)
 
+void bind_cr (cr_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cd_ace< CFG, CFG::master_types >
+ cd_ace (const char *prefix)
 
+void bind_cd (cd_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::ace_target_socket< CFG::BUSWIDTH > tsckt {"tsckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, CFG::master_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr
 
+TYPES::template s2m_t< bool > aw_ready
 
+TYPES::template m2s_t< bool > aw_lock
 
+TYPES::template m2s_t< bool > aw_valid
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar
 
+TYPES::template m2s_t< bool > aw_unique
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user
 
+TYPES::template m2s_t< bool > aw_stashniden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid
 
+TYPES::template m2s_t< bool > aw_stashlpiden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop
 
+TYPES::template m2s_opt_t< bool > aw_trace
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, CFG::master_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst
 
+TYPES::template m2s_t< bool > ar_lock
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region
 
+TYPES::template m2s_t< bool > ar_valid
 
+TYPES::template s2m_t< bool > ar_ready
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user
 
+TYPES::template m2s_opt_t< bool > ar_trace
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext
 
- Public Attributes inherited from axi::rresp_ace< CFG, CFG::master_types >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id
 
+TYPES::template s2m_t< typename CFG::data_t > r_data
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp
 
+TYPES::template s2m_full_t< bool > r_last
 
+TYPES::template s2m_t< bool > r_valid
 
+TYPES::template m2s_t< bool > r_ready
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user
 
+TYPES::template s2m_opt_t< bool > r_trace
 
+TYPES::template m2s_t< bool > r_ack
 
- Public Attributes inherited from axi::ac_ace< CFG, CFG::master_types >
+TYPES::template s2m_t< bool > ac_valid
 
+TYPES::template m2s_t< bool > ac_ready
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext
 
+TYPES::template s2m_opt_t< bool > ac_trace
 
- Public Attributes inherited from axi::cr_ace< CFG, CFG::master_types >
+TYPES::template m2s_t< bool > cr_valid
 
+TYPES::template s2m_t< bool > cr_ready
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp
 
+TYPES::template m2s_opt_t< bool > cr_trace
 
- Public Attributes inherited from axi::cd_ace< CFG, CFG::master_types >
+TYPES::template m2s_t< bool > cd_valid
 
+TYPES::template s2m_t< bool > cd_ready
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data
 
+TYPES::template m2s_full_t< bool > cd_last
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_initiator< CFG >

+ + +

Definition at line 36 of file ace_initiator.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__initiator.js b/develop/structaxi_1_1pin_1_1ace__initiator.js new file mode 100644 index 00000000..f30d6e20 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__initiator = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__initiator.html#ad638947a22e1cf0a460b89537b8c120f", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__initiator.html#a40110f88df445005684d5ce4f6e5d847", null ], + [ "ace_initiator", "structaxi_1_1pin_1_1ace__initiator.html#ae3ea71803abf5439d7f739b099681490", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__initiator.html#a69a885243b851c2a38b0fe64598877ae", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__initiator.html#ac97c937183d8c8a9ca51e2b2f4d05e6e", null ], + [ "tsckt", "structaxi_1_1pin_1_1ace__initiator.html#a1e0e18e90549401a60832e66ccb25e63", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.map b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.map new file mode 100644 index 00000000..01687720 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.map @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 new file mode 100644 index 00000000..5765ff53 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 @@ -0,0 +1 @@ +6d3172af64431c871f05a273be532a32 \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.png b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.png new file mode 100644 index 00000000..d51011ca Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__initiator__coll__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map new file mode 100644 index 00000000..52fcea89 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 new file mode 100644 index 00000000..381cc4a3 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 @@ -0,0 +1 @@ +50e5ea5162ea1b5eeac879bb9ef400c8 \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png new file mode 100644 index 00000000..0e605051 Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator-members.html b/develop/structaxi_1_1pin_1_1ace__lite__initiator-members.html new file mode 100644 index 00000000..a889995c --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator-members.html @@ -0,0 +1,197 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pin::ace_lite_initiator< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_lite_initiator< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_lite_initiator(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
clk_i (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
phase_type typedef (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
SC_HAS_PROCESS(ace_lite_initiator) (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
tsckt (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator.html b/develop/structaxi_1_1pin_1_1ace__lite__initiator.html new file mode 100644 index 00000000..cea5abaa --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator.html @@ -0,0 +1,516 @@ + + + + + + + +scc: axi::pin::ace_lite_initiator< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_lite_initiator< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_lite_initiator< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_lite_initiator< CFG >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_lite_initiator)
 
+ ace_lite_initiator (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, TYPES >
+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, TYPES >
+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_axi< CFG, TYPES >
+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_target_socket< CFG::BUSWIDTH > tsckt {"tsckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
- Public Attributes inherited from axi::rresp_axi< CFG, TYPES >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_lite_initiator< CFG >

+ + +

Definition at line 34 of file ace_lite_initiator.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator.js b/develop/structaxi_1_1pin_1_1ace__lite__initiator.js new file mode 100644 index 00000000..8ec7e455 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__lite__initiator = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__lite__initiator.html#aaab85a1a64a60b759d2da2796f3e5e2a", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__lite__initiator.html#aff5dcb4ab83c887df553fac56a98f661", null ], + [ "ace_lite_initiator", "structaxi_1_1pin_1_1ace__lite__initiator.html#af18b263b5032f4ec3c3447e25b637aec", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__lite__initiator.html#a7c2961050fea91c88fb82be819816823", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__lite__initiator.html#aba822315e15d051f6cd17bd085f00607", null ], + [ "tsckt", "structaxi_1_1pin_1_1ace__lite__initiator.html#a78f346ce1a33dcb8672ea86509439c0e", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map new file mode 100644 index 00000000..9601dcf8 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 new file mode 100644 index 00000000..2a203dd1 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 @@ -0,0 +1 @@ +d33842d48b78faf1478fb36df31911cb \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png new file mode 100644 index 00000000..251a66e3 Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map new file mode 100644 index 00000000..d93a4bdd --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 new file mode 100644 index 00000000..19cb918e --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 @@ -0,0 +1 @@ +617f6d29ac38c3de93dd365521139a12 \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png new file mode 100644 index 00000000..70dce472 Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target-members.html b/develop/structaxi_1_1pin_1_1ace__lite__target-members.html new file mode 100644 index 00000000..f76516c7 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target-members.html @@ -0,0 +1,197 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pin::ace_lite_target< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_lite_target< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_lite_target(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
clk_i (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
isckt (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
phase_type typedef (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
SC_HAS_PROCESS(ace_lite_target) (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target.html b/develop/structaxi_1_1pin_1_1ace__lite__target.html new file mode 100644 index 00000000..6912c90c --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target.html @@ -0,0 +1,517 @@ + + + + + + + +scc: axi::pin::ace_lite_target< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Classes | +Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_lite_target< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_lite_target< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_lite_target< CFG >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_lite_target)
 
+ ace_lite_target (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, TYPES >
+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, TYPES >
+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_axi< CFG, TYPES >
+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< CFG::BUSWIDTH > isckt {"isckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
- Public Attributes inherited from axi::rresp_axi< CFG, TYPES >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_lite_target< CFG >

+ + +

Definition at line 36 of file ace_lite_target.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target.js b/develop/structaxi_1_1pin_1_1ace__lite__target.js new file mode 100644 index 00000000..e36f5647 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__lite__target = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__lite__target.html#a95b24a90fe94ddc1fe927e622d05812f", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__lite__target.html#ae93064bf1f5e2106957ccd8606f288e2", null ], + [ "ace_lite_target", "structaxi_1_1pin_1_1ace__lite__target.html#a033c18767e51960adf370b598cc3180a", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__lite__target.html#a3b320c9f5846a6130b60a2c4b9206637", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__lite__target.html#a06648b39eae4552c22c492dd05e8d53a", null ], + [ "isckt", "structaxi_1_1pin_1_1ace__lite__target.html#abd1d5a863fa5be71a76a8382f61ae79b", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map new file mode 100644 index 00000000..7faae0fd --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 new file mode 100644 index 00000000..976d3c69 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 @@ -0,0 +1 @@ +396ba8dc1574b4a6bf83b9dfdbf46c37 \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png new file mode 100644 index 00000000..52d356c3 Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map new file mode 100644 index 00000000..147f147a --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 new file mode 100644 index 00000000..1596aa72 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 @@ -0,0 +1 @@ +74b1daca2e917f2d5b52ccba578f1410 \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png new file mode 100644 index 00000000..a892fc81 Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__target-members.html b/develop/structaxi_1_1pin_1_1ace__target-members.html new file mode 100644 index 00000000..0a62e4a6 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target-members.html @@ -0,0 +1,221 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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axi::pin::ace_target< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_target< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ac_ace()=default (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >inline
ac_addr (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_prot (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_ready (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_snoop (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_trace (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_valid (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_vmidext (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ace_target(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >inline
ar_addr (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_bar (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_burst (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_cache (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_domain (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_id (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_len (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_lock (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_prot (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_qos (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_ready (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_region (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_size (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_snoop (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_trace (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_user (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_valid (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_vmidext (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
aw_ace()=default (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >inline
aw_addr (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_atop (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_bar (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_burst (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_cache (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_domain (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_id (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_len (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_lock (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_prot (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_qos (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_ready (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_region (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_size (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_snoop (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashlpid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashlpiden (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashnid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashniden (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_trace (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_unique (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_user (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_valid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
ace_bw_transport_if< axi::axi_protocol_types >::b_snoop(TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0axi::bw_blocking_transport_if< TYPES::tlm_payload_type >pure virtual
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >inline
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >inline
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >inline
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
cd_ace()=default (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >inline
cd_data (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_last (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_ready (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_valid (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
clk_i (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
cr_ace()=default (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >inline
cr_ready (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_resp (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_trace (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_valid (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
isckt (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
phase_type typedef (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_ack (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_data (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_id (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_last (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_ready (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_resp (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_trace (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_user (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_valid (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_ace()=default (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
SC_HAS_PROCESS(ace_target) (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
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SystemC components library
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axi::pin::ace_target< CFG > Struct Template Reference
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+Inheritance diagram for axi::pin::ace_target< CFG >:
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Inheritance graph
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Collaboration graph
+ + + + + + + + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_target)
 
+ ace_target (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, CFG::slave_types >
+ aw_ace (const char *prefix)
 
+void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, CFG::slave_types >
+ ar_ace (const char *prefix)
 
+void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_ace< CFG, CFG::slave_types >
+ rresp_ace (const char *prefix)
 
+void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ac_ace< CFG, CFG::slave_types >
+ ac_ace (const char *prefix)
 
+void bind_ac (ac_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cr_ace< CFG, CFG::slave_types >
+ cr_ace (const char *prefix)
 
+void bind_cr (cr_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cd_ace< CFG, CFG::slave_types >
+ cd_ace (const char *prefix)
 
+void bind_cd (cd_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::bw_blocking_transport_if< TYPES::tlm_payload_type >
virtual void b_snoop (TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0
 snoop access to a snooped master More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::ace_initiator_socket< CFG::BUSWIDTH > isckt {"isckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, CFG::slave_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr
 
+TYPES::template s2m_t< bool > aw_ready
 
+TYPES::template m2s_t< bool > aw_lock
 
+TYPES::template m2s_t< bool > aw_valid
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar
 
+TYPES::template m2s_t< bool > aw_unique
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user
 
+TYPES::template m2s_t< bool > aw_stashniden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid
 
+TYPES::template m2s_t< bool > aw_stashlpiden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop
 
+TYPES::template m2s_opt_t< bool > aw_trace
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, CFG::slave_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst
 
+TYPES::template m2s_t< bool > ar_lock
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region
 
+TYPES::template m2s_t< bool > ar_valid
 
+TYPES::template s2m_t< bool > ar_ready
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user
 
+TYPES::template m2s_opt_t< bool > ar_trace
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext
 
- Public Attributes inherited from axi::rresp_ace< CFG, CFG::slave_types >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id
 
+TYPES::template s2m_t< typename CFG::data_t > r_data
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp
 
+TYPES::template s2m_full_t< bool > r_last
 
+TYPES::template s2m_t< bool > r_valid
 
+TYPES::template m2s_t< bool > r_ready
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user
 
+TYPES::template s2m_opt_t< bool > r_trace
 
+TYPES::template m2s_t< bool > r_ack
 
- Public Attributes inherited from axi::ac_ace< CFG, CFG::slave_types >
+TYPES::template s2m_t< bool > ac_valid
 
+TYPES::template m2s_t< bool > ac_ready
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext
 
+TYPES::template s2m_opt_t< bool > ac_trace
 
- Public Attributes inherited from axi::cr_ace< CFG, CFG::slave_types >
+TYPES::template m2s_t< bool > cr_valid
 
+TYPES::template s2m_t< bool > cr_ready
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp
 
+TYPES::template m2s_opt_t< bool > cr_trace
 
- Public Attributes inherited from axi::cd_ace< CFG, CFG::slave_types >
+TYPES::template m2s_t< bool > cd_valid
 
+TYPES::template s2m_t< bool > cd_ready
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data
 
+TYPES::template m2s_full_t< bool > cd_last
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Member Functions inherited from axi::bw_blocking_transport_if< TYPES::tlm_payload_type >
virtual void b_snoop (TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0
 snoop access to a snooped master More...
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_target< CFG >

+ + +

Definition at line 36 of file ace_target.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1pin_1_1ace__target.js b/develop/structaxi_1_1pin_1_1ace__target.js new file mode 100644 index 00000000..0c69019a --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__target = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__target.html#a350e9f1d941cd3062057143da4b6472d", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__target.html#a264ce57e79ffa0392ca9c1968f5ea3f7", null ], + [ "ace_target", "structaxi_1_1pin_1_1ace__target.html#afb6bd99ea0dfd407a18e08454810b6ba", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__target.html#a6c0b1d5568f229baa7009664798d4f9f", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__target.html#a6cf5d5a6e9c6c89118368dd4a6df05d7", null ], + [ "isckt", "structaxi_1_1pin_1_1ace__target.html#ac049d53eff4b9e7ceb470dc2ac4dfed0", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__target__coll__graph.map b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.map new file mode 100644 index 00000000..f99ad1ee --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.map @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__target__coll__graph.md5 b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.md5 new file mode 100644 index 00000000..3c127b3e --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.md5 @@ -0,0 +1 @@ +7bd68a1dcc2ecf7c996f2cc92951cbdf \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__target__coll__graph.png b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.png new file mode 100644 index 00000000..c3c9086e Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__target__coll__graph.png differ diff --git a/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.map b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.map new file mode 100644 index 00000000..d06e46a3 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 new file mode 100644 index 00000000..5dc67943 --- /dev/null +++ b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 @@ -0,0 +1 @@ +c05e3e0c17af4a4459d73a4906af4d4a \ No newline at end of file diff --git a/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.png b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.png new file mode 100644 index 00000000..d01a0cfc Binary files /dev/null and b/develop/structaxi_1_1pin_1_1ace__target__inherit__graph.png differ diff --git a/develop/structaxi_1_1rresp__ace-members.html b/develop/structaxi_1_1rresp__ace-members.html new file mode 100644 index 00000000..b7247d91 --- /dev/null +++ b/develop/structaxi_1_1rresp__ace-members.html @@ -0,0 +1,93 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::rresp_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + +
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
r_ack (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_data (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_id (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_last (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_ready (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_resp (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_trace (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_user (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_valid (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
rresp_ace()=default (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1rresp__ace.html b/develop/structaxi_1_1rresp__ace.html new file mode 100644 index 00000000..5c36af96 --- /dev/null +++ b/develop/structaxi_1_1rresp__ace.html @@ -0,0 +1,136 @@ + + + + + + + +scc: axi::rresp_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::rresp_ace< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ rresp_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+TYPES::template m2s_t< bool > r_ack {"r_ack"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::rresp_ace< CFG, TYPES >

+ + +

Definition at line 344 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1rresp__ace.js b/develop/structaxi_1_1rresp__ace.js new file mode 100644 index 00000000..5ee47606 --- /dev/null +++ b/develop/structaxi_1_1rresp__ace.js @@ -0,0 +1,16 @@ +var structaxi_1_1rresp__ace = +[ + [ "rresp_ace", "structaxi_1_1rresp__ace.html#ae61af314ce8b56e8e7521dc50ee8c0f3", null ], + [ "rresp_ace", "structaxi_1_1rresp__ace.html#a7b3ce32fa6be63bd426e21792a3262d0", null ], + [ "bind_r", "structaxi_1_1rresp__ace.html#a7341dfdd1b7a9139d62ffc93812429ca", null ], + [ "bind_rresp", "structaxi_1_1rresp__ace.html#a092d706292173a77ad831339be10cee3", null ], + [ "r_ack", "structaxi_1_1rresp__ace.html#a2e0aa1b049f4417d89b47448f7221e32", null ], + [ "r_data", "structaxi_1_1rresp__ace.html#a610f4aa1017d01dab7895be7f4fcbcf5", null ], + [ "r_id", "structaxi_1_1rresp__ace.html#a863e27eabf2f61949eb39b0566094224", null ], + [ "r_last", "structaxi_1_1rresp__ace.html#af11a234e23c78f071a0e536f936f201d", null ], + [ "r_ready", "structaxi_1_1rresp__ace.html#ac7d06011cc2092dede8a6b521cfddc53", null ], + [ "r_resp", "structaxi_1_1rresp__ace.html#a1ef63f969b1c7ee839e28fdde1928105", null ], + [ "r_trace", "structaxi_1_1rresp__ace.html#afb2e3415f35c03eb0af557e620aaac52", null ], + [ "r_user", "structaxi_1_1rresp__ace.html#af60b25459380de7461e5ccd1130e6e4a", null ], + [ "r_valid", "structaxi_1_1rresp__ace.html#a57857e73e309fd8fd0b3f8605ad6bd5f", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1rresp__axi-members.html b/develop/structaxi_1_1rresp__axi-members.html new file mode 100644 index 00000000..25786f9a --- /dev/null +++ b/develop/structaxi_1_1rresp__axi-members.html @@ -0,0 +1,94 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
+
axi::rresp_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + +
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1rresp__axi.html b/develop/structaxi_1_1rresp__axi.html new file mode 100644 index 00000000..396eec9b --- /dev/null +++ b/develop/structaxi_1_1rresp__axi.html @@ -0,0 +1,151 @@ + + + + + + + +scc: axi::rresp_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::rresp_axi< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::rresp_axi< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + + + + + + + + + + +

+Public Member Functions

+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::rresp_axi< CFG, TYPES >

+ + +

Definition at line 308 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1rresp__axi.js b/develop/structaxi_1_1rresp__axi.js new file mode 100644 index 00000000..92f035ec --- /dev/null +++ b/develop/structaxi_1_1rresp__axi.js @@ -0,0 +1,17 @@ +var structaxi_1_1rresp__axi = +[ + [ "rresp_axi", "structaxi_1_1rresp__axi.html#aed5ce2c298bbde49b4ca1a03a355a798", null ], + [ "rresp_axi", "structaxi_1_1rresp__axi.html#abf07964f86dcd08fb1f0800f06196c54", null ], + [ "bind_r", "structaxi_1_1rresp__axi.html#a959db8736246a6f9efc3baacb593d243", null ], + [ "bind_r", "structaxi_1_1rresp__axi.html#ac70ba71a449cf31b9e3d3f94672dc933", null ], + [ "bind_rresp", "structaxi_1_1rresp__axi.html#aff10c6264f0c8569c22b2ed308e32721", null ], + [ "bind_rresp", "structaxi_1_1rresp__axi.html#a8ea3e2f8f34258bd554c2cadbad33123", null ], + [ "r_data", "structaxi_1_1rresp__axi.html#ae3ca7f71c5c5209bcddeb065ee033024", null ], + [ "r_id", "structaxi_1_1rresp__axi.html#ad610c9758dd6a9109b45be34ddd61168", null ], + [ "r_last", "structaxi_1_1rresp__axi.html#a9d8caa3e7ef61382fa7b5870f897a3ef", null ], + [ "r_ready", "structaxi_1_1rresp__axi.html#ad55fd4b1b0ca0f2ef9dfc6e33b9021e1", null ], + [ "r_resp", "structaxi_1_1rresp__axi.html#a7bfdec05e564eef8c1151a6db8ff7ae9", null ], + [ "r_trace", "structaxi_1_1rresp__axi.html#a91991c339f845e41c0c634815b422d34", null ], + [ "r_user", "structaxi_1_1rresp__axi.html#a291db1a699addf66aba410b1180303ec", null ], + [ "r_valid", "structaxi_1_1rresp__axi.html#a05a123376cb6b58a5351b4a23e130bda", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1rresp__axi__inherit__graph.map b/develop/structaxi_1_1rresp__axi__inherit__graph.map new file mode 100644 index 00000000..60326aca --- /dev/null +++ b/develop/structaxi_1_1rresp__axi__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/develop/structaxi_1_1rresp__axi__inherit__graph.md5 b/develop/structaxi_1_1rresp__axi__inherit__graph.md5 new file mode 100644 index 00000000..66a06fca --- /dev/null +++ b/develop/structaxi_1_1rresp__axi__inherit__graph.md5 @@ -0,0 +1 @@ +beb5d85e60787caf68b114d3ee68794b \ No newline at end of file diff --git a/develop/structaxi_1_1rresp__axi__inherit__graph.png b/develop/structaxi_1_1rresp__axi__inherit__graph.png new file mode 100644 index 00000000..50857b8a Binary files /dev/null and b/develop/structaxi_1_1rresp__axi__inherit__graph.png differ diff --git a/develop/structaxi_1_1rresp__axi__lite-members.html b/develop/structaxi_1_1rresp__axi__lite-members.html new file mode 100644 index 00000000..2b02e39c --- /dev/null +++ b/develop/structaxi_1_1rresp__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
+
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+
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+
+
+ +
+
+
+
axi::rresp_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >inline
r_data (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_ready (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_resp (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_valid (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
rresp_axi_lite()=default (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
rresp_axi_lite(const char *prefix) (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1rresp__axi__lite.html b/develop/structaxi_1_1rresp__axi__lite.html new file mode 100644 index 00000000..b1ab216f --- /dev/null +++ b/develop/structaxi_1_1rresp__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::rresp_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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+
axi::rresp_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

Read data channel signals. + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ rresp_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::rresp_axi_lite< CFG, TYPES >

+ +

Read data channel signals.

+ +

Definition at line 467 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1rresp__axi__lite.js b/develop/structaxi_1_1rresp__axi__lite.js new file mode 100644 index 00000000..feaab3cc --- /dev/null +++ b/develop/structaxi_1_1rresp__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1rresp__axi__lite = +[ + [ "rresp_axi_lite", "structaxi_1_1rresp__axi__lite.html#a10da839a4295aea9e73adf34ef0f91ec", null ], + [ "rresp_axi_lite", "structaxi_1_1rresp__axi__lite.html#a00922fcb47239b3d1037dba1b273b272", null ], + [ "bind_r", "structaxi_1_1rresp__axi__lite.html#a9f9cc0115d8c5e672cf95cb45ffc9e88", null ], + [ "r_data", "structaxi_1_1rresp__axi__lite.html#a58cc6b71cbfe007f76e8f3472d2bf9b5", null ], + [ "r_ready", "structaxi_1_1rresp__axi__lite.html#a74a2482dba10dbe33191ece8dd2c9172", null ], + [ "r_resp", "structaxi_1_1rresp__axi__lite.html#a5032ba8ce4f600aea4e3983e0c620b0a", null ], + [ "r_valid", "structaxi_1_1rresp__axi__lite.html#a260591195046ba88ca10c43a7055c7b0", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1wdata__axi-members.html b/develop/structaxi_1_1wdata__axi-members.html new file mode 100644 index 00000000..44aedc7b --- /dev/null +++ b/develop/structaxi_1_1wdata__axi-members.html @@ -0,0 +1,95 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
+
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+
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+ +
+
+
+
axi::wdata_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::wdata_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + +
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1wdata__axi.html b/develop/structaxi_1_1wdata__axi.html new file mode 100644 index 00000000..4b04fb5c --- /dev/null +++ b/develop/structaxi_1_1wdata__axi.html @@ -0,0 +1,156 @@ + + + + + + + +scc: axi::wdata_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::wdata_axi< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::wdata_axi< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + + + +
[legend]
+ + + + + + + + + + + + + + + + +

+Public Member Functions

+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::wdata_axi< CFG, TYPES >

+ + +

Definition at line 186 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1wdata__axi.js b/develop/structaxi_1_1wdata__axi.js new file mode 100644 index 00000000..2805b443 --- /dev/null +++ b/develop/structaxi_1_1wdata__axi.js @@ -0,0 +1,18 @@ +var structaxi_1_1wdata__axi = +[ + [ "wdata_axi", "structaxi_1_1wdata__axi.html#ab6fea06af6a69e51d234d4f09a6e443c", null ], + [ "wdata_axi", "structaxi_1_1wdata__axi.html#a085f7dba812e5ef8dd2ca18a7a4aef11", null ], + [ "bind_w", "structaxi_1_1wdata__axi.html#a227be2f584dc22c70f677145bfe827c4", null ], + [ "bind_w", "structaxi_1_1wdata__axi.html#a7f2bea298c2fc7f3148d56e62d96c23a", null ], + [ "bind_wdata", "structaxi_1_1wdata__axi.html#aba4fd3ab0eba131bbbe96cdf9f5cb57e", null ], + [ "bind_wdata", "structaxi_1_1wdata__axi.html#a1a6c6026d3c9ae1974217b120331d8c8", null ], + [ "w_ack", "structaxi_1_1wdata__axi.html#a385664fa77192e7eca1936c24f06cce3", null ], + [ "w_data", "structaxi_1_1wdata__axi.html#a6f18ff405009842fec2a44d9bf3e8017", null ], + [ "w_id", "structaxi_1_1wdata__axi.html#a6c6f08d7b3c8d6d5ceb32721dc80b7d8", null ], + [ "w_last", "structaxi_1_1wdata__axi.html#ae501c4578e95114a8420767c8f993639", null ], + [ "w_ready", "structaxi_1_1wdata__axi.html#af47c0f2c23b5be25cd02e1a42617293b", null ], + [ "w_strb", "structaxi_1_1wdata__axi.html#a676e556d99ed9beff14fd7ade22dc464", null ], + [ "w_trace", "structaxi_1_1wdata__axi.html#aee7a79a28b2b4451011e98bba23c74b1", null ], + [ "w_user", "structaxi_1_1wdata__axi.html#ae11626386d762fe4d6f269ce6834aa5f", null ], + [ "w_valid", "structaxi_1_1wdata__axi.html#a7ea49b79cd3b4a8800b8d1bafbdb1ef2", null ] +]; \ No newline at end of file diff --git a/develop/structaxi_1_1wdata__axi__inherit__graph.map b/develop/structaxi_1_1wdata__axi__inherit__graph.map new file mode 100644 index 00000000..fd5364e1 --- /dev/null +++ b/develop/structaxi_1_1wdata__axi__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/develop/structaxi_1_1wdata__axi__inherit__graph.md5 b/develop/structaxi_1_1wdata__axi__inherit__graph.md5 new file mode 100644 index 00000000..159ecf7c --- /dev/null +++ b/develop/structaxi_1_1wdata__axi__inherit__graph.md5 @@ -0,0 +1 @@ +8bc168fba4804279e1423fc2571fe96b \ No newline at end of file diff --git a/develop/structaxi_1_1wdata__axi__inherit__graph.png b/develop/structaxi_1_1wdata__axi__inherit__graph.png new file mode 100644 index 00000000..6aca046a Binary files /dev/null and b/develop/structaxi_1_1wdata__axi__inherit__graph.png differ diff --git a/develop/structaxi_1_1wdata__axi__lite-members.html b/develop/structaxi_1_1wdata__axi__lite-members.html new file mode 100644 index 00000000..0c96b432 --- /dev/null +++ b/develop/structaxi_1_1wdata__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::wdata_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::wdata_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >inline
w_data (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_ready (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_strb (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_valid (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
wdata_axi_lite()=default (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
wdata_axi_lite(const char *prefix) (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/develop/structaxi_1_1wdata__axi__lite.html b/develop/structaxi_1_1wdata__axi__lite.html new file mode 100644 index 00000000..c60df887 --- /dev/null +++ b/develop/structaxi_1_1wdata__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::wdata_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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axi::wdata_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

write data channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ wdata_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::wdata_axi_lite< CFG, TYPES >

+ +

write data channel signals

+ +

Definition at line 404 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structaxi_1_1wdata__axi__lite.js b/develop/structaxi_1_1wdata__axi__lite.js new file mode 100644 index 00000000..2a9f7486 --- /dev/null +++ b/develop/structaxi_1_1wdata__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1wdata__axi__lite = +[ + [ "wdata_axi_lite", "structaxi_1_1wdata__axi__lite.html#a3e9d650b47bd083f8eba24563aaabe42", null ], + [ "wdata_axi_lite", "structaxi_1_1wdata__axi__lite.html#a93b3a687cb6aac1f066af8873b7b3a4b", null ], + [ "bind_w", "structaxi_1_1wdata__axi__lite.html#adddf758c62f44aea560cf7d5ad179916", null ], + [ "w_data", "structaxi_1_1wdata__axi__lite.html#a65eed7c10fb70f58b1ef85dc64fd70fc", null ], + [ "w_ready", "structaxi_1_1wdata__axi__lite.html#a7dd039028cd627c1e162d70226b1369a", null ], + [ "w_strb", "structaxi_1_1wdata__axi__lite.html#a8fa80664451077881e4775f21eb3d900", null ], + [ "w_valid", "structaxi_1_1wdata__axi__lite.html#aa13809572afb4c947da11268ea5aa0b9", null ] +]; \ No newline at end of file diff --git a/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html b/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html new file mode 100644 index 00000000..59dd2ce7 --- /dev/null +++ b/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html @@ -0,0 +1,81 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
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+
+
chi::enable_for_enum< rsp_resperrtype_e > Member List
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This is the complete list of members for chi::enable_for_enum< rsp_resperrtype_e >, including all inherited members.

+ + +
enable (defined in chi::enable_for_enum< rsp_resperrtype_e >)chi::enable_for_enum< rsp_resperrtype_e >static
+
+ + + + diff --git a/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html b/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html new file mode 100644 index 00000000..994b9e8f --- /dev/null +++ b/develop/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html @@ -0,0 +1,94 @@ + + + + + + + +scc: chi::enable_for_enum< rsp_resperrtype_e > Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Static Public Attributes | +List of all members
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chi::enable_for_enum< rsp_resperrtype_e > Struct Reference
+
+
+ + + + +

+Static Public Attributes

+static const bool enable = true
 
+

Detailed Description

+
+

Definition at line 1087 of file chi_tlm.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__discrete__restriction-members.html b/develop/structscc_1_1__discrete__restriction-members.html new file mode 100644 index 00000000..2f58c957 --- /dev/null +++ b/develop/structscc_1_1__discrete__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
+
scc::_discrete_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_discrete_restriction< T >, including all inherited members.

+ + + + +
_discrete_restriction(COLLECTION_TYPE values) (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >inline
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >inline
values (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >
+
+ + + + diff --git a/develop/structscc_1_1__discrete__restriction.html b/develop/structscc_1_1__discrete__restriction.html new file mode 100644 index 00000000..dc26c3f5 --- /dev/null +++ b/develop/structscc_1_1__discrete__restriction.html @@ -0,0 +1,108 @@ + + + + + + + +scc: scc::_discrete_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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scc::_discrete_restriction< T > Struct Template Reference
+
+
+ + + + + + + +

+Public Member Functions

+template<typename COLLECTION_TYPE >
 _discrete_restriction (COLLECTION_TYPE values)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+std::unordered_set< T > const values
 
+

Detailed Description

+

template<typename T>
+struct scc::_discrete_restriction< T >

+ + +

Definition at line 75 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__discrete__restriction.js b/develop/structscc_1_1__discrete__restriction.js new file mode 100644 index 00000000..3349802a --- /dev/null +++ b/develop/structscc_1_1__discrete__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__discrete__restriction = +[ + [ "_discrete_restriction", "structscc_1_1__discrete__restriction.html#a5a25f5eafbd0de4b333d2ddb1459870c", null ], + [ "operator()", "structscc_1_1__discrete__restriction.html#abb01c560c44197b1a774f4c97eae9f15", null ], + [ "values", "structscc_1_1__discrete__restriction.html#ac09374f8554ab2097d1f381fa23be542", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__max__excl__restriction-members.html b/develop/structscc_1_1__max__excl__restriction-members.html new file mode 100644 index 00000000..50d4a6b0 --- /dev/null +++ b/develop/structscc_1_1__max__excl__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
SystemC components library
+
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+
+
scc::_max_excl_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_max_excl_restriction< T >, including all inherited members.

+ + + + +
_max_excl_restriction(T max) (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >inline
max (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__max__excl__restriction.html b/develop/structscc_1_1__max__excl__restriction.html new file mode 100644 index 00000000..a76c86fc --- /dev/null +++ b/develop/structscc_1_1__max__excl__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_max_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_max_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _max_excl_restriction (T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_max_excl_restriction< T >

+ + +

Definition at line 67 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__max__excl__restriction.js b/develop/structscc_1_1__max__excl__restriction.js new file mode 100644 index 00000000..9c9c217a --- /dev/null +++ b/develop/structscc_1_1__max__excl__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__max__excl__restriction = +[ + [ "_max_excl_restriction", "structscc_1_1__max__excl__restriction.html#a4d0ecc4b22a2f6cdc18b5bd01891fe5e", null ], + [ "operator()", "structscc_1_1__max__excl__restriction.html#a64366d04c3700ad0db579d069fa2bad6", null ], + [ "max", "structscc_1_1__max__excl__restriction.html#a9d6ac59482e2350361cc983e24692fc7", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__max__restriction-members.html b/develop/structscc_1_1__max__restriction-members.html new file mode 100644 index 00000000..cbacc95e --- /dev/null +++ b/develop/structscc_1_1__max__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
scc::_max_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_max_restriction< T >, including all inherited members.

+ + + + +
_max_restriction(T max) (defined in scc::_max_restriction< T >)scc::_max_restriction< T >inline
max (defined in scc::_max_restriction< T >)scc::_max_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_max_restriction< T >)scc::_max_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__max__restriction.html b/develop/structscc_1_1__max__restriction.html new file mode 100644 index 00000000..779fe408 --- /dev/null +++ b/develop/structscc_1_1__max__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_max_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_max_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _max_restriction (T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_max_restriction< T >

+ + +

Definition at line 59 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__max__restriction.js b/develop/structscc_1_1__max__restriction.js new file mode 100644 index 00000000..d0434c97 --- /dev/null +++ b/develop/structscc_1_1__max__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__max__restriction = +[ + [ "_max_restriction", "structscc_1_1__max__restriction.html#a9c23b9701eb894a8bc6dcc9e485fef21", null ], + [ "operator()", "structscc_1_1__max__restriction.html#a0d0c527133192d5818ae6e2a64c8d5e4", null ], + [ "max", "structscc_1_1__max__restriction.html#a02c3e3e505b01e01aa4597e293263242", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__min__excl__restriction-members.html b/develop/structscc_1_1__min__excl__restriction-members.html new file mode 100644 index 00000000..1967fd8a --- /dev/null +++ b/develop/structscc_1_1__min__excl__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
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+
scc::_min_excl_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_excl_restriction< T >, including all inherited members.

+ + + + +
_min_excl_restriction(T min) (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >inline
min (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__min__excl__restriction.html b/develop/structscc_1_1__min__excl__restriction.html new file mode 100644 index 00000000..8cd66e3e --- /dev/null +++ b/develop/structscc_1_1__min__excl__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_min_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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scc::_min_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_excl_restriction (T min)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const min
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_excl_restriction< T >

+ + +

Definition at line 51 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__min__excl__restriction.js b/develop/structscc_1_1__min__excl__restriction.js new file mode 100644 index 00000000..2e11aa9c --- /dev/null +++ b/develop/structscc_1_1__min__excl__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__min__excl__restriction = +[ + [ "_min_excl_restriction", "structscc_1_1__min__excl__restriction.html#a01ab6129292a9784ee8f94518b96fd71", null ], + [ "operator()", "structscc_1_1__min__excl__restriction.html#a971103e984f937c810bff047f9cfde9f", null ], + [ "min", "structscc_1_1__min__excl__restriction.html#a78fbe1b131f778e8842939f8d10c0a99", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__min__max__excl__restriction-members.html b/develop/structscc_1_1__min__max__excl__restriction-members.html new file mode 100644 index 00000000..19cceec8 --- /dev/null +++ b/develop/structscc_1_1__min__max__excl__restriction-members.html @@ -0,0 +1,84 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::_min_max_excl_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_max_excl_restriction< T >, including all inherited members.

+ + + + + +
_min_max_excl_restriction(T min, T max) (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >inline
max (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >
min (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__min__max__excl__restriction.html b/develop/structscc_1_1__min__max__excl__restriction.html new file mode 100644 index 00000000..034a2ef0 --- /dev/null +++ b/develop/structscc_1_1__min__max__excl__restriction.html @@ -0,0 +1,110 @@ + + + + + + + +scc: scc::_min_max_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_min_max_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_max_excl_restriction (T min, T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + + + +

+Public Attributes

+T const min
 
+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_max_excl_restriction< T >

+ + +

Definition at line 33 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__min__max__excl__restriction.js b/develop/structscc_1_1__min__max__excl__restriction.js new file mode 100644 index 00000000..5e1a61c0 --- /dev/null +++ b/develop/structscc_1_1__min__max__excl__restriction.js @@ -0,0 +1,7 @@ +var structscc_1_1__min__max__excl__restriction = +[ + [ "_min_max_excl_restriction", "structscc_1_1__min__max__excl__restriction.html#a8d8626c7fa578acac5ab91d0b0e956b4", null ], + [ "operator()", "structscc_1_1__min__max__excl__restriction.html#a68b53f3da65b99c473259018d935fd2f", null ], + [ "max", "structscc_1_1__min__max__excl__restriction.html#a52b619df3ab17d0f8aa8b4eacddbfd3d", null ], + [ "min", "structscc_1_1__min__max__excl__restriction.html#a5ee759edf3653def287d307acbf045e4", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__min__max__restriction-members.html b/develop/structscc_1_1__min__max__restriction-members.html new file mode 100644 index 00000000..7c5c2ebb --- /dev/null +++ b/develop/structscc_1_1__min__max__restriction-members.html @@ -0,0 +1,84 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
+ +
+
+
+
scc::_min_max_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_max_restriction< T >, including all inherited members.

+ + + + + +
_min_max_restriction(T min, T max) (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >inline
max (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >
min (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__min__max__restriction.html b/develop/structscc_1_1__min__max__restriction.html new file mode 100644 index 00000000..74087bb4 --- /dev/null +++ b/develop/structscc_1_1__min__max__restriction.html @@ -0,0 +1,110 @@ + + + + + + + +scc: scc::_min_max_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_min_max_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_max_restriction (T min, T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + + + +

+Public Attributes

+T const min
 
+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_max_restriction< T >

+ + +

Definition at line 23 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__min__max__restriction.js b/develop/structscc_1_1__min__max__restriction.js new file mode 100644 index 00000000..40afacd5 --- /dev/null +++ b/develop/structscc_1_1__min__max__restriction.js @@ -0,0 +1,7 @@ +var structscc_1_1__min__max__restriction = +[ + [ "_min_max_restriction", "structscc_1_1__min__max__restriction.html#aff665e4a73dbce31a258e6b7e08ae459", null ], + [ "operator()", "structscc_1_1__min__max__restriction.html#a9a0d4d7606b62fa1e122d6e933dc663d", null ], + [ "max", "structscc_1_1__min__max__restriction.html#a965362acfd28304d0ddf19c4b4524623", null ], + [ "min", "structscc_1_1__min__max__restriction.html#aff4250c15f1523b5bda33ad9e843f7f0", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1__min__restriction-members.html b/develop/structscc_1_1__min__restriction-members.html new file mode 100644 index 00000000..e27984e1 --- /dev/null +++ b/develop/structscc_1_1__min__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::_min_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_restriction< T >, including all inherited members.

+ + + + +
_min_restriction(T min) (defined in scc::_min_restriction< T >)scc::_min_restriction< T >inline
min (defined in scc::_min_restriction< T >)scc::_min_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_restriction< T >)scc::_min_restriction< T >inline
+
+ + + + diff --git a/develop/structscc_1_1__min__restriction.html b/develop/structscc_1_1__min__restriction.html new file mode 100644 index 00000000..38e28b87 --- /dev/null +++ b/develop/structscc_1_1__min__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_min_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_min_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_restriction (T min)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const min
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_restriction< T >

+ + +

Definition at line 43 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1__min__restriction.js b/develop/structscc_1_1__min__restriction.js new file mode 100644 index 00000000..66667a98 --- /dev/null +++ b/develop/structscc_1_1__min__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__min__restriction = +[ + [ "_min_restriction", "structscc_1_1__min__restriction.html#a538771b6826f30d7ed178c00b7bdace4", null ], + [ "operator()", "structscc_1_1__min__restriction.html#a6d60e43565bd944f05210c49d09b7ec1", null ], + [ "min", "structscc_1_1__min__restriction.html#aedd6ccc772278d2ba6b25d851bd6298c", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1cci__param__restricted-members.html b/develop/structscc_1_1cci__param__restricted-members.html new file mode 100644 index 00000000..2d368b1f --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted-members.html @@ -0,0 +1,82 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::cci_param_restricted< T, TM > Member List
+
+
+ +

This is the complete list of members for scc::cci_param_restricted< T, TM >, including all inherited members.

+ + + +
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())scc::cci_param_restricted< T, TM >inline
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())scc::cci_param_restricted< T, TM >inline
+
+ + + + diff --git a/develop/structscc_1_1cci__param__restricted.html b/develop/structscc_1_1cci__param__restricted.html new file mode 100644 index 00000000..ddd57556 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted.html @@ -0,0 +1,295 @@ + + + + + + + +scc: scc::cci_param_restricted< T, TM > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+List of all members
+
+
scc::cci_param_restricted< T, TM > Struct Template Reference
+
+
+ +

extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter. + More...

+ +

#include <cci_param_restricted.h>

+
+Inheritance diagram for scc::cci_param_restricted< T, TM >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::cci_param_restricted< T, TM >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + +

+Public Member Functions

Constructors
template<typename RESTR >
 cci_param_restricted (const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
 
template<typename RESTR >
 cci_param_restricted (const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
 
+

Detailed Description

+

template<typename T, cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+struct scc::cci_param_restricted< T, TM >

+ +

extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter.

+
Template Parameters
+ + + +
Ttype of the parameter value
TMspecifies the parameter type lock behavior
+
+
+ +

Definition at line 180 of file cci_param_restricted.h.

+

Constructor & Destructor Documentation

+ +

◆ cci_param_restricted() [1/2]

+ +
+
+
+template<typename T , cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+
+template<typename RESTR >
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
scc::cci_param_restricted< T, TM >::cci_param_restricted (const std::string & name,
const T & default_value,
RESTR const & restr,
const std::string & desc = "",
cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
const cci::cci_originator & originator = cci::cci_originator() 
)
+ 		+inline
+
+

Constructor with (local/hierarchical) name, default value, restriction, description and originator.

+
Parameters
+ + + + + + + +
nameName of the parameter
default_valueDefault value of the parameter (Typed value)
restrRestriction to apply, will be checked befor every write
descDescription of the parameter
name_typeEither the name should be absolute or relative
originatorOriginator of the parameter
+
+
+ +

Definition at line 196 of file cci_param_restricted.h.

+ +
+
+ +

◆ cci_param_restricted() [2/2]

+ +
+
+
+template<typename T , cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+
+template<typename RESTR >
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
scc::cci_param_restricted< T, TM >::cci_param_restricted (const std::string & name,
const T & default_value,
RESTR const & restr,
cci::cci_broker_handle private_broker,
const std::string & desc = "",
cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
const cci::cci_originator & originator = cci::cci_originator() 
)
+ 		+inline
+
+

Constructor with (local/hierarchical) name, default value, restriction, private broker, description, name type and originator.

+
Parameters
+ + + + + + + + +
nameName of the parameter
default_valueDefault value of the parameter (Typed value)
private_brokerAssociated private broker
restrRestriction to apply, will be checked befor every write
descDescription of the parameter
name_typeEither the name should be absolute or relative
originatorOriginator of the parameter
+
+
+ +

Definition at line 217 of file cci_param_restricted.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/develop/structscc_1_1cci__param__restricted.js b/develop/structscc_1_1cci__param__restricted.js new file mode 100644 index 00000000..a89b8bf3 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted.js @@ -0,0 +1,5 @@ +var structscc_1_1cci__param__restricted = +[ + [ "cci_param_restricted", "structscc_1_1cci__param__restricted.html#a6b7f0b6ac7677e10cc8ad1a0fd3e3629", null ], + [ "cci_param_restricted", "structscc_1_1cci__param__restricted.html#aeafefd5891fb058a13d6dd40f9325ac4", null ] +]; \ No newline at end of file diff --git a/develop/structscc_1_1cci__param__restricted__coll__graph.map b/develop/structscc_1_1cci__param__restricted__coll__graph.map new file mode 100644 index 00000000..ee591705 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/develop/structscc_1_1cci__param__restricted__coll__graph.md5 b/develop/structscc_1_1cci__param__restricted__coll__graph.md5 new file mode 100644 index 00000000..5d5c2843 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted__coll__graph.md5 @@ -0,0 +1 @@ +53f739e8bfb0226fcc469a28a6e12a56 \ No newline at end of file diff --git a/develop/structscc_1_1cci__param__restricted__coll__graph.png b/develop/structscc_1_1cci__param__restricted__coll__graph.png new file mode 100644 index 00000000..2f9b41f7 Binary files /dev/null and b/develop/structscc_1_1cci__param__restricted__coll__graph.png differ diff --git a/develop/structscc_1_1cci__param__restricted__inherit__graph.map b/develop/structscc_1_1cci__param__restricted__inherit__graph.map new file mode 100644 index 00000000..ee591705 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted__inherit__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/develop/structscc_1_1cci__param__restricted__inherit__graph.md5 b/develop/structscc_1_1cci__param__restricted__inherit__graph.md5 new file mode 100644 index 00000000..5d5c2843 --- /dev/null +++ b/develop/structscc_1_1cci__param__restricted__inherit__graph.md5 @@ -0,0 +1 @@ +53f739e8bfb0226fcc469a28a6e12a56 \ No newline at end of file diff --git a/develop/structscc_1_1cci__param__restricted__inherit__graph.png b/develop/structscc_1_1cci__param__restricted__inherit__graph.png new file mode 100644 index 00000000..2f9b41f7 Binary files /dev/null and b/develop/structscc_1_1cci__param__restricted__inherit__graph.png differ diff --git a/develop/target__info__if_8h_source.html b/develop/target__info__if_8h_source.html new file mode 100644 index 00000000..e6fc92bf --- /dev/null +++ b/develop/target__info__if_8h_source.html @@ -0,0 +1,104 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/target_info_if.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
target_info_if.h
+
+
+
1 /*
+
2  * target_info_if.h
+
3  *
+
4  * Created on: Aug 23, 2023
+
5  * Author: eyckj
+
6  */
+
7 
+
8 #ifndef _AXI_PE_TARGET_INFO_IF_H_
+
9 #define _AXI_PE_TARGET_INFO_IF_H_
+
10 
+
11 namespace axi {
+
12 namespace pe {
+
13 
+
14 class target_info_if {
+
15 public:
+
16  virtual ~target_info_if() = default;
+
17 
+
18  virtual size_t get_outstanding_tx_count() = 0;
+
19 };
+
20 
+
21 } /* namespace pe */
+
22 } /* namespace axi */
+
23 
+
24 #endif /* _AXI_PE_TARGET_INFO_IF_H_ */
+
axi::pe::target_info_if
Definition: target_info_if.h:14
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
+
+ + + + diff --git a/main/ace__initiator_8h_source.html b/main/ace__initiator_8h_source.html new file mode 100644 index 00000000..8235e4cd --- /dev/null +++ b/main/ace__initiator_8h_source.html @@ -0,0 +1,832 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_initiator.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_initiator.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_INITIATOR_H_
+
18 #define _BUS_AXI_PIN_ACE_INITIATOR_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <tlm_utils/peq_with_cb_and_phase.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_initiator : public sc_core::sc_module,
+
37  public aw_ace<CFG, typename CFG::master_types>,
+
38  public wdata_ace<CFG, typename CFG::master_types>,
+
39  public b_ace<CFG, typename CFG::master_types>,
+
40  public ar_ace<CFG, typename CFG::master_types>,
+
41  public rresp_ace<CFG, typename CFG::master_types>,
+
42 
+
43  public ac_ace<CFG, typename CFG::master_types>,
+
44  public cr_ace<CFG, typename CFG::master_types>,
+
45  public cd_ace<CFG, typename CFG::master_types>,
+
46 
+
47  protected axi::fsm::base,
+
48  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
49  SC_HAS_PROCESS(ace_initiator);
+
50 
+
51  enum { CACHELINE_SZ = 64 };
+
52 
+
53  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
54  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
55 
+
56  sc_core::sc_in<bool> clk_i{"clk_i"};
+
57 
+
58  axi::ace_target_socket<CFG::BUSWIDTH> tsckt{"tsckt"};
+
59 
+
60  ace_initiator(sc_core::sc_module_name const& nm)
+
61  : sc_core::sc_module(nm)
+
62  // coherent= true
+
63  , base(CFG::BUSWIDTH, true) {
+
64  instance_name = name();
+
65  tsckt(*this);
+
66  SC_METHOD(clk_delay);
+
67  sensitive << clk_i.pos();
+
68  SC_THREAD(ar_t);
+
69  SC_THREAD(r_t);
+
70  SC_THREAD(aw_t);
+
71  SC_THREAD(wdata_t);
+
72  SC_THREAD(b_t);
+
73  SC_THREAD(ac_t);
+
74  SC_THREAD(cr_resp_t);
+
75  SC_THREAD(cd_t);
+
76  SC_THREAD(rack_t);
+
77  SC_THREAD(wack_t);
+
78  }
+
79 
+
80 private:
+
81  void b_transport(payload_type& trans, sc_core::sc_time& t) override {
+
82  trans.set_dmi_allowed(false);
+
83  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
84  }
+
85 
+
86  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
87  assert(trans.get_extension<axi::ace_extension>() && "missing ACE extension");
+
88  sc_core::sc_time delay; // FIXME: calculate delay correctly
+
89  fw_peq.notify(trans, phase, delay);
+
90  return tlm::TLM_ACCEPTED;
+
91  }
+
92 
+
93  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override {
+
94  trans.set_dmi_allowed(false);
+
95  return false;
+
96  }
+
97 
+
98  unsigned int transport_dbg(payload_type& trans) override { return 0; }
+
99 
+
100  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
101 
+
102  fsm_handle* create_fsm_handle() { return new fsm_handle(); }
+
103 
+
104  void setup_callbacks(fsm_handle* fsm_hndl);
+
105 
+
106  void clk_delay() { clk_delayed.notify(axi::CLK_DELAY); }
+
107 
+
108  void ar_t();
+
109  void r_t();
+
110  void aw_t();
+
111  void wdata_t();
+
112  void b_t();
+
118  void ac_t();
+
119  void cr_resp_t();
+
120  void cd_t();
+
121 
+
122  void rack_t();
+
123  void wack_t();
+
131  static typename CFG::data_t get_cache_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
132  unsigned int SNOOP = 3; // TBD??
+
133  scc::peq<std::tuple<uint8_t, fsm_handle*>> cd_vl;
+
134  scc::peq<std::tuple<uint8_t, fsm_handle*>> cr_resp_vl;
+
135  std::array<unsigned, 3> outstanding_cnt{0, 0, 0};
+
136  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
137  std::array<fsm_handle*, 3> active_resp{nullptr, nullptr, nullptr};
+
138  std::array<fsm_handle*, 4> active_resp_beat{nullptr, nullptr, nullptr};
+
139  sc_core::sc_clock* clk_if{nullptr};
+
140  sc_core::sc_event clk_delayed, clk_self, r_end_resp_evt, w_end_resp_evt, aw_evt, ar_evt, ac_end_req_evt;
+
141  void nb_fw(payload_type& trans, const phase_type& phase) {
+
142  auto t = sc_core::SC_ZERO_TIME;
+
143  base::nb_fw(trans, phase, t);
+
144  }
+
145  tlm_utils::peq_with_cb_and_phase<ace_initiator> fw_peq{this, &ace_initiator::nb_fw};
+
146  std::unordered_map<unsigned, std::deque<fsm_handle*>> rd_resp_by_id, wr_resp_by_id;
+
147  sc_core::sc_buffer<uint8_t> wdata_vl;
+
148  sc_core::sc_event rack_vl;
+
149  sc_core::sc_event wack_vl;
+
150  void write_ar(tlm::tlm_generic_payload& trans);
+
151  void write_aw(tlm::tlm_generic_payload& trans);
+
152  void write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last = false);
+
153 };
+
154 
+
155 } // namespace pin
+
156 } // namespace axi
+
157 
+
158 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_ar(tlm::tlm_generic_payload& trans) {
+
159  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
160  this->ar_addr.write(addr);
+
161  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
162  this->ar_prot.write(ext->get_prot());
+
163  if(!CFG::IS_LITE) {
+
164  this->ar_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
165  this->ar_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
166  this->ar_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
167  this->ar_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
168  if(ext->is_exclusive())
+
169  this->ar_lock->write(true);
+
170  this->ar_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
171  this->ar_prot.write(ext->get_prot());
+
172  this->ar_qos->write(ext->get_qos());
+
173  this->ar_region->write(ext->get_region());
+
174  this->ar_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
175  this->ar_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
176  this->ar_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
177  this->ar_user->write(ext->get_user(axi::common::id_type::CTRL));
+
178  }
+
179  }
+
180 }
+
181 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_aw(tlm::tlm_generic_payload& trans) {
+
182  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
183  this->aw_addr.write(addr);
+
184  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
185  this->aw_prot.write(ext->get_prot());
+
186  if(ext->is_exclusive())
+
187  this->aw_lock->write(true);
+
188  if(this->aw_id.get_interface())
+
189  this->aw_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
190  this->aw_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
191  this->aw_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
192  this->aw_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
193  this->aw_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
194  this->aw_qos->write(sc_dt::sc_uint<4>(ext->get_qos()));
+
195  this->aw_region->write(sc_dt::sc_uint<4>(ext->get_region()));
+
196  this->aw_user->write(ext->get_user(axi::common::id_type::CTRL));
+
197  this->aw_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
198  this->aw_snoop->write(sc_dt::sc_uint<CFG::AWSNOOPWIDTH>((uint8_t)ext->get_snoop()));
+
199  this->aw_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
200  this->aw_unique->write(ext->get_unique());
+
201  }
+
202 }
+
203 
+
204 // FIXME: strb not yet correct
+
205 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last) {
+
206  typename CFG::data_t data{0};
+
207  sc_dt::sc_uint<CFG::BUSWIDTH / 8> strb{0};
+
208  auto ext = trans.get_extension<axi::ace_extension>();
+
209  auto size = 1u << ext->get_size();
+
210  auto byte_offset = beat * size;
+
211  auto offset = (trans.get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
212  auto beptr = trans.get_byte_enable_length() ? trans.get_byte_enable_ptr() + byte_offset : nullptr;
+
213  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
214  if(beat == 0) {
+
215  auto dptr = trans.get_data_ptr();
+
216  if(dptr)
+
217  for(size_t i = offset; i < size; ++i, ++dptr) {
+
218  auto bit_offs = i * 8;
+
219  data(bit_offs + 7, bit_offs) = *dptr;
+
220  if(beptr) {
+
221  strb[i] = *beptr == 0xff;
+
222  ++beptr;
+
223  } else
+
224  strb[i] = true;
+
225  }
+
226  } else {
+
227  auto beat_start_idx = byte_offset - offset;
+
228  auto data_len = trans.get_data_length();
+
229  auto dptr = trans.get_data_ptr() + beat_start_idx;
+
230  if(dptr)
+
231  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
232  auto bit_offs = i * 8;
+
233  data(bit_offs + 7, bit_offs) = *dptr;
+
234  if(beptr) {
+
235  strb[i] = *beptr == 0xff;
+
236  ++beptr;
+
237  } else
+
238  strb[i] = true;
+
239  }
+
240  }
+
241  } else { // aligned or single beat access
+
242  auto dptr = trans.get_data_ptr() + byte_offset;
+
243  if(dptr)
+
244  for(size_t i = 0; i < size; ++i, ++dptr) {
+
245  auto bit_offs = (offset + i) * 8;
+
246  data(bit_offs + 7, bit_offs) = *dptr;
+
247  if(beptr) {
+
248  strb[offset + i] = *beptr == 0xff;
+
249  ++beptr;
+
250  } else
+
251  strb[offset + i] = true;
+
252  }
+
253  }
+
254  this->w_data.write(data);
+
255  this->w_strb.write(strb);
+
256  if(!CFG::IS_LITE) {
+
257  this->w_id->write(ext->get_id());
+
258  if(this->w_user.get_interface())
+
259  this->w_user->write(ext->get_user(axi::common::id_type::DATA));
+
260  }
+
261 }
+
262 
+
263 template <typename CFG> typename CFG::data_t axi::pin::ace_initiator<CFG>::get_cache_data_for_beat(fsm_handle* fsm_hndl) {
+
264  auto beat_count = fsm_hndl->beat_count;
+
265  // SCCTRACE(SCMOD) << " " ;
+
266  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
267  auto byte_offset = beat_count * size;
+
268  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
269  typename CFG::data_t data{0};
+
270  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
271  if(beat_count == 0) {
+
272  auto dptr = fsm_hndl->trans->get_data_ptr();
+
273  for(size_t i = offset; i < size; ++i, ++dptr) {
+
274  auto bit_offs = i * 8;
+
275  data(bit_offs + 7, bit_offs) = *dptr;
+
276  }
+
277  } else {
+
278  auto beat_start_idx = byte_offset - offset;
+
279  auto data_len = fsm_hndl->trans->get_data_length();
+
280  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
281  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
282  auto bit_offs = i * 8;
+
283  data(bit_offs + 7, bit_offs) = *dptr;
+
284  }
+
285  }
+
286  } else { // aligned or single beat access
+
287  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
288  for(size_t i = 0; i < size; ++i, ++dptr) {
+
289  auto bit_offs = (offset + i) * 8;
+
290  data(bit_offs + 7, bit_offs) = *dptr;
+
291  }
+
292  }
+
293  return data;
+
294 }
+
295 
+
296 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
297  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
298  if(fsm_hndl->is_snoop) {
+
299  SCCTRACE(SCMOD) << " for snoop in RequestPhaseBeg ";
+
300  } else {
+
301  fsm_hndl->beat_count = 0;
+
302  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
303  if(CFG::IS_LITE) {
+
304  auto offset = fsm_hndl->trans->get_address() % (CFG::BUSWIDTH / 8);
+
305  if(offset + fsm_hndl->trans->get_data_length() > CFG::BUSWIDTH / 8) {
+
306  SCCFATAL(SCMOD) << " transaction " << *fsm_hndl->trans << " is not AXI4Lite compliant";
+
307  }
+
308  }
+
309  }
+
310  };
+
311  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
312  sc_assert(fsm_hndl->trans->is_write());
+
313  if(fsm_hndl->beat_count == 0) {
+
314  write_aw(*fsm_hndl->trans);
+
315  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
316  }
+
317  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count);
+
318  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
319  wdata_vl.write(0x1);
+
320  };
+
321  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
322  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
323  tlm::tlm_phase phase = axi::END_PARTIAL_REQ;
+
324  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
325  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
326  fsm_hndl->beat_count++;
+
327  };
+
328  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
329  if(fsm_hndl->is_snoop) {
+
330  SCCTRACE(SCMOD) << " BegReq of setup_cb";
+
331  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
332  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
333  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
334  } else {
+
335  switch(fsm_hndl->trans->get_command()) {
+
336  case tlm::TLM_READ_COMMAND:
+
337  active_req[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
338  write_ar(*fsm_hndl->trans);
+
339  ar_evt.notify(sc_core::SC_ZERO_TIME);
+
340  break;
+
341  case tlm::TLM_WRITE_COMMAND:
+
342  SCCTRACE(SCMOD) << "in BegReqE for trans " << *fsm_hndl->trans;
+
343  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
344  if(fsm_hndl->beat_count == 0) {
+
345  write_aw(*fsm_hndl->trans);
+
346  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
347  }
+
348  /* for Evict Trans, only addr on aw_t, response on b_t() */
+
349  auto ext = fsm_hndl->trans->get_extension<ace_extension>();
+
350  if(!axi::is_dataless(ext)) {
+
351  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count, true);
+
352  wdata_vl.write(0x3);
+
353  }
+
354  }
+
355  }
+
356  };
+
357  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
358  if(fsm_hndl->is_snoop) {
+
359  active_req[SNOOP] = nullptr;
+
360  ac_end_req_evt.notify(); // if snoop
+
361  } else {
+
362  switch(fsm_hndl->trans->get_command()) {
+
363  case tlm::TLM_READ_COMMAND:
+
364  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
365  active_req[tlm::TLM_READ_COMMAND] = nullptr;
+
366  break;
+
367  case tlm::TLM_WRITE_COMMAND:
+
368  SCCTRACE(SCMOD) << "in EndReq for trans " << *fsm_hndl->trans;
+
369  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
370  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
371  fsm_hndl->beat_count++;
+
372  }
+
373  tlm::tlm_phase phase = tlm::END_REQ;
+
374  sc_core::sc_time t = (sc_core::SC_ZERO_TIME); // (clk_if?clk_if->period()-ace::CLK_DELAY-1_ps:sc_core::SC_ZERO_TIME);
+
375  SCCTRACE(SCMOD) << " in EndReq before set_resp";
+
376  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
377  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
378  }
+
379  };
+
380  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
381  if(fsm_hndl->is_snoop) {
+
382  active_resp_beat[SNOOP] = fsm_hndl;
+
383  cd_vl.notify({1, fsm_hndl});
+
384 
+
385  } else {
+
386  // scheduling the response
+
387  assert(fsm_hndl->trans->is_read());
+
388  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
389  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
390  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
391  }
+
392  };
+
393  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
394  SCCTRACE(SCMOD) << "in EndPartRespE of setup_cb ";
+
395  if(fsm_hndl->is_snoop) {
+
396  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
397  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
398  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
399  // why here nullptr??
+
400  active_resp_beat[SNOOP] = nullptr;
+
401  fsm_hndl->beat_count++;
+
402  } else {
+
403  fsm_hndl->beat_count++;
+
404  r_end_resp_evt.notify();
+
405  }
+
406  };
+
407  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
408  SCCTRACE(SCMOD) << "in setup_cb, processing event BegRespE for trans " << *fsm_hndl->trans;
+
409  if(fsm_hndl->is_snoop) {
+
410  active_resp_beat[SNOOP] = fsm_hndl;
+
411  cd_vl.notify({3, fsm_hndl}); // TBD??
+
412  cr_resp_vl.notify({3, fsm_hndl});
+
413 
+
414  } else {
+
415  // scheduling the response
+
416  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
417  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
418  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
419  }
+
420  };
+
421  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
422  SCCTRACE(SCMOD) << "in EndResp of setup_cb for trans" << *fsm_hndl->trans;
+
423  if(fsm_hndl->is_snoop) {
+
424  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
425  tlm::tlm_phase phase = tlm::END_RESP;
+
426  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
427  active_resp_beat[SNOOP] = nullptr;
+
428  // here notify cr_evnt
+
429  fsm_hndl->finish.notify();
+
430  } else {
+
431  if(fsm_hndl->trans->is_read()) {
+
432  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
433  r_end_resp_evt.notify();
+
434  } else if(fsm_hndl->trans->is_write()) {
+
435  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
436  w_end_resp_evt.notify();
+
437  }
+
438  }
+
439  };
+
440  fsm_hndl->fsm->cb[Ack] = [this, fsm_hndl]() -> void {
+
441  SCCTRACE(SCMOD) << "in ACK of setup_cb for " << *fsm_hndl->trans;
+
442  if(fsm_hndl->trans->is_read()) {
+
443  rack_vl.notify(sc_core::SC_ZERO_TIME);
+
444  }
+
445  if(fsm_hndl->trans->is_write()) {
+
446  wack_vl.notify(sc_core::SC_ZERO_TIME);
+
447  }
+
448  };
+
449 }
+
450 
+
451 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::rack_t() {
+
452  this->r_ack.write(false);
+
453  wait(sc_core::SC_ZERO_TIME);
+
454  while(true) {
+
455  wait(rack_vl);
+
456  this->r_ack.write(true);
+
457  wait(clk_i.posedge_event());
+
458  this->r_ack.write(false);
+
459  }
+
460 }
+
461 
+
462 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::wack_t() {
+
463  this->w_ack.write(false);
+
464  wait(sc_core::SC_ZERO_TIME);
+
465  while(true) {
+
466  wait(wack_vl);
+
467  this->w_ack.write(true);
+
468  wait(clk_i.posedge_event());
+
469  this->w_ack.write(false);
+
470  }
+
471 }
+
472 
+
473 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::ar_t() {
+
474  this->ar_valid.write(false);
+
475  wait(sc_core::SC_ZERO_TIME);
+
476  while(true) {
+
477  wait(ar_evt);
+
478  this->ar_valid.write(true);
+
479  do {
+
480  wait(this->ar_ready.posedge_event() | clk_delayed);
+
481  if(this->ar_ready.read())
+
482  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[tlm::TLM_READ_COMMAND]);
+
483  } while(!this->ar_ready.read());
+
484  wait(clk_i.posedge_event());
+
485  this->ar_valid.write(false);
+
486  }
+
487 }
+
488 
+
489 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::r_t() {
+
490  this->r_ready.write(false);
+
491  wait(sc_core::SC_ZERO_TIME);
+
492  while(true) {
+
493  wait(this->r_valid.posedge_event() | clk_delayed);
+
494  if(this->r_valid.event() || (!active_resp[tlm::TLM_READ_COMMAND] && this->r_valid.read())) {
+
495  wait(sc_core::SC_ZERO_TIME);
+
496  auto id = CFG::IS_LITE ? 0U : this->r_id->read().to_uint();
+
497  auto data = this->r_data.read();
+
498  auto resp = this->r_resp.read();
+
499  SCCTRACE(SCMOD) << " r_t() get r_resp = " << resp;
+
500  auto& q = rd_resp_by_id[id];
+
501  sc_assert(q.size());
+
502  auto* fsm_hndl = q.front();
+
503  auto beat_count = fsm_hndl->beat_count;
+
504  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
505  auto byte_offset = beat_count * size;
+
506  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
507  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
508  if(beat_count == 0) {
+
509  auto dptr = fsm_hndl->trans->get_data_ptr();
+
510  if(dptr)
+
511  for(size_t i = offset; i < size; ++i, ++dptr) {
+
512  auto bit_offs = i * 8;
+
513  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
514  }
+
515  } else {
+
516  auto beat_start_idx = beat_count * size - offset;
+
517  auto data_len = fsm_hndl->trans->get_data_length();
+
518  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
519  if(dptr)
+
520  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
521  auto bit_offs = i * 8;
+
522  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
523  }
+
524  }
+
525  } else { // aligned or single beat access
+
526  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
527  if(dptr)
+
528  for(size_t i = 0; i < size; ++i, ++dptr) {
+
529  auto bit_offs = (offset + i) * 8;
+
530  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
531  }
+
532  }
+
533  axi::ace_extension* e;
+
534  fsm_hndl->trans->get_extension(e);
+
535  e->set_cresp(resp);
+
536  e->add_to_response_array(*e);
+
537  /* for Make Trans, Clean Trans and Read barrier Trans, no read data transfer on r_t, only response on r_t
+
538  * */
+
539  if(axi::is_dataless(e)) {
+
540  SCCTRACE(SCMOD) << " r_t() for Make/Clean/Barrier Trans" << *fsm_hndl->trans;
+
541  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
542  } else {
+
543  auto tp = CFG::IS_LITE || this->r_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
544  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
545  react(tp, fsm_hndl);
+
546  }
+
547  wait(r_end_resp_evt);
+
548  this->r_ready->write(true);
+
549  wait(clk_i.posedge_event());
+
550  this->r_ready.write(false);
+
551  }
+
552  }
+
553 }
+
554 
+
555 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::aw_t() {
+
556  this->aw_valid.write(false);
+
557  wait(sc_core::SC_ZERO_TIME);
+
558  while(true) {
+
559  wait(aw_evt);
+
560  this->aw_valid.write(true);
+
561  SCCTRACE(SCMOD) << " aw_t() write aw_valid ";
+
562  do {
+
563  wait(this->aw_ready.posedge_event() | clk_delayed);
+
564  } while(!this->aw_ready.read());
+
565  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
566  if(axi::is_dataless(fsm_hndl->trans->get_extension<axi::ace_extension>()))
+
567  react(axi::fsm::protocol_time_point_e::EndReqE, fsm_hndl);
+
568  wait(clk_i.posedge_event());
+
569  this->aw_valid.write(false);
+
570  }
+
571 }
+
572 
+
573 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::wdata_t() {
+
574  this->w_valid.write(false);
+
575  wait(sc_core::SC_ZERO_TIME);
+
576  while(true) {
+
577  if(!CFG::IS_LITE)
+
578  this->w_last->write(false);
+
579  wait(wdata_vl.default_event());
+
580  auto val = wdata_vl.read();
+
581  SCCTRACE(SCMOD) << "wdata_t() with wdata_vl = " << (uint16_t)val;
+
582  this->w_valid.write(val & 0x1);
+
583  if(!CFG::IS_LITE)
+
584  this->w_last->write(val & 0x2);
+
585  do {
+
586  wait(this->w_ready.posedge_event() | clk_delayed);
+
587  // SCCTRACE(SCMOD) << "wdata_t() received w_ready for " << *active_req[tlm::TLM_WRITE_COMMAND]->trans;
+
588  if(this->w_ready.read()) {
+
589  auto evt =
+
590  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndReqE : axi::fsm::protocol_time_point_e::EndPartReqE;
+
591  react(evt, active_req[tlm::TLM_WRITE_COMMAND]);
+
592  }
+
593  } while(!this->w_ready.read());
+
594  wait(clk_i.posedge_event());
+
595  this->w_valid.write(false);
+
596  }
+
597 }
+
598 
+
599 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::b_t() {
+
600  this->b_ready.write(false);
+
601  wait(sc_core::SC_ZERO_TIME);
+
602  while(true) {
+
603  wait(this->b_valid.posedge_event() | clk_delayed);
+
604  if(this->b_valid.event() || (!active_resp[tlm::TLM_WRITE_COMMAND] && this->b_valid.read())) {
+
605  auto id = !CFG::IS_LITE ? this->b_id->read().to_uint() : 0U;
+
606  auto resp = this->b_resp.read();
+
607  auto& q = wr_resp_by_id[id];
+
608  sc_assert(q.size());
+
609  auto* fsm_hndl = q.front();
+
610  axi::ace_extension* e;
+
611  fsm_hndl->trans->get_extension(e);
+
612  e->set_resp(axi::into<axi::resp_e>(resp));
+
613  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
614  // r_end_req_evt notified in EndResp
+
615  wait(w_end_resp_evt);
+
616  this->b_ready.write(true);
+
617  wait(clk_i.posedge_event());
+
618  this->b_ready.write(false);
+
619  }
+
620  }
+
621 }
+
622 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::ac_t() {
+
623  this->ac_ready.write(false);
+
624  wait(sc_core::SC_ZERO_TIME);
+
625  auto arid = 0U;
+
626  // A snoop transaction must be a full cache line in length,
+
627  // here cachelinesize in byte, -1 because last beat in Resp transmitted
+
628  auto arlen = ((CACHELINE_SZ - 1) / CFG::BUSWIDTH / 8);
+
629  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
630  // here +1 because last beat in Resp transmitted
+
631  auto data_len = (1 << arsize) * (arlen + 1);
+
632  while(true) {
+
633  wait(this->ac_valid.posedge_event() | clk_delayed);
+
634  if(this->ac_valid.read()) {
+
635  SCCTRACE(SCMOD) << "ACVALID detected, for address 0x" << std::hex << this->ac_addr.read();
+
636  SCCTRACE(SCMOD) << "in ac_t(), create snoop trans with data_len= " << data_len;
+
637  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
638  gp->set_address(this->ac_addr.read());
+
639  gp->set_command(tlm::TLM_READ_COMMAND); // snoop command
+
640  gp->set_streaming_width(data_len);
+
641  axi::ace_extension* ext;
+
642  gp->get_extension(ext);
+
643  // if cacheline smaller than buswidth, beat num=1
+
644  if(data_len == (CFG::BUSWIDTH / 8))
+
645  arlen = 1;
+
646  ext->set_length(arlen);
+
647  ext->set_size(arsize);
+
648  ext->set_snoop(axi::into<axi::snoop_e>(this->ac_snoop->read()));
+
649  ext->set_prot(this->ac_prot->read());
+
650  /*snoop transaction of burst length greater than one must be of burst type WRAP.
+
651  * A snoop transaction of burst length one must be of burst type INCR
+
652  */
+
653  ext->set_burst((CACHELINE_SZ * 8) > CFG::BUSWIDTH ? axi::burst_e::WRAP : axi::burst_e::INCR);
+
654  active_req[SNOOP] = find_or_create(gp, true);
+
655  active_req[SNOOP]->is_snoop = true;
+
656  react(axi::fsm::protocol_time_point_e::RequestPhaseBeg, active_req[SNOOP]);
+
657  // ac_end_req_evt notified in EndReqE
+
658  wait(ac_end_req_evt);
+
659  this->ac_ready.write(true);
+
660  wait(clk_i.posedge_event());
+
661  this->ac_ready.write(false);
+
662  }
+
663  }
+
664 }
+
665 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::cd_t() {
+
666  this->cd_valid.write(false);
+
667  wait(sc_core::SC_ZERO_TIME);
+
668  fsm_handle* fsm_hndl;
+
669  uint8_t val;
+
670  while(true) {
+
671  // cd_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
672  std::tie(val, fsm_hndl) = cd_vl.get();
+
673  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat_count = " << fsm_hndl->beat_count;
+
674  SCCTRACE(SCMOD) << __FUNCTION__ << " got snoop beat of trans " << *fsm_hndl->trans;
+
675  // data already packed in Trans in END_REQ via calling operation_cb
+
676  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
677  this->cd_data.write(get_cache_data_for_beat(fsm_hndl));
+
678  this->cd_valid.write(val & 0x1);
+
679  SCCTRACE(SCMOD) << __FUNCTION__ << "() write cd_valid high ";
+
680  this->cd_last->write(val & 0x2);
+
681  do {
+
682  wait(this->cd_ready.posedge_event() | clk_delayed);
+
683  if(this->cd_ready.read()) {
+
684  auto evt =
+
685  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
686 
+
687  // here only schedule EndPartResp for cache data because EndResp is scheduled in cr_resp_t() when last beat is transferred
+
688  if(!(val & 0x2)) { // BEGIN_PARTIAL_REQ ( val=1 ) or in BEG_RESP(val=3)
+
689  SCCTRACE(SCMOD) << __FUNCTION__ << "() receives cd_ready high, schedule evt " << evt2str(evt);
+
690  react(evt, active_resp_beat[SNOOP]);
+
691  }
+
692  }
+
693  } while(!this->cd_ready.read());
+
694  SCCTRACE(SCMOD) << __FUNCTION__ << " finished snoop beat of trans [" << fsm_hndl->trans << "]";
+
695  wait(clk_i.posedge_event());
+
696  this->cd_valid.write(false);
+
697  if(val & 0x2) // if last beat, after one clock cd_last shouldbe low
+
698  this->cd_last->write(false);
+
699  }
+
700 }
+
701 template <typename CFG> inline void axi::pin::ace_initiator<CFG>::cr_resp_t() {
+
702  this->cr_valid.write(false);
+
703  wait(sc_core::SC_ZERO_TIME);
+
704  fsm_handle* fsm_hndl;
+
705  uint8_t val;
+
706  while(true) {
+
707  // cr_resp_vl notified in BEG_RESP(val=3??)
+
708  std::tie(val, fsm_hndl) = cr_resp_vl.get();
+
709  SCCTRACE(SCMOD) << __FUNCTION__ << " (), generate snoop response in cr channel, val = " << (uint16_t)val
+
710  << " total beat_num = " << fsm_hndl->beat_count;
+
711  // data already packed in Trans in END_REQ via bw_o
+
712  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
713  this->cr_resp.write((ext->get_cresp()));
+
714  this->cr_valid.write(true);
+
715  do {
+
716  wait(this->cr_ready.posedge_event() | clk_delayed);
+
717  if(this->cr_ready.read()) {
+
718  auto evt = axi::fsm::protocol_time_point_e::EndRespE;
+
719  SCCTRACE(SCMOD) << __FUNCTION__ << "(), schedule EndRespE ";
+
720  react(evt, active_resp_beat[SNOOP]);
+
721  }
+
722  } while(!this->cr_ready.read());
+
723  SCCTRACE(SCMOD) << "finished snoop response ";
+
724  wait(clk_i.posedge_event());
+
725  this->cr_valid.write(false);
+
726  }
+
727 }
+
728 
+
729 #endif /* _BUS_AXI_PIN_ACE_INITIATOR_H_ */
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+ + +
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ac_ace
snoop address(AC) channel signals
Definition: signal_if.h:629
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace_target_socket< CFG::BUSWIDTH >
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi_extension::add_to_response_array
void add_to_response_array(response &)
add a read response to the response array
Definition: axi_tlm.h:1598
+
axi::b_axi
Definition: signal_if.h:227
+
axi::cd_ace
snoop data(cd) channel signals
Definition: signal_if.h:658
+
axi::cr_ace
snoop response(cr) channel signals
Definition: signal_if.h:680
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::nb_fw
tlm::tlm_sync_enum nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of th...
Definition: base.cpp:190
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
axi::pin::ace_initiator
Definition: ace_initiator.h:48
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::request::get_size
uint8_t get_size() const
set the AxSIZE value of the transaction
Definition: axi_tlm.h:1389
+
axi::response::set_resp
void set_resp(resp_e)
set the response status as POD
Definition: axi_tlm.h:1500
+
axi::rresp_ace
Definition: signal_if.h:344
+
axi::wdata_axi
Definition: signal_if.h:186
+
scc::peq
priority event queue
Definition: peq.h:41
+
+
+ + + + diff --git a/main/ace__lite__initiator_8h_source.html b/main/ace__lite__initiator_8h_source.html new file mode 100644 index 00000000..0dfe41b4 --- /dev/null +++ b/main/ace__lite__initiator_8h_source.html @@ -0,0 +1,613 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_lite_initiator.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_lite_initiator.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_LITE_INITIATOR_H_
+
18 #define _BUS_AXI_PIN_ACE_LITE_INITIATOR_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <tlm_utils/peq_with_cb_and_phase.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 template <typename CFG>
+
34 struct ace_lite_initiator : public sc_core::sc_module,
+
35  public aw_ace_lite<CFG, typename CFG::master_types>,
+
36  public wdata_ace_lite<CFG, typename CFG::master_types>,
+
37  public b_ace_lite<CFG, typename CFG::master_types>,
+
38  public ar_ace_lite<CFG, typename CFG::master_types>,
+
39  public rresp_ace_lite<CFG, typename CFG::master_types>,
+
40  protected axi::fsm::base,
+
41  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
42  SC_HAS_PROCESS(ace_lite_initiator);
+
43 
+
44  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
45  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
46 
+
47  sc_core::sc_in<bool> clk_i{"clk_i"};
+
48 
+
49  axi::axi_target_socket<CFG::BUSWIDTH> tsckt{"tsckt"};
+
50 
+
51  ace_lite_initiator(sc_core::sc_module_name const& nm)
+
52  : sc_core::sc_module(nm)
+
53  // ace_lite has no ack, therefore coherent= false
+
54  , base(CFG::BUSWIDTH, false) {
+
55  instance_name = name();
+
56  tsckt(*this);
+
57  SC_METHOD(clk_delay);
+
58  sensitive << clk_i.pos();
+
59  SC_THREAD(ar_t);
+
60  SC_THREAD(r_t);
+
61  SC_THREAD(aw_t);
+
62  SC_THREAD(wdata_t);
+
63  SC_THREAD(b_t);
+
64  }
+
65 
+
66 private:
+
67  void b_transport(payload_type& trans, sc_core::sc_time& t) override {
+
68  trans.set_dmi_allowed(false);
+
69  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
70  }
+
71 
+
72  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
73  assert(trans.get_extension<axi::ace_extension>() && "missing ACE extension");
+
74  sc_core::sc_time delay; // FIXME: calculate delay correctly
+
75  fw_peq.notify(trans, phase, delay);
+
76  return tlm::TLM_ACCEPTED;
+
77  }
+
78 
+
79  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override {
+
80  trans.set_dmi_allowed(false);
+
81  return false;
+
82  }
+
83 
+
84  unsigned int transport_dbg(payload_type& trans) override { return 0; }
+
85 
+
86  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
87 
+
88  fsm_handle* create_fsm_handle() { return new fsm_handle(); }
+
89 
+
90  void setup_callbacks(fsm_handle* fsm_hndl);
+
91 
+
92  void clk_delay() { clk_delayed.notify(axi::CLK_DELAY); }
+
93 
+
94  void ar_t();
+
95  void r_t();
+
96  void aw_t();
+
97  void wdata_t();
+
98  void b_t();
+
106  static typename CFG::data_t get_cache_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
107  std::array<unsigned, 3> outstanding_cnt{0, 0, 0};
+
108  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
109  std::array<fsm_handle*, 3> active_resp{nullptr, nullptr, nullptr};
+
110  sc_core::sc_clock* clk_if{nullptr};
+
111  sc_core::sc_event clk_delayed, clk_self, r_end_resp_evt, w_end_resp_evt, aw_evt, ar_evt;
+
112  void nb_fw(payload_type& trans, const phase_type& phase) {
+
113  auto t = sc_core::SC_ZERO_TIME;
+
114  base::nb_fw(trans, phase, t);
+
115  }
+
116  tlm_utils::peq_with_cb_and_phase<ace_lite_initiator> fw_peq{this, &ace_lite_initiator::nb_fw};
+
117  std::unordered_map<unsigned, std::deque<fsm_handle*>> rd_resp_by_id, wr_resp_by_id;
+
118  sc_core::sc_buffer<uint8_t> wdata_vl;
+
119  void write_ar(tlm::tlm_generic_payload& trans);
+
120  void write_aw(tlm::tlm_generic_payload& trans);
+
121  void write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last = false);
+
122 };
+
123 
+
124 } // namespace pin
+
125 } // namespace axi
+
126 
+
127 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::write_ar(tlm::tlm_generic_payload& trans) {
+
128  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
129  this->ar_addr.write(addr);
+
130  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
131  this->ar_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
132  this->ar_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
133  this->ar_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
134  this->ar_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
135  if(ext->is_exclusive())
+
136  this->ar_lock->write(true);
+
137  this->ar_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
138  this->ar_prot.write(ext->get_prot());
+
139  this->ar_qos->write(ext->get_qos());
+
140  this->ar_region->write(ext->get_region());
+
141  this->ar_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
142  this->ar_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
143  this->ar_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
144  this->ar_user->write(ext->get_user(axi::common::id_type::CTRL));
+
145  }
+
146 }
+
147 
+
148 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::write_aw(tlm::tlm_generic_payload& trans) {
+
149  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
150  this->aw_addr.write(addr);
+
151  if(auto ext = trans.get_extension<axi::ace_extension>()) {
+
152  this->aw_prot.write(ext->get_prot());
+
153  // TBD?? this->aw_lock.write();
+
154  if(this->aw_id.get_interface())
+
155  this->aw_id->write(sc_dt::sc_uint<CFG::IDWIDTH>(ext->get_id()));
+
156  if(ext->is_exclusive())
+
157  this->aw_lock->write(true);
+
158  this->aw_len->write(sc_dt::sc_uint<8>(ext->get_length()));
+
159  this->aw_size->write(sc_dt::sc_uint<3>(ext->get_size()));
+
160  this->aw_burst->write(sc_dt::sc_uint<2>(axi::to_int(ext->get_burst())));
+
161  this->aw_cache->write(sc_dt::sc_uint<4>(ext->get_cache()));
+
162  this->aw_qos->write(sc_dt::sc_uint<4>(ext->get_qos()));
+
163  this->aw_region->write(sc_dt::sc_uint<4>(ext->get_region()));
+
164  this->aw_user->write(ext->get_user(axi::common::id_type::CTRL));
+
165  this->aw_domain->write(sc_dt::sc_uint<2>((uint8_t)ext->get_domain()));
+
166  this->aw_snoop->write(sc_dt::sc_uint<CFG::AWSNOOPWIDTH>((uint8_t)ext->get_snoop()));
+
167  this->aw_bar->write(sc_dt::sc_uint<2>((uint8_t)ext->get_barrier()));
+
168  /* ace_lite doe not have unique* */
+
169  // this->aw_unique->write(ext->get_unique());
+
170  if(ext->is_stash_nid_en()) {
+
171  this->aw_stashniden->write(true);
+
172  this->aw_stashnid->write(sc_dt::sc_uint<11>(ext->get_stash_nid()));
+
173  }
+
174  if(ext->is_stash_lpid_en()) {
+
175  this->aw_stashlpiden->write(true);
+
176  this->aw_stashlpid->write(sc_dt::sc_uint<5>(ext->get_stash_lpid()));
+
177  }
+
178  }
+
179 }
+
180 
+
181 // FIXME: strb not yet correct
+
182 template <typename CFG>
+
183 inline void axi::pin::ace_lite_initiator<CFG>::write_wdata(tlm::tlm_generic_payload& trans, unsigned beat, bool last) {
+
184  typename CFG::data_t data{0};
+
185  sc_dt::sc_uint<CFG::BUSWIDTH / 8> strb{0};
+
186  auto ext = trans.get_extension<axi::ace_extension>();
+
187  auto size = 1u << ext->get_size();
+
188  auto byte_offset = beat * size;
+
189  auto offset = (trans.get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
190  auto beptr = trans.get_byte_enable_length() ? trans.get_byte_enable_ptr() + byte_offset : nullptr;
+
191  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
192  if(beat == 0) {
+
193  auto dptr = trans.get_data_ptr();
+
194  if(dptr)
+
195  for(size_t i = offset; i < size; ++i, ++dptr) {
+
196  auto bit_offs = i * 8;
+
197  data(bit_offs + 7, bit_offs) = *dptr;
+
198  if(beptr) {
+
199  strb[i] = *beptr == 0xff;
+
200  ++beptr;
+
201  } else
+
202  strb[i] = true;
+
203  }
+
204  } else {
+
205  auto beat_start_idx = byte_offset - offset;
+
206  auto data_len = trans.get_data_length();
+
207  auto dptr = trans.get_data_ptr() + beat_start_idx;
+
208  if(dptr)
+
209  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
210  auto bit_offs = i * 8;
+
211  data(bit_offs + 7, bit_offs) = *dptr;
+
212  if(beptr) {
+
213  strb[i] = *beptr == 0xff;
+
214  ++beptr;
+
215  } else
+
216  strb[i] = true;
+
217  }
+
218  }
+
219  } else { // aligned or single beat access
+
220  auto dptr = trans.get_data_ptr() + byte_offset;
+
221  if(dptr)
+
222  for(size_t i = 0; i < size; ++i, ++dptr) {
+
223  auto bit_offs = (offset + i) * 8;
+
224  data(bit_offs + 7, bit_offs) = *dptr;
+
225  if(beptr) {
+
226  strb[offset + i] = *beptr == 0xff;
+
227  ++beptr;
+
228  } else
+
229  strb[offset + i] = true;
+
230  }
+
231  }
+
232  this->w_data.write(data);
+
233  this->w_strb.write(strb);
+
234  if(!CFG::IS_LITE) {
+
235  this->w_id->write(ext->get_id());
+
236  if(this->w_user.get_interface())
+
237  this->w_user->write(ext->get_user(axi::common::id_type::DATA));
+
238  }
+
239 }
+
240 
+
241 template <typename CFG> typename CFG::data_t axi::pin::ace_lite_initiator<CFG>::get_cache_data_for_beat(fsm_handle* fsm_hndl) {
+
242  auto beat_count = fsm_hndl->beat_count;
+
243  // SCCTRACE(SCMOD) << " " ;
+
244  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
245  auto byte_offset = beat_count * size;
+
246  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
247  typename CFG::data_t data{0};
+
248  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
249  if(beat_count == 0) {
+
250  auto dptr = fsm_hndl->trans->get_data_ptr();
+
251  for(size_t i = offset; i < size; ++i, ++dptr) {
+
252  auto bit_offs = i * 8;
+
253  data(bit_offs + 7, bit_offs) = *dptr;
+
254  }
+
255  } else {
+
256  auto beat_start_idx = byte_offset - offset;
+
257  auto data_len = fsm_hndl->trans->get_data_length();
+
258  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
259  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
260  auto bit_offs = i * 8;
+
261  data(bit_offs + 7, bit_offs) = *dptr;
+
262  }
+
263  }
+
264  } else { // aligned or single beat access
+
265  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
266  for(size_t i = 0; i < size; ++i, ++dptr) {
+
267  auto bit_offs = (offset + i) * 8;
+
268  data(bit_offs + 7, bit_offs) = *dptr;
+
269  }
+
270  }
+
271  return data;
+
272 }
+
273 
+
274 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
275  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
276  if(fsm_hndl->is_snoop) {
+
277  SCCTRACE(SCMOD) << " for snoop in RequestPhaseBeg ";
+
278  } else {
+
279  fsm_hndl->beat_count = 0;
+
280  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
281  if(CFG::IS_LITE) {
+
282  auto offset = fsm_hndl->trans->get_address() % (CFG::BUSWIDTH / 8);
+
283  if(offset + fsm_hndl->trans->get_data_length() > CFG::BUSWIDTH / 8) {
+
284  SCCFATAL(SCMOD) << " transaction " << *fsm_hndl->trans << " is not AXI4Lite compliant";
+
285  }
+
286  }
+
287  }
+
288  };
+
289  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
290  sc_assert(fsm_hndl->trans->is_write());
+
291  if(fsm_hndl->beat_count == 0) {
+
292  write_aw(*fsm_hndl->trans);
+
293  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
294  }
+
295  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count);
+
296  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
297  wdata_vl.write(0x1);
+
298  };
+
299  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
300  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
301  tlm::tlm_phase phase = axi::END_PARTIAL_REQ;
+
302  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
303  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
304  fsm_hndl->beat_count++;
+
305  };
+
306  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
307  SCCTRACEALL(SCMOD) << "In BegReqE of setup_cb";
+
308  switch(fsm_hndl->trans->get_command()) {
+
309  case tlm::TLM_READ_COMMAND:
+
310  active_req[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
311  write_ar(*fsm_hndl->trans);
+
312  ar_evt.notify(sc_core::SC_ZERO_TIME);
+
313  break;
+
314  case tlm::TLM_WRITE_COMMAND:
+
315  active_req[tlm::TLM_WRITE_COMMAND] = fsm_hndl;
+
316  if(fsm_hndl->beat_count == 0) {
+
317  write_aw(*fsm_hndl->trans);
+
318  aw_evt.notify(sc_core::SC_ZERO_TIME);
+
319  }
+
320  /* for dataless trans, no data on wdata_t*/
+
321  auto ext = fsm_hndl->trans->get_extension<ace_extension>();
+
322  if(!axi::is_dataless(ext)) {
+
323  write_wdata(*fsm_hndl->trans, fsm_hndl->beat_count, true);
+
324  wdata_vl.write(0x3);
+
325  }
+
326  }
+
327  };
+
328  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
329  SCCTRACEALL(SCMOD) << "In EndReqE of setup_cb";
+
330  switch(fsm_hndl->trans->get_command()) {
+
331  case tlm::TLM_READ_COMMAND:
+
332  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
333  active_req[tlm::TLM_READ_COMMAND] = nullptr;
+
334  break;
+
335  case tlm::TLM_WRITE_COMMAND:
+
336  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].push_back(fsm_hndl);
+
337  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
338  fsm_hndl->beat_count++;
+
339  }
+
340  tlm::tlm_phase phase = tlm::END_REQ;
+
341  sc_core::sc_time t = (clk_if ? clk_if->period() - axi::CLK_DELAY - 1_ps : sc_core::SC_ZERO_TIME);
+
342  SCCTRACE(SCMOD) << " in EndReq before set_resp";
+
343  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
344  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
345  };
+
346 
+
347  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
348  // scheduling the response
+
349  assert(fsm_hndl->trans->is_read());
+
350  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
351  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
352  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
353  };
+
354  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
355  SCCTRACE(SCMOD) << "in EndPartRespE of setup_cb ";
+
356  fsm_hndl->beat_count++;
+
357  r_end_resp_evt.notify();
+
358  };
+
359  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
360  // scheduling the response
+
361  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
362  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
363  auto ret = tsckt->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
364  };
+
365  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
366  SCCTRACE(SCMOD) << "in EndResp of setup_cb ";
+
367  if(fsm_hndl->trans->is_read()) {
+
368  rd_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
369  r_end_resp_evt.notify();
+
370  }
+
371  if(fsm_hndl->trans->is_write()) {
+
372  wr_resp_by_id[axi::get_axi_id(*fsm_hndl->trans)].pop_front();
+
373  w_end_resp_evt.notify();
+
374  }
+
375  };
+
376 }
+
377 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::ar_t() {
+
378  this->ar_valid.write(false);
+
379  wait(sc_core::SC_ZERO_TIME);
+
380  while(true) {
+
381  wait(ar_evt);
+
382  this->ar_valid.write(true);
+
383  do {
+
384  wait(this->ar_ready.posedge_event() | clk_delayed);
+
385  if(this->ar_ready.read())
+
386  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[tlm::TLM_READ_COMMAND]);
+
387  } while(!this->ar_ready.read());
+
388  wait(clk_i.posedge_event());
+
389  this->ar_valid.write(false);
+
390  }
+
391 }
+
392 
+
393 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::r_t() {
+
394  this->r_ready.write(false);
+
395  wait(sc_core::SC_ZERO_TIME);
+
396  while(true) {
+
397  wait(this->r_valid.posedge_event() | clk_delayed);
+
398  if(this->r_valid.event() || (!active_resp[tlm::TLM_READ_COMMAND] && this->r_valid.read())) {
+
399  wait(sc_core::SC_ZERO_TIME);
+
400  auto id = CFG::IS_LITE ? 0U : this->r_id->read().to_uint();
+
401  auto data = this->r_data.read();
+
402  auto resp = this->r_resp.read();
+
403  auto& q = rd_resp_by_id[id];
+
404  sc_assert(q.size());
+
405  auto* fsm_hndl = q.front();
+
406  auto beat_count = fsm_hndl->beat_count;
+
407  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
408  auto byte_offset = beat_count * size;
+
409  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
410  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
411  if(beat_count == 0) {
+
412  auto dptr = fsm_hndl->trans->get_data_ptr();
+
413  if(dptr)
+
414  for(size_t i = offset; i < size; ++i, ++dptr) {
+
415  auto bit_offs = i * 8;
+
416  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
417  }
+
418  } else {
+
419  auto beat_start_idx = beat_count * size - offset;
+
420  auto data_len = fsm_hndl->trans->get_data_length();
+
421  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
422  if(dptr)
+
423  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
424  auto bit_offs = i * 8;
+
425  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
426  }
+
427  }
+
428  } else { // aligned or single beat access
+
429  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
430  if(dptr)
+
431  for(size_t i = 0; i < size; ++i, ++dptr) {
+
432  auto bit_offs = (offset + i) * 8;
+
433  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
434  }
+
435  }
+
436  axi::ace_extension* e;
+
437  fsm_hndl->trans->get_extension(e);
+
438  e->set_cresp(resp);
+
439  e->add_to_response_array(*e);
+
440  /* dataless trans * */
+
441  if(axi::is_dataless(e)) {
+
442  SCCTRACE(SCMOD) << " r_t() for Make/Clean/Barrier Trans" << *fsm_hndl->trans;
+
443  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
444  } else {
+
445  auto tp = CFG::IS_LITE || this->r_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
446  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
447  react(tp, fsm_hndl);
+
448  }
+
449 
+
450  // r_end_resp_evt notified in EndPartialResp or Endresp
+
451  wait(r_end_resp_evt);
+
452  this->r_ready->write(true);
+
453  wait(clk_i.posedge_event());
+
454  this->r_ready.write(false);
+
455  }
+
456  }
+
457 }
+
458 
+
459 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::aw_t() {
+
460  this->aw_valid.write(false);
+
461  wait(sc_core::SC_ZERO_TIME);
+
462  while(true) {
+
463  wait(aw_evt);
+
464  this->aw_valid.write(true);
+
465  do {
+
466  wait(this->aw_ready.posedge_event() | clk_delayed);
+
467  } while(!this->aw_ready.read());
+
468  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
469  if(axi::is_dataless(fsm_hndl->trans->get_extension<axi::ace_extension>()))
+
470  react(axi::fsm::protocol_time_point_e::EndReqE, fsm_hndl);
+
471  wait(clk_i.posedge_event());
+
472  this->aw_valid.write(false);
+
473  }
+
474 }
+
475 
+
476 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::wdata_t() {
+
477  this->w_valid.write(false);
+
478  wait(sc_core::SC_ZERO_TIME);
+
479  while(true) {
+
480  if(!CFG::IS_LITE)
+
481  this->w_last->write(false);
+
482  wait(wdata_vl.default_event());
+
483  auto val = wdata_vl.read();
+
484  this->w_valid.write(val & 0x1);
+
485  if(!CFG::IS_LITE)
+
486  this->w_last->write(val & 0x2);
+
487  do {
+
488  wait(this->w_ready.posedge_event() | clk_delayed);
+
489  if(this->w_ready.read()) {
+
490  auto evt =
+
491  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndReqE : axi::fsm::protocol_time_point_e::EndPartReqE;
+
492  react(evt, active_req[tlm::TLM_WRITE_COMMAND]);
+
493  }
+
494  } while(!this->w_ready.read());
+
495  wait(clk_i.posedge_event());
+
496  this->w_valid.write(false);
+
497  }
+
498 }
+
499 
+
500 template <typename CFG> inline void axi::pin::ace_lite_initiator<CFG>::b_t() {
+
501  this->b_ready.write(false);
+
502  wait(sc_core::SC_ZERO_TIME);
+
503  while(true) {
+
504  wait(this->b_valid.posedge_event() | clk_delayed);
+
505  if(this->b_valid.event() || (!active_resp[tlm::TLM_WRITE_COMMAND] && this->b_valid.read())) {
+
506  SCCTRACEALL(SCMOD) << " b_t() received b_valid ";
+
507  auto id = !CFG::IS_LITE ? this->b_id->read().to_uint() : 0U;
+
508  auto resp = this->b_resp.read();
+
509  auto& q = wr_resp_by_id[id];
+
510  sc_assert(q.size());
+
511  auto* fsm_hndl = q.front();
+
512  axi::ace_extension* e;
+
513  fsm_hndl->trans->get_extension(e);
+
514  e->set_resp(axi::into<axi::resp_e>(resp));
+
515  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
516  // w_end_resp_evt notified in Endresp
+
517  wait(w_end_resp_evt);
+
518  this->b_ready.write(true);
+
519  wait(clk_i.posedge_event());
+
520  this->b_ready.write(false);
+
521  }
+
522  }
+
523 }
+
524 #endif /* _BUS_AXI_PIN_ace_lite_INITIATOR_H_ */
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi_extension::add_to_response_array
void add_to_response_array(response &)
add a read response to the response array
Definition: axi_tlm.h:1598
+
axi::axi_target_socket< CFG::BUSWIDTH >
+
axi::b_axi
Definition: signal_if.h:227
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::nb_fw
tlm::tlm_sync_enum nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of th...
Definition: base.cpp:190
+
axi::fsm::base::base
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
the constructor
Definition: base.cpp:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::pin::ace_lite_initiator
Definition: ace_lite_initiator.h:41
+
axi::request::get_size
uint8_t get_size() const
set the AxSIZE value of the transaction
Definition: axi_tlm.h:1389
+
axi::response::set_resp
void set_resp(resp_e)
set the response status as POD
Definition: axi_tlm.h:1500
+
axi::rresp_axi
Definition: signal_if.h:308
+
axi::wdata_axi
Definition: signal_if.h:186
+
+
+ + + + diff --git a/main/ace__lite__target_8h_source.html b/main/ace__lite__target_8h_source.html new file mode 100644 index 00000000..6af9d413 --- /dev/null +++ b/main/ace__lite__target_8h_source.html @@ -0,0 +1,616 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_lite_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_lite_target.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_LITE_TARGET_H_
+
18 #define _BUS_AXI_PIN_ACE_LITE_TARGET_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <util/ities.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_lite_target : public sc_core::sc_module,
+
37  public aw_ace_lite<CFG, typename CFG::slave_types>,
+
38  public wdata_ace_lite<CFG, typename CFG::slave_types>,
+
39  public b_ace_lite<CFG, typename CFG::slave_types>,
+
40  public ar_ace_lite<CFG, typename CFG::slave_types>,
+
41  public rresp_ace_lite<CFG, typename CFG::slave_types>,
+
42  protected axi::fsm::base,
+
43  public axi::axi_bw_transport_if<axi::axi_protocol_types> {
+
44  SC_HAS_PROCESS(ace_lite_target);
+
45 
+
46  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
47  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
48 
+
49  sc_core::sc_in<bool> clk_i{"clk_i"};
+
50 
+
51  axi::axi_initiator_socket<CFG::BUSWIDTH> isckt{"isckt"};
+
52 
+
53  ace_lite_target(sc_core::sc_module_name const& nm)
+
54  : sc_core::sc_module(nm)
+
55  // ace_lite has no ack, therefore coherent= false
+
56  , base(CFG::BUSWIDTH, false) {
+
57  instance_name = name();
+
58  isckt.bind(*this);
+
59  SC_METHOD(clk_delay);
+
60  sensitive << clk_i.pos();
+
61  dont_initialize();
+
62  SC_THREAD(ar_t);
+
63  SC_THREAD(rresp_t);
+
64  SC_THREAD(aw_t);
+
65  SC_THREAD(wdata_t);
+
66  SC_THREAD(bresp_t);
+
67  }
+
68 
+
69 private:
+
70  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
71 
+
72  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override;
+
73 
+
74  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
75 
+
76  axi::fsm::fsm_handle* create_fsm_handle() override { return new fsm_handle(); }
+
77 
+
78  void setup_callbacks(axi::fsm::fsm_handle*) override;
+
79 
+
80  void clk_delay() {
+
81 #ifdef DELTA_SYNC
+
82  if(sc_core::sc_delta_count_at_current_time() < 5) {
+
83  clk_self.notify(sc_core::SC_ZERO_TIME);
+
84  next_trigger(clk_self);
+
85  } else
+
86  clk_delayed.notify(sc_core::SC_ZERO_TIME /*clk_if ? clk_if->period() - 1_ps : 1_ps*/);
+
87 #else
+
88  clk_delayed.notify(axi::CLK_DELAY);
+
89 #endif
+
90  }
+
91  void ar_t();
+
92  void rresp_t();
+
93  void aw_t();
+
94  void wdata_t();
+
95  void bresp_t();
+
96  static typename CFG::data_t get_read_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
97  struct aw_data {
+
98  unsigned id;
+
99  uint64_t addr;
+
100  unsigned prot;
+
101  unsigned size;
+
102  unsigned cache;
+
103  unsigned burst;
+
104  unsigned qos;
+
105  unsigned region;
+
106  unsigned len;
+
107  unsigned domain;
+
108  unsigned snoop;
+
109  unsigned bar;
+
110  unsigned unique;
+
111  unsigned stashnid;
+
112  unsigned stashlpid;
+
113  bool lock;
+
114  uint64_t user;
+
115  };
+
116 
+
117  std::deque<axi::fsm::fsm_handle*> snp_resp_queue;
+
118 
+
119  sc_core::sc_clock* clk_if{nullptr};
+
120  sc_core::sc_event clk_delayed, clk_self, ar_end_req_evt, wdata_end_req_evt;
+
121  std::array<fsm_handle*, 3> active_req_beat{nullptr, nullptr, nullptr};
+
122  std::array<fsm_handle*, 3> active_req{nullptr, nullptr, nullptr};
+
123  std::array<fsm_handle*, 3> active_resp_beat{nullptr, nullptr, nullptr};
+
124  scc::peq<aw_data> aw_que;
+
125  scc::peq<std::tuple<uint8_t, fsm_handle*>> rresp_vl;
+
126  scc::peq<std::tuple<uint8_t, fsm_handle*>> wresp_vl;
+
127 };
+
128 } // namespace pin
+
129 } // namespace axi
+
130 
+
131 template <typename CFG>
+
132 inline tlm::tlm_sync_enum axi::pin::ace_lite_target<CFG>::nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) {
+
133  auto ret = tlm::TLM_ACCEPTED;
+
134  SCCTRACE(SCMOD) << "nb_transport_bw with " << phase << " with delay= " << t << " of trans " << trans;
+
135  if(phase == END_PARTIAL_REQ || phase == tlm::END_REQ) { // read/write
+
136  schedule(phase == tlm::END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
137  } else if(phase == axi::BEGIN_PARTIAL_RESP || phase == tlm::BEGIN_RESP) { // read/write response
+
138  schedule(phase == tlm::BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
139  } else
+
140  SCCFATAL(SCMOD) << "Illegal phase received: " << phase;
+
141  return ret;
+
142 }
+
143 
+
144 template <typename CFG>
+
145 inline void axi::pin::ace_lite_target<CFG>::invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) {}
+
146 
+
147 template <typename CFG> typename CFG::data_t axi::pin::ace_lite_target<CFG>::get_read_data_for_beat(fsm_handle* fsm_hndl) {
+
148  auto beat_count = fsm_hndl->beat_count;
+
149  // SCCTRACE(SCMOD) << " " ;
+
150  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
151  auto byte_offset = beat_count * size;
+
152  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
153  typename CFG::data_t data{0};
+
154  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
155  if(beat_count == 0) {
+
156  auto dptr = fsm_hndl->trans->get_data_ptr();
+
157  for(size_t i = offset; i < size; ++i, ++dptr) {
+
158  auto bit_offs = i * 8;
+
159  data(bit_offs + 7, bit_offs) = *dptr;
+
160  }
+
161  } else {
+
162  auto beat_start_idx = byte_offset - offset;
+
163  auto data_len = fsm_hndl->trans->get_data_length();
+
164  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
165  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
166  auto bit_offs = i * 8;
+
167  data(bit_offs + 7, bit_offs) = *dptr;
+
168  }
+
169  }
+
170  } else { // aligned or single beat access
+
171  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
172  for(size_t i = 0; i < size; ++i, ++dptr) {
+
173  auto bit_offs = (offset + i) * 8;
+
174  data(bit_offs + 7, bit_offs) = *dptr;
+
175  }
+
176  }
+
177  return data;
+
178 }
+
179 
+
180 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
181  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void { fsm_hndl->beat_count = 0; };
+
182  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
183  sc_assert(fsm_hndl->trans->get_command() == tlm::TLM_WRITE_COMMAND);
+
184  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_REQ;
+
185  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
186  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
187  if(ret == tlm::TLM_UPDATED) {
+
188  schedule(EndPartReqE, fsm_hndl->trans, t, true);
+
189  }
+
190  };
+
191  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
192  wdata_end_req_evt.notify();
+
193  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
194  fsm_hndl->beat_count++;
+
195  };
+
196  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
197  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
198  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
199  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
200  if(ret == tlm::TLM_UPDATED) {
+
201  schedule(EndReqE, fsm_hndl->trans, t, true);
+
202  }
+
203  };
+
204  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
205  switch(fsm_hndl->trans->get_command()) {
+
206  case tlm::TLM_READ_COMMAND:
+
207  ar_end_req_evt.notify();
+
208  active_req_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
209  break;
+
210  case tlm::TLM_WRITE_COMMAND:
+
211  wdata_end_req_evt.notify();
+
212  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
213  fsm_hndl->beat_count++;
+
214  break;
+
215  default:
+
216  break;
+
217  }
+
218  };
+
219  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
220  assert(fsm_hndl->trans->is_read());
+
221  active_resp_beat[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
222  rresp_vl.notify({1, fsm_hndl});
+
223  };
+
224  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
225  // scheduling the response
+
226  assert(fsm_hndl->trans->is_read());
+
227  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
228  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
229  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
230  active_resp_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
231  fsm_hndl->beat_count++;
+
232  };
+
233  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
234  SCCTRACE(SCMOD) << "processing event BegRespE for trans " << *fsm_hndl->trans;
+
235  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
236  active_resp_beat[fsm_hndl->trans->get_command()] = fsm_hndl;
+
237  switch(fsm_hndl->trans->get_command()) {
+
238  case tlm::TLM_READ_COMMAND:
+
239  rresp_vl.notify({3, fsm_hndl});
+
240  break;
+
241  case tlm::TLM_WRITE_COMMAND:
+
242  wresp_vl.notify({3, fsm_hndl});
+
243  break;
+
244  default:
+
245  break;
+
246  }
+
247  };
+
248  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
249  // scheduling the response
+
250  tlm::tlm_phase phase = tlm::END_RESP;
+
251  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
252  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
253  SCCTRACE(SCMOD) << "EndResp of setup_cb with coherent = " << coherent;
+
254  fsm_hndl->finish.notify();
+
255  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
256  };
+
257 }
+
258 
+
259 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::ar_t() {
+
260  this->ar_ready.write(false);
+
261  wait(sc_core::SC_ZERO_TIME);
+
262  auto arid = 0U;
+
263  auto arlen = 0U;
+
264  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
265  auto data_len = (1 << arsize) * (arlen + 1);
+
266  while(true) {
+
267  wait(this->ar_valid.posedge_event() | clk_delayed);
+
268  if(this->ar_valid.read()) {
+
269  SCCTRACE(SCMOD) << "ARVALID detected for 0x" << std::hex << this->ar_addr.read();
+
270  arid = this->ar_id->read().to_uint();
+
271  arlen = this->ar_len->read().to_uint();
+
272  arsize = this->ar_size->read().to_uint();
+
273  data_len = (1 << arsize) * (arlen + 1);
+
274  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len);
+
275  gp->set_address(this->ar_addr.read());
+
276  gp->set_command(tlm::TLM_READ_COMMAND);
+
277  gp->set_streaming_width(data_len);
+
278  axi::ace_extension* ext;
+
279  gp->get_extension(ext);
+
280  ext->set_id(arid);
+
281  ext->set_length(arlen);
+
282  if(this->ar_lock->read())
+
283  ext->set_exclusive(true);
+
284  ext->set_size(arsize);
+
285  ext->set_burst(axi::into<axi::burst_e>(this->ar_burst->read()));
+
286  ext->set_cache(this->ar_cache->read());
+
287  ext->set_prot(this->ar_prot->read());
+
288  ext->set_qos(this->ar_qos->read());
+
289  ext->set_region(this->ar_region->read());
+
290  ext->set_domain(axi::into<axi::domain_e>(this->ar_domain->read())); // ace extension
+
291  ext->set_snoop(axi::into<axi::snoop_e>(this->ar_snoop->read()));
+
292  ext->set_barrier(axi::into<axi::bar_e>(this->ar_bar->read()));
+
293 
+
294  active_req_beat[tlm::TLM_READ_COMMAND] = find_or_create(gp);
+
295  react(axi::fsm::protocol_time_point_e::BegReqE, active_req_beat[tlm::TLM_READ_COMMAND]);
+
296  wait(ar_end_req_evt);
+
297  this->ar_ready.write(true);
+
298  wait(clk_i.posedge_event());
+
299  this->ar_ready.write(false);
+
300  }
+
301  }
+
302 }
+
303 
+
304 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::rresp_t() {
+
305  this->r_valid.write(false);
+
306  wait(sc_core::SC_ZERO_TIME);
+
307  fsm_handle* fsm_hndl;
+
308  uint8_t val;
+
309  while(true) {
+
310  // rresp_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
311  std::tie(val, fsm_hndl) = rresp_vl.get();
+
312  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat count = " << fsm_hndl->beat_count;
+
313  SCCTRACE(SCMOD) << __FUNCTION__ << " got read response beat of trans " << *fsm_hndl->trans;
+
314  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
315  this->r_data.write(get_read_data_for_beat(fsm_hndl));
+
316  this->r_resp.write(ext->get_cresp());
+
317  this->r_valid.write(val & 0x1);
+
318  if(!CFG::IS_LITE) {
+
319  this->r_id->write(ext->get_id());
+
320  this->r_last->write(val & 0x2);
+
321  }
+
322  do {
+
323  wait(this->r_ready.posedge_event() | clk_delayed);
+
324  if(this->r_ready.read()) {
+
325  auto evt =
+
326  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
327  react(evt, active_resp_beat[tlm::TLM_READ_COMMAND]);
+
328  }
+
329  } while(!this->r_ready.read());
+
330  SCCTRACE(SCMOD) << "finished read response beat of trans [" << fsm_hndl->trans << "]";
+
331  wait(clk_i.posedge_event());
+
332  this->r_valid.write(false);
+
333  if(!CFG::IS_LITE)
+
334  this->r_last->write(false);
+
335  }
+
336 }
+
337 
+
338 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::aw_t() {
+
339  this->aw_ready.write(false);
+
340  wait(sc_core::SC_ZERO_TIME);
+
341  const auto awsize = util::ilog2(CFG::BUSWIDTH / 8);
+
342  while(true) {
+
343  wait(this->aw_valid.posedge_event() | clk_delayed);
+
344  if(this->aw_valid.event() || (!active_req_beat[tlm::TLM_IGNORE_COMMAND] && this->aw_valid.read())) {
+
345  SCCTRACE(SCMOD) << "AWVALID detected for 0x" << std::hex << this->aw_addr.read();
+
346  // clang-format off
+
347  aw_data awd = {CFG::IS_LITE ? 0U : this->aw_id->read().to_uint(),
+
348  this->aw_addr.read().to_uint64(),
+
349  this->aw_prot.read().to_uint(),
+
350  this->aw_size->read().to_uint(),
+
351  this->aw_cache->read().to_uint(),
+
352  this->aw_burst->read().to_uint(),
+
353  this->aw_qos->read().to_uint(),
+
354  this->aw_region->read().to_uint(),
+
355  this->aw_len->read().to_uint(),
+
356  this->aw_domain->read().to_uint(),
+
357  this->aw_snoop->read().to_uint(),
+
358  this->aw_bar->read().to_uint(),
+
359  this->aw_unique->read(),
+
360  this->aw_stashniden->read() ? 0U : this->aw_stashnid->read().to_uint(),
+
361  this->aw_stashlpiden->read()? 0U : this->aw_stashlpid->read().to_uint(),
+
362  this->aw_lock->read() ? true : false,
+
363  0};
+
364  // clang-format on
+
365  aw_que.notify(awd);
+
366  this->aw_ready.write(true);
+
367  wait(clk_i.posedge_event());
+
368  this->aw_ready.write(false);
+
369  }
+
370  }
+
371 }
+
372 
+
373 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::wdata_t() {
+
374  this->w_ready.write(false);
+
375  wait(sc_core::SC_ZERO_TIME);
+
376  while(true) {
+
377  wait(this->w_valid.posedge_event() | clk_delayed);
+
378  this->w_ready.write(false);
+
379  if(this->w_valid.event() || (!active_req_beat[tlm::TLM_WRITE_COMMAND] && this->w_valid.read())) {
+
380  if(!active_req[tlm::TLM_WRITE_COMMAND]) {
+
381  if(!aw_que.has_next())
+
382  wait(aw_que.event());
+
383  auto awd = aw_que.get();
+
384  auto data_len = (1 << awd.size) * (awd.len + 1);
+
385  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
386  gp->set_address(awd.addr);
+
387  gp->set_command(tlm::TLM_WRITE_COMMAND);
+
388  axi::ace_extension* ext;
+
389  gp->get_extension(ext);
+
390  ext->set_id(awd.id);
+
391  ext->set_length(awd.len);
+
392  ext->set_size(awd.size);
+
393  ext->set_burst(axi::into<axi::burst_e>(awd.burst));
+
394  ext->set_prot(awd.prot);
+
395  ext->set_qos(awd.qos);
+
396  ext->set_cache(awd.cache);
+
397  ext->set_region(awd.region);
+
398  ext->set_snoop(axi::into<axi::snoop_e>(awd.snoop));
+
399  ext->set_barrier(axi::into<axi::bar_e>(awd.bar));
+
400  // ace_lite does not have aw_unique ext->set_unique(awd.unique);
+
401  ext->set_stash_nid(awd.stashnid);
+
402  ext->set_stash_lpid(awd.stashlpid);
+
403  ext->set_exclusive(awd.lock);
+
404  if(CFG::USERWIDTH)
+
405  ext->set_user(axi::common::id_type::CTRL, awd.user);
+
406  active_req_beat[tlm::TLM_WRITE_COMMAND] = find_or_create(gp);
+
407  active_req[tlm::TLM_WRITE_COMMAND] = active_req_beat[tlm::TLM_WRITE_COMMAND];
+
408  }
+
409  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
410  SCCTRACE(SCMOD) << "WDATA detected for 0x" << std::hex << this->ar_addr.read();
+
411  auto& gp = fsm_hndl->trans;
+
412  auto data = this->w_data.read();
+
413  auto strb = this->w_strb.read();
+
414  auto last = this->w_last->read();
+
415  auto beat_count = fsm_hndl->beat_count;
+
416  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
417  auto byte_offset = beat_count * size;
+
418  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
419  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
420  if(beat_count == 0) {
+
421  auto dptr = fsm_hndl->trans->get_data_ptr();
+
422  auto beptr = fsm_hndl->trans->get_byte_enable_ptr();
+
423  for(size_t i = offset; i < size; ++i, ++dptr, ++beptr) {
+
424  auto bit_offs = i * 8;
+
425  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
426  *beptr = strb[i] ? 0xff : 0;
+
427  }
+
428  } else {
+
429  auto beat_start_idx = byte_offset - offset;
+
430  auto data_len = fsm_hndl->trans->get_data_length();
+
431  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
432  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + beat_start_idx;
+
433  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr, ++beptr) {
+
434  auto bit_offs = i * 8;
+
435  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
436  *beptr = strb[i] ? 0xff : 0;
+
437  }
+
438  }
+
439  } else { // aligned or single beat access
+
440  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
441  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + byte_offset;
+
442  for(size_t i = 0; i < size; ++i, ++dptr, ++beptr) {
+
443  auto bit_offs = (offset + i) * 8;
+
444  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
445  *beptr = strb[offset + i] ? 0xff : 0;
+
446  }
+
447  }
+
448  // TODO: assuming consecutive write (not scattered)
+
449  auto strobe = strb.to_uint();
+
450  if(last) {
+
451  auto act_data_len = CFG::IS_LITE ? util::bit_count(strobe) : (beat_count + 1) * size;
+
452  // if(CFG::IS_LITE && act_data_len<CFG::BUSWIDTH/8) {
+
453  // std::fill(gp->get_byte_enable_ptr(), gp->get_byte_enable_ptr() + act_data_len, 0xff);
+
454  // std::fill(gp->get_byte_enable_ptr() + act_data_len, gp->get_byte_enable_ptr() +
+
455  // gp->get_byte_enable_length(), 0x0);
+
456  // }
+
457  gp->set_data_length(act_data_len);
+
458  gp->set_byte_enable_length(act_data_len);
+
459  gp->set_streaming_width(act_data_len);
+
460  }
+
461  auto tp = this->w_last->read() ? axi::fsm::protocol_time_point_e::BegReqE : axi::fsm::protocol_time_point_e::BegPartReqE;
+
462  react(tp, fsm_hndl);
+
463  // notified in EndPartReqE/EndReq
+
464  wait(wdata_end_req_evt);
+
465  this->w_ready.write(true);
+
466  wait(clk_i.posedge_event());
+
467  this->w_ready.write(false);
+
468  if(last)
+
469  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
470  }
+
471  }
+
472 }
+
473 
+
474 template <typename CFG> inline void axi::pin::ace_lite_target<CFG>::bresp_t() {
+
475  this->b_valid.write(false);
+
476  wait(sc_core::SC_ZERO_TIME);
+
477  fsm_handle* fsm_hndl;
+
478  uint8_t val;
+
479  while(true) {
+
480  std::tie(val, fsm_hndl) = wresp_vl.get();
+
481  SCCTRACE(SCMOD) << "got write response of trans " << *fsm_hndl->trans;
+
482  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
483  this->b_resp.write(axi::to_int(ext->get_resp()));
+
484  this->b_valid.write(true);
+
485  if(!CFG::IS_LITE)
+
486  this->b_id->write(ext->get_id());
+
487  SCCTRACE(SCMOD) << "got write response";
+
488  do {
+
489  wait(this->b_ready.posedge_event() | clk_delayed);
+
490  if(this->b_ready.read()) {
+
491  react(axi::fsm::protocol_time_point_e::EndRespE, active_resp_beat[tlm::TLM_WRITE_COMMAND]);
+
492  }
+
493  } while(!this->b_ready.read());
+
494  SCCTRACE(SCMOD) << "finished write response of trans [" << fsm_hndl->trans << "]";
+
495  wait(clk_i.posedge_event());
+
496  this->b_valid.write(false);
+
497  }
+
498 }
+
499 
+
500 #endif /* _BUS_AXI_PIN_ace_lite_TARGET_H_ */
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::axi_bw_transport_if
tlm::tlm_bw_transport_if< TYPES > axi_bw_transport_if
alias declaration for the backward interface:
Definition: axi_tlm.h:918
+
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace::set_barrier
void set_barrier(bar_e)
set the AxBAR value
Definition: axi_tlm.h:1449
+
axi::ace::set_domain
void set_domain(domain_e)
set the AxDOMAIN value
Definition: axi_tlm.h:1441
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi4::set_exclusive
void set_exclusive(bool=true)
get the exclusive bit of AxLOCK (AxLOCK[0])
Definition: axi_tlm.h:1324
+
axi::axi_initiator_socket< CFG::BUSWIDTH >
+
axi::b_axi
Definition: signal_if.h:227
+
axi::common::set_id
void set_id(unsigned int value)
Definition: axi_tlm.h:1252
+
axi::common::set_user
void set_user(id_type chnl, unsigned int value)
Definition: axi_tlm.h:1256
+
axi::common::get_id
unsigned int get_id() const
Definition: axi_tlm.h:1254
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::pin::ace_lite_target
Definition: ace_lite_target.h:43
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_qos
void set_qos(uint8_t)
set the AxQOS (quality of service) value
Definition: axi_tlm.h:1426
+
axi::request::set_cache
void set_cache(uint8_t)
set the AxCACHE value as POD, only value from 0..15 are allowed
Definition: axi_tlm.h:1434
+
axi::request::set_region
void set_region(uint8_t)
set the AxREGION value
Definition: axi_tlm.h:1430
+
axi::request::set_stash_lpid
void set_stash_lpid(uint8_t)
set the raw AWSTASHLPID value
Definition: axi_tlm.h:1467
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::request::set_stash_nid
void set_stash_nid(uint8_t)
set the raw AWSTASHNID value
Definition: axi_tlm.h:1461
+
axi::response::get_resp
resp_e get_resp() const
get the response status as POD
Definition: axi_tlm.h:1502
+
axi::rresp_axi
Definition: signal_if.h:308
+
axi::wdata_axi
Definition: signal_if.h:186
+ +
+
+ + + + diff --git a/main/ace__target_8h_source.html b/main/ace__target_8h_source.html new file mode 100644 index 00000000..51daa3bb --- /dev/null +++ b/main/ace__target_8h_source.html @@ -0,0 +1,822 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/axi/pin/ace_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2021-2022 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #ifndef _BUS_AXI_PIN_ACE_TARGET_H_
+
18 #define _BUS_AXI_PIN_ACE_TARGET_H_
+
19 
+
20 #include <axi/axi_tlm.h>
+
21 #include <axi/fsm/base.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/signal_if.h>
+
24 #include <systemc>
+
25 #include <tlm/scc/tlm_mm.h>
+
26 #include <util/ities.h>
+
27 
+
29 namespace axi {
+
31 namespace pin {
+
32 
+
33 using namespace axi::fsm;
+
34 
+
35 template <typename CFG>
+
36 struct ace_target : public sc_core::sc_module,
+
37  public aw_ace<CFG, typename CFG::slave_types>,
+
38  public wdata_ace<CFG, typename CFG::slave_types>,
+
39  public b_ace<CFG, typename CFG::slave_types>,
+
40  public ar_ace<CFG, typename CFG::slave_types>,
+
41  public rresp_ace<CFG, typename CFG::slave_types>,
+
42 
+
43  public ac_ace<CFG, typename CFG::slave_types>,
+
44  public cr_ace<CFG, typename CFG::slave_types>,
+
45  public cd_ace<CFG, typename CFG::slave_types>,
+
46 
+
47  protected axi::fsm::base,
+
48  public axi::ace_bw_transport_if<axi::axi_protocol_types> {
+
49  SC_HAS_PROCESS(ace_target);
+
50 
+
51  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
52  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
53 
+
54  sc_core::sc_in<bool> clk_i{"clk_i"};
+
55 
+
56  axi::ace_initiator_socket<CFG::BUSWIDTH> isckt{"isckt"};
+
57 
+
58  ace_target(sc_core::sc_module_name const& nm)
+
59  : sc_core::sc_module(nm)
+
60  // coherent= true
+
61  , base(CFG::BUSWIDTH, true) {
+
62  instance_name = name();
+
63  isckt.bind(*this);
+
64  SC_METHOD(clk_delay);
+
65  sensitive << clk_i.pos();
+
66  dont_initialize();
+
67  SC_THREAD(ar_t);
+
68  SC_THREAD(rresp_t);
+
69  SC_THREAD(aw_t);
+
70  SC_THREAD(wdata_t);
+
71  SC_THREAD(bresp_t);
+
72  SC_THREAD(ac_t);
+
73  SC_THREAD(cr_t);
+
74  SC_THREAD(cd_t);
+
75  }
+
76 
+
77 private:
+
78  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
79  void b_snoop(payload_type& trans, sc_core::sc_time& t) override{};
+
80 
+
81  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override;
+
82 
+
83  void end_of_elaboration() override { clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface()); }
+
84 
+
85  axi::fsm::fsm_handle* create_fsm_handle() override { return new fsm_handle(); }
+
86 
+
87  void setup_callbacks(axi::fsm::fsm_handle*) override;
+
88 
+
94  unsigned snoop_latency{1};
+
95 
+
96  void clk_delay() {
+
97 #ifdef DELTA_SYNC
+
98  if(sc_core::sc_delta_count_at_current_time() < 5) {
+
99  clk_self.notify(sc_core::SC_ZERO_TIME);
+
100  next_trigger(clk_self);
+
101  } else
+
102  clk_delayed.notify(sc_core::SC_ZERO_TIME /*clk_if ? clk_if->period() - 1_ps : 1_ps*/);
+
103 #else
+
104  clk_delayed.notify(axi::CLK_DELAY);
+
105 #endif
+
106  }
+
107  void ar_t();
+
108  void rresp_t();
+
109  void aw_t();
+
110  void wdata_t();
+
111  void bresp_t();
+
112  void ac_t();
+
113  void cr_t();
+
114  void cd_t();
+
115  static typename CFG::data_t get_read_data_for_beat(fsm::fsm_handle* fsm_hndl);
+
116  struct aw_data {
+
117  unsigned id;
+
118  uint64_t addr;
+
119  unsigned prot;
+
120  unsigned size;
+
121  unsigned cache;
+
122  unsigned burst;
+
123  unsigned qos;
+
124  unsigned region;
+
125  unsigned len;
+
126  unsigned domain;
+
127  unsigned snoop;
+
128  unsigned bar;
+
129  unsigned unique;
+
130  bool lock;
+
131  uint64_t user;
+
132  };
+
133 
+
134  std::deque<axi::fsm::fsm_handle*> snp_resp_queue;
+
135 
+
136  sc_core::sc_clock* clk_if{nullptr};
+
137  sc_core::sc_event clk_delayed, clk_self, ar_end_req_evt, wdata_end_req_evt, ac_evt, cd_end_req_evt, cr_end_req_evt;
+
138  std::array<fsm_handle*, 3> active_req_beat{nullptr, nullptr, nullptr};
+
139  std::array<fsm_handle*, 4> active_req{nullptr, nullptr, nullptr};
+
140  std::array<fsm_handle*, 3> active_resp_beat{nullptr, nullptr, nullptr};
+
141  scc::peq<aw_data> aw_que;
+
142  scc::peq<std::tuple<uint8_t, fsm_handle*>> rresp_vl;
+
143  scc::peq<std::tuple<uint8_t, fsm_handle*>> wresp_vl;
+
144  scc::peq<std::tuple<uint8_t, fsm_handle*>> cr_vl; // snoop response
+
145 
+
146  unsigned int SNOOP = 3; // TBD??
+
147  void write_ac(tlm::tlm_generic_payload& trans);
+
148 };
+
149 
+
150 } // namespace pin
+
151 } // namespace axi
+
152 
+
153 template <typename CFG>
+
154 inline tlm::tlm_sync_enum axi::pin::ace_target<CFG>::nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) {
+
155  auto ret = tlm::TLM_ACCEPTED;
+
156  SCCTRACE(SCMOD) << "nb_transport_bw with " << phase << " with delay= " << t << " of trans " << trans;
+
157  if(phase == END_PARTIAL_REQ || phase == tlm::END_REQ) { // read/write
+
158  schedule(phase == tlm::END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
159  } else if(phase == axi::BEGIN_PARTIAL_RESP || phase == tlm::BEGIN_RESP) { // read/write response
+
160  schedule(phase == tlm::BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
161  } else if(phase == tlm::BEGIN_REQ) { // snoop read
+
162  auto fsm_hndl = find_or_create(&trans, true);
+
163  fsm_hndl->is_snoop = true;
+
164  schedule(BegReqE, &trans, t);
+
165  } else if(phase == END_PARTIAL_RESP || phase == tlm::END_RESP) { // snoop read response
+
166  schedule(phase == tlm::END_RESP ? EndRespE : EndPartRespE, &trans, t);
+
167  }
+
168  return ret;
+
169 }
+
170 
+
171 template <typename CFG>
+
172 inline void axi::pin::ace_target<CFG>::invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) {}
+
173 
+
174 template <typename CFG> typename CFG::data_t axi::pin::ace_target<CFG>::get_read_data_for_beat(fsm_handle* fsm_hndl) {
+
175  auto beat_count = fsm_hndl->beat_count;
+
176  // SCCTRACE(SCMOD) << " " ;
+
177  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
178  auto byte_offset = beat_count * size;
+
179  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
180  typename CFG::data_t data{0};
+
181  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
182  if(beat_count == 0) {
+
183  auto dptr = fsm_hndl->trans->get_data_ptr();
+
184  for(size_t i = offset; i < size; ++i, ++dptr) {
+
185  auto bit_offs = i * 8;
+
186  data(bit_offs + 7, bit_offs) = *dptr;
+
187  }
+
188  } else {
+
189  auto beat_start_idx = byte_offset - offset;
+
190  auto data_len = fsm_hndl->trans->get_data_length();
+
191  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
192  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
193  auto bit_offs = i * 8;
+
194  data(bit_offs + 7, bit_offs) = *dptr;
+
195  }
+
196  }
+
197  } else { // aligned or single beat access
+
198  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
199  for(size_t i = 0; i < size; ++i, ++dptr) {
+
200  auto bit_offs = (offset + i) * 8;
+
201  data(bit_offs + 7, bit_offs) = *dptr;
+
202  }
+
203  }
+
204  return data;
+
205 }
+
206 
+
207 template <typename CFG> inline void axi::pin::ace_target<CFG>::setup_callbacks(fsm_handle* fsm_hndl) {
+
208  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void { fsm_hndl->beat_count = 0; };
+
209  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
210  sc_assert(fsm_hndl->trans->get_command() == tlm::TLM_WRITE_COMMAND);
+
211  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_REQ;
+
212  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
213  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
214  if(ret == tlm::TLM_UPDATED) {
+
215  schedule(EndPartReqE, fsm_hndl->trans, t, true);
+
216  }
+
217  };
+
218  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
219  wdata_end_req_evt.notify();
+
220  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
221  fsm_hndl->beat_count++;
+
222  };
+
223  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
224  if(fsm_hndl->is_snoop) {
+
225  SCCTRACE(SCMOD) << "in BegReq of setup_cb, call write_ac() ";
+
226  active_req[SNOOP] = fsm_hndl;
+
227  write_ac(*fsm_hndl->trans);
+
228  ac_evt.notify(sc_core::SC_ZERO_TIME);
+
229 
+
230  } else {
+
231  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
232  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
233  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
234  if(ret == tlm::TLM_UPDATED) {
+
235  schedule(EndReqE, fsm_hndl->trans, t, true);
+
236  }
+
237  }
+
238  };
+
239 
+
240  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
241  if(fsm_hndl->is_snoop) {
+
242  SCCTRACE(SCMOD) << "snoop with EndReq evt";
+
243  auto latency = 0;
+
244  snp_resp_queue.push_back(fsm_hndl);
+
245  active_req[SNOOP] = nullptr;
+
246  tlm::tlm_phase phase = tlm::END_REQ;
+
247  // ?? here t(delay) should be zero or clock cycle??
+
248  // sc_core::sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : sc_core::SC_ZERO_TIME);
+
249  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
250  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
251  auto exta = fsm_hndl->trans->get_extension<ace_extension>();
+
252  fsm_hndl->trans->set_response_status(tlm::TLM_OK_RESPONSE);
+
253  } else {
+
254  switch(fsm_hndl->trans->get_command()) {
+
255  case tlm::TLM_READ_COMMAND:
+
256  ar_end_req_evt.notify();
+
257  active_req_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
258  break;
+
259  case tlm::TLM_WRITE_COMMAND:
+
260  wdata_end_req_evt.notify();
+
261  active_req_beat[tlm::TLM_WRITE_COMMAND] = nullptr;
+
262  fsm_hndl->beat_count++;
+
263  break;
+
264  default:
+
265  break;
+
266  }
+
267  }
+
268  };
+
269  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
270  if(fsm_hndl->is_snoop) {
+
271  tlm::tlm_phase phase = axi::BEGIN_PARTIAL_RESP;
+
272  sc_core::sc_time t;
+
273  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
274 
+
275  } else {
+
276  assert(fsm_hndl->trans->is_read());
+
277  active_resp_beat[tlm::TLM_READ_COMMAND] = fsm_hndl;
+
278  rresp_vl.notify({1, fsm_hndl});
+
279  }
+
280  };
+
281  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
282  if(fsm_hndl->is_snoop) {
+
283  fsm_hndl->beat_count++;
+
284  cd_end_req_evt.notify();
+
285 
+
286  } else {
+
287  // scheduling the response
+
288  assert(fsm_hndl->trans->is_read());
+
289  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
290  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
291  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
292  active_resp_beat[tlm::TLM_READ_COMMAND] = nullptr;
+
293  fsm_hndl->beat_count++;
+
294  }
+
295  };
+
296  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
297  SCCTRACE(SCMOD) << "processing event BegRespE for trans " << *fsm_hndl->trans;
+
298  if(fsm_hndl->is_snoop) {
+
299  tlm::tlm_phase phase = tlm::BEGIN_RESP;
+
300  sc_core::sc_time t;
+
301  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
302  } else {
+
303  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
304  active_resp_beat[fsm_hndl->trans->get_command()] = fsm_hndl;
+
305  switch(fsm_hndl->trans->get_command()) {
+
306  case tlm::TLM_READ_COMMAND:
+
307  rresp_vl.notify({3, fsm_hndl});
+
308  break;
+
309  case tlm::TLM_WRITE_COMMAND:
+
310  wresp_vl.notify({3, fsm_hndl});
+
311  break;
+
312  default:
+
313  break;
+
314  }
+
315  }
+
316  };
+
317  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
318  if(fsm_hndl->is_snoop) {
+
319  SCCTRACE(SCMOD) << " in EndRespE ";
+
320  cd_end_req_evt.notify();
+
321  cr_end_req_evt.notify(); // need to check these two event??
+
322  snp_resp_queue.pop_front();
+
323  fsm_hndl->finish.notify();
+
324 
+
325  } else {
+
326  // scheduling the response
+
327  tlm::tlm_phase phase = tlm::END_RESP;
+
328  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
329  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
330  SCCTRACE(SCMOD) << "EndResp of setup_cb with coherent = " << coherent;
+
331  if(coherent)
+
332  schedule(Ack, fsm_hndl->trans, t); // later can add ack_resp_delay to replace t
+
333  else {
+
334  fsm_hndl->finish.notify();
+
335  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
336  }
+
337  }
+
338  };
+
339  fsm_hndl->fsm->cb[Ack] = [this, fsm_hndl]() -> void {
+
340  SCCTRACE(SCMOD) << " in Ack of setup_cb";
+
341  sc_core::sc_time t(sc_core::SC_ZERO_TIME);
+
342  tlm::tlm_phase phase = axi::ACK;
+
343  auto ret = isckt->nb_transport_fw(*fsm_hndl->trans, phase, t);
+
344  fsm_hndl->finish.notify();
+
345  active_resp_beat[fsm_hndl->trans->get_command()] = nullptr;
+
346  };
+
347 }
+
348 
+
349 template <typename CFG> inline void axi::pin::ace_target<CFG>::ar_t() {
+
350  this->ar_ready.write(false);
+
351  wait(sc_core::SC_ZERO_TIME);
+
352  auto arid = 0U;
+
353  auto arlen = 0U;
+
354  auto arsize = util::ilog2(CFG::BUSWIDTH / 8);
+
355 
+
356  auto data_len = (1 << arsize) * (arlen + 1);
+
357  while(true) {
+
358  wait(this->ar_valid.posedge_event() | clk_delayed);
+
359  if(this->ar_valid.read()) {
+
360  SCCTRACE(SCMOD) << "ARVALID detected for 0x" << std::hex << this->ar_addr.read();
+
361  if(!CFG::IS_LITE) {
+
362  arid = this->ar_id->read().to_uint();
+
363  arlen = this->ar_len->read().to_uint();
+
364  arsize = this->ar_size->read().to_uint();
+
365  }
+
366  data_len = (1 << arsize) * (arlen + 1);
+
367  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len);
+
368  gp->set_address(this->ar_addr.read());
+
369  gp->set_command(tlm::TLM_READ_COMMAND);
+
370  gp->set_streaming_width(data_len);
+
371  axi::ace_extension* ext;
+
372  gp->get_extension(ext);
+
373  ext->set_id(arid);
+
374  ext->set_length(arlen);
+
375  ext->set_size(arsize);
+
376  if(this->ar_lock->read())
+
377  ext->set_exclusive(true);
+
378  ext->set_domain(axi::into<axi::domain_e>(this->ar_domain->read())); // ace extension
+
379  ext->set_snoop(axi::into<axi::snoop_e>(this->ar_snoop->read()));
+
380  ext->set_barrier(axi::into<axi::bar_e>(this->ar_bar->read()));
+
381  ext->set_burst(CFG::IS_LITE ? axi::burst_e::INCR : axi::into<axi::burst_e>(this->ar_burst->read()));
+
382  ext->set_cache(this->ar_cache->read());
+
383  ext->set_prot(this->ar_prot->read());
+
384  ext->set_qos(this->ar_qos->read());
+
385  ext->set_region(this->ar_region->read());
+
386 
+
387  active_req_beat[tlm::TLM_READ_COMMAND] = find_or_create(gp);
+
388  react(axi::fsm::protocol_time_point_e::BegReqE, active_req_beat[tlm::TLM_READ_COMMAND]);
+
389  wait(ar_end_req_evt);
+
390  this->ar_ready.write(true);
+
391  wait(clk_i.posedge_event());
+
392  this->ar_ready.write(false);
+
393  }
+
394  }
+
395 }
+
396 
+
397 template <typename CFG> inline void axi::pin::ace_target<CFG>::rresp_t() {
+
398  this->r_valid.write(false);
+
399  wait(sc_core::SC_ZERO_TIME);
+
400  fsm_handle* fsm_hndl;
+
401  uint8_t val;
+
402  while(true) {
+
403  // rresp_vl notified in BEGIN_PARTIAL_REQ ( val=1 ??)or in BEG_RESP(val=3??)
+
404  std::tie(val, fsm_hndl) = rresp_vl.get();
+
405  SCCTRACE(SCMOD) << __FUNCTION__ << " val = " << (uint16_t)val << " beat count = " << fsm_hndl->beat_count;
+
406  SCCTRACE(SCMOD) << __FUNCTION__ << " got read response beat of trans " << *fsm_hndl->trans;
+
407  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
408  this->r_data.write(get_read_data_for_beat(fsm_hndl));
+
409  this->r_resp.write(ext->get_cresp());
+
410  this->r_valid.write(val & 0x1);
+
411  if(!CFG::IS_LITE) {
+
412  this->r_id->write(ext->get_id());
+
413  this->r_last->write(val & 0x2);
+
414  }
+
415  do {
+
416  wait(this->r_ready.posedge_event() | clk_delayed);
+
417  if(this->r_ready.read()) {
+
418  auto evt =
+
419  CFG::IS_LITE || (val & 0x2) ? axi::fsm::protocol_time_point_e::EndRespE : axi::fsm::protocol_time_point_e::EndPartRespE;
+
420  react(evt, active_resp_beat[tlm::TLM_READ_COMMAND]);
+
421  }
+
422  } while(!this->r_ready.read());
+
423  SCCTRACE(SCMOD) << "finished read response beat of trans [" << fsm_hndl->trans << "]";
+
424  wait(clk_i.posedge_event());
+
425  this->r_valid.write(false);
+
426  if(!CFG::IS_LITE)
+
427  this->r_last->write(false);
+
428  }
+
429 }
+
430 
+
431 template <typename CFG> inline void axi::pin::ace_target<CFG>::aw_t() {
+
432  this->aw_ready.write(false);
+
433  wait(sc_core::SC_ZERO_TIME);
+
434  const auto awsize = util::ilog2(CFG::BUSWIDTH / 8);
+
435  while(true) {
+
436  wait(this->aw_valid.posedge_event() | clk_delayed);
+
437  if(this->aw_valid.event() || (!active_req_beat[tlm::TLM_IGNORE_COMMAND] && this->aw_valid.read())) {
+
438  SCCTRACE(SCMOD) << "AWVALID detected for 0x" << std::hex << this->aw_addr.read();
+
439  // clang-format off
+
440  aw_data awd = {CFG::IS_LITE ? 0U : this->aw_id->read().to_uint(),
+
441  this->aw_addr.read().to_uint64(),
+
442  this->aw_prot.read().to_uint(),
+
443  CFG::IS_LITE ? awsize : this->aw_size->read().to_uint(),
+
444  CFG::IS_LITE ? 0U : this->aw_cache->read().to_uint(),
+
445  CFG::IS_LITE ? 0U : this->aw_burst->read().to_uint(),
+
446  CFG::IS_LITE ? 0U : this->aw_qos->read().to_uint(),
+
447  CFG::IS_LITE ? 0U : this->aw_region->read().to_uint(),
+
448  CFG::IS_LITE ? 0U : this->aw_len->read().to_uint(),
+
449  CFG::IS_LITE ? 0U : this->aw_domain->read().to_uint(),
+
450  CFG::IS_LITE ? 0U : this->aw_snoop->read().to_uint(),
+
451  CFG::IS_LITE ? 0U : this->aw_bar->read().to_uint(),
+
452  CFG::IS_LITE ? 0U : this->aw_unique->read(),
+
453  CFG::IS_LITE ? false : this->aw_lock->read(),
+
454  0};
+
455  // clang-format on
+
456  aw_que.notify(awd);
+
457  this->aw_ready.write(true);
+
458  wait(clk_i.posedge_event());
+
459  this->aw_ready.write(false);
+
460  }
+
461  }
+
462 }
+
463 
+
464 template <typename CFG> inline void axi::pin::ace_target<CFG>::wdata_t() {
+
465  this->w_ready.write(false);
+
466  wait(sc_core::SC_ZERO_TIME);
+
467  while(true) {
+
468  wait(this->w_valid.posedge_event() | clk_delayed);
+
469  this->w_ready.write(false);
+
470  if(this->w_valid.event() || (!active_req_beat[tlm::TLM_WRITE_COMMAND] && this->w_valid.read())) {
+
471  if(!active_req[tlm::TLM_WRITE_COMMAND]) {
+
472  if(!aw_que.has_next())
+
473  wait(aw_que.event());
+
474  auto awd = aw_que.get();
+
475  auto data_len = (1 << awd.size) * (awd.len + 1);
+
476  auto gp = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(data_len, true);
+
477  gp->set_address(awd.addr);
+
478  gp->set_command(tlm::TLM_WRITE_COMMAND);
+
479  axi::ace_extension* ext;
+
480  gp->get_extension(ext);
+
481  ext->set_id(awd.id);
+
482  ext->set_length(awd.len);
+
483  ext->set_size(awd.size);
+
484  ext->set_burst(axi::into<axi::burst_e>(awd.burst));
+
485  ext->set_prot(awd.prot);
+
486  ext->set_qos(awd.qos);
+
487  ext->set_cache(awd.cache);
+
488  ext->set_region(awd.region);
+
489  ext->set_snoop(axi::into<axi::snoop_e>(awd.snoop));
+
490  ext->set_barrier(axi::into<axi::bar_e>(awd.bar));
+
491  ext->set_unique(awd.unique);
+
492  ext->set_exclusive(awd.lock);
+
493  if(CFG::USERWIDTH)
+
494  ext->set_user(axi::common::id_type::CTRL, awd.user);
+
495 
+
496  active_req_beat[tlm::TLM_WRITE_COMMAND] = find_or_create(gp);
+
497  active_req[tlm::TLM_WRITE_COMMAND] = active_req_beat[tlm::TLM_WRITE_COMMAND];
+
498  }
+
499  auto* fsm_hndl = active_req[tlm::TLM_WRITE_COMMAND];
+
500  SCCTRACE(SCMOD) << "WDATA detected for 0x" << std::hex << this->ar_addr.read();
+
501  auto& gp = fsm_hndl->trans;
+
502  auto data = this->w_data.read();
+
503  auto strb = this->w_strb.read();
+
504  auto last = CFG::IS_LITE ? true : this->w_last->read();
+
505  auto beat_count = fsm_hndl->beat_count;
+
506  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
507  auto byte_offset = beat_count * size;
+
508  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
509  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
510  if(beat_count == 0) {
+
511  auto dptr = fsm_hndl->trans->get_data_ptr();
+
512  auto beptr = fsm_hndl->trans->get_byte_enable_ptr();
+
513  for(size_t i = offset; i < size; ++i, ++dptr, ++beptr) {
+
514  auto bit_offs = i * 8;
+
515  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
516  *beptr = strb[i] ? 0xff : 0;
+
517  }
+
518  } else {
+
519  auto beat_start_idx = byte_offset - offset;
+
520  auto data_len = fsm_hndl->trans->get_data_length();
+
521  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
522  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + beat_start_idx;
+
523  for(size_t i = 0; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr, ++beptr) {
+
524  auto bit_offs = i * 8;
+
525  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
526  *beptr = strb[i] ? 0xff : 0;
+
527  }
+
528  }
+
529  } else { // aligned or single beat access
+
530  auto dptr = fsm_hndl->trans->get_data_ptr() + byte_offset;
+
531  auto beptr = fsm_hndl->trans->get_byte_enable_ptr() + byte_offset;
+
532  for(size_t i = 0; i < size; ++i, ++dptr, ++beptr) {
+
533  auto bit_offs = (offset + i) * 8;
+
534  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
535  *beptr = strb[offset + i] ? 0xff : 0;
+
536  }
+
537  }
+
538  // TODO: assuming consecutive write (not scattered)
+
539  auto strobe = strb.to_uint();
+
540  if(last) {
+
541  auto act_data_len = CFG::IS_LITE ? util::bit_count(strobe) : (beat_count + 1) * size;
+
542  // if(CFG::IS_LITE && act_data_len<CFG::BUSWIDTH/8) {
+
543  // std::fill(gp->get_byte_enable_ptr(), gp->get_byte_enable_ptr() + act_data_len, 0xff);
+
544  // std::fill(gp->get_byte_enable_ptr() + act_data_len, gp->get_byte_enable_ptr() +
+
545  // gp->get_byte_enable_length(), 0x0);
+
546  // }
+
547  gp->set_data_length(act_data_len);
+
548  gp->set_byte_enable_length(act_data_len);
+
549  gp->set_streaming_width(act_data_len);
+
550  }
+
551  auto tp = CFG::IS_LITE || this->w_last->read() ? axi::fsm::protocol_time_point_e::BegReqE
+
552  : axi::fsm::protocol_time_point_e::BegPartReqE;
+
553  react(tp, fsm_hndl);
+
554  // notifed in EndPartReqE/EndReq
+
555  wait(wdata_end_req_evt);
+
556  this->w_ready.write(true);
+
557  wait(clk_i.posedge_event());
+
558  this->w_ready.write(false);
+
559  if(last)
+
560  active_req[tlm::TLM_WRITE_COMMAND] = nullptr;
+
561  }
+
562  }
+
563 }
+
564 
+
565 template <typename CFG> inline void axi::pin::ace_target<CFG>::bresp_t() {
+
566  this->b_valid.write(false);
+
567  wait(sc_core::SC_ZERO_TIME);
+
568  fsm_handle* fsm_hndl;
+
569  uint8_t val;
+
570  while(true) {
+
571  std::tie(val, fsm_hndl) = wresp_vl.get();
+
572  SCCTRACE(SCMOD) << "got write response of trans " << *fsm_hndl->trans;
+
573  auto ext = fsm_hndl->trans->get_extension<axi::ace_extension>();
+
574  this->b_resp.write(axi::to_int(ext->get_resp()));
+
575  this->b_valid.write(true);
+
576  if(!CFG::IS_LITE)
+
577  this->b_id->write(ext->get_id());
+
578  SCCTRACE(SCMOD) << "got write response";
+
579  do {
+
580  wait(this->b_ready.posedge_event() | clk_delayed);
+
581  if(this->b_ready.read()) {
+
582  react(axi::fsm::protocol_time_point_e::EndRespE, active_resp_beat[tlm::TLM_WRITE_COMMAND]);
+
583  }
+
584  } while(!this->b_ready.read());
+
585  SCCTRACE(SCMOD) << "finished write response of trans [" << fsm_hndl->trans << "]";
+
586  wait(clk_i.posedge_event());
+
587  this->b_valid.write(false);
+
588  }
+
589 }
+
590 
+
591 // write snoop address
+
592 template <typename CFG> inline void axi::pin::ace_target<CFG>::write_ac(tlm::tlm_generic_payload& trans) {
+
593  sc_dt::sc_uint<CFG::ADDRWIDTH> addr = trans.get_address();
+
594  this->ac_addr.write(addr);
+
595  auto ext = trans.get_extension<ace_extension>();
+
596  sc_assert(ext && "No ACE extension found for snoop access");
+
597  this->ac_prot.write(ext->get_prot());
+
598  this->ac_snoop->write(sc_dt::sc_uint<4>((uint8_t)ext->get_snoop()));
+
599 }
+
600 
+
601 template <typename CFG> inline void axi::pin::ace_target<CFG>::ac_t() {
+
602  this->ac_valid.write(false);
+
603  wait(sc_core::SC_ZERO_TIME);
+
604  while(true) {
+
605  wait(ac_evt);
+
606  this->ac_valid.write(true);
+
607  do {
+
608  wait(this->ac_ready.posedge_event() | clk_delayed);
+
609  if(this->ac_ready.read()) {
+
610  SCCTRACE(SCMOD) << "in ac_t() detect ac_ready high , schedule EndReq";
+
611  react(axi::fsm::protocol_time_point_e::EndReqE, active_req[SNOOP]);
+
612  }
+
613  } while(!this->ac_ready.read());
+
614  wait(clk_i.posedge_event());
+
615  this->ac_valid.write(false);
+
616  }
+
617 }
+
618 
+
619 template <typename CFG> inline void axi::pin::ace_target<CFG>::cd_t() {
+
620  this->cd_ready.write(false);
+
621  wait(sc_core::SC_ZERO_TIME);
+
622  while(true) {
+
623  wait(this->cd_valid.posedge_event() | clk_delayed);
+
624  if(this->cd_valid.read()) {
+
625  SCCTRACE(SCMOD) << "in cd_t(), received cd_valid high ";
+
626  wait(sc_core::SC_ZERO_TIME);
+
627  auto data = this->cd_data.read();
+
628  if(snp_resp_queue.empty())
+
629  sc_assert(" snp_resp_queue empty");
+
630  auto* fsm_hndl = snp_resp_queue.front();
+
631  auto beat_count = fsm_hndl->beat_count;
+
632  SCCTRACE(SCMOD) << "in cd_t(), received beau_count = " << fsm_hndl->beat_count;
+
633  auto size = axi::get_burst_size(*fsm_hndl->trans);
+
634  auto byte_offset = beat_count * size;
+
635  auto offset = (fsm_hndl->trans->get_address() + byte_offset) & (CFG::BUSWIDTH / 8 - 1);
+
636  if(offset && (size + offset) > (CFG::BUSWIDTH / 8)) { // un-aligned multi-beat access
+
637  if(beat_count == 0) {
+
638  auto dptr = fsm_hndl->trans->get_data_ptr();
+
639  for(size_t i = offset; i < size; ++i, ++dptr) {
+
640  auto bit_offs = i * 8;
+
641  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
642  }
+
643  } else {
+
644  auto beat_start_idx = beat_count * size - offset;
+
645  auto data_len = fsm_hndl->trans->get_data_length();
+
646  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_start_idx;
+
647  for(size_t i = offset; i < size && (beat_start_idx + i) < data_len; ++i, ++dptr) {
+
648  auto bit_offs = i * 8;
+
649  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
650  }
+
651  }
+
652  } else { // aligned or single beat access
+
653  auto dptr = fsm_hndl->trans->get_data_ptr() + beat_count * size;
+
654  for(size_t i = 0; i < size; ++i, ++dptr) {
+
655  auto bit_offs = (offset + i) * 8;
+
656  *dptr = data(bit_offs + 7, bit_offs).to_uint();
+
657  }
+
658  }
+
659  /*
+
660  axi::ace_extension* e;
+
661  fsm_hndl->trans->get_extension(e);
+
662  e->set_resp(axi::into<axi::resp_e>(resp));
+
663  e->add_to_response_array(*e);
+
664  */
+
665  auto tp = CFG::IS_LITE || this->cd_last->read() ? axi::fsm::protocol_time_point_e::BegRespE
+
666  : axi::fsm::protocol_time_point_e::BegPartRespE;
+
667  if(!this->cd_last->read()) // only react BegPartRespE
+
668  react(tp, fsm_hndl);
+
669  // cd_end_req_evt notified in EndPartRespE or EndResp
+
670  wait(cd_end_req_evt);
+
671  this->cd_ready.write(true);
+
672  wait(clk_i.posedge_event());
+
673  this->cd_ready.write(false);
+
674  }
+
675  }
+
676 }
+
677 
+
678 template <typename CFG> inline void axi::pin::ace_target<CFG>::cr_t() {
+
679  this->cr_ready.write(false);
+
680  wait(sc_core::SC_ZERO_TIME);
+
681  while(true) {
+
682  wait(this->cr_valid.posedge_event() | clk_delayed);
+
683  if(this->cr_valid.read()) {
+
684  SCCTRACE(SCMOD) << "in cr_t() received cr_valid high ";
+
685  wait(sc_core::SC_ZERO_TIME);
+
686 
+
687  auto* fsm_hndl = snp_resp_queue.front();
+
688  auto crresp = this->cr_resp.read();
+
689  axi::ace_extension* e;
+
690  fsm_hndl->trans->get_extension(e);
+
691  e->set_cresp(crresp);
+
692 
+
693  SCCTRACE(SCMOD) << " in cr_t() react() with BegRespE ";
+
694  // hongyu TBD?? schedule BegResp??
+
695  react(axi::fsm::protocol_time_point_e::BegRespE, fsm_hndl);
+
696  wait(cr_end_req_evt); // notify in EndResp
+
697  this->cr_ready.write(true);
+
698  wait(clk_i.posedge_event());
+
699  this->cr_ready.write(false);
+
700  }
+
701  }
+
702 }
+
703 
+
704 #endif /* _BUS_AXI_PIN_ACE_TARGET_H_ */
+
axi::ace_bw_transport_if
Definition: axi_tlm.h:926
+
tlm::scc::tlm_mm::allocate
payload_type * allocate()
get a plain tlm_payload_type without extensions
Definition: tlm_mm.h:228
+
tlm::scc::tlm_mm::get
static tlm_mm & get()
accessor function of the singleton
Definition: tlm_mm.h:222
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+ +
axi::to_int
constexpr ULT to_int(E t)
Definition: axi_tlm.h:47
+
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition: axi_tlm.h:1157
+
util::ilog2
CONSTEXPR unsigned ilog2(uint32_t val)
Definition: ities.h:163
+
axi::ac_ace
snoop address(AC) channel signals
Definition: signal_if.h:629
+
axi::ace_extension
Definition: axi_tlm.h:861
+
axi::ace_initiator_socket< CFG::BUSWIDTH >
+
axi::ace_response::set_cresp
void set_cresp(uint8_t)
set the coherent response status
Definition: axi_tlm.h:1531
+
axi::ace_response::get_cresp
uint8_t get_cresp() const
get the coherent response status
Definition: axi_tlm.h:1533
+
axi::ace::set_barrier
void set_barrier(bar_e)
set the AxBAR value
Definition: axi_tlm.h:1449
+
axi::ace::set_domain
void set_domain(domain_e)
set the AxDOMAIN value
Definition: axi_tlm.h:1441
+
axi::ace::set_unique
void set_unique(bool)
set the AxUNIQUE value
Definition: axi_tlm.h:1453
+
axi::ace::get_snoop
snoop_e get_snoop() const
get the AxSNOOP value return the snoop value
Definition: axi_tlm.h:1447
+
axi::ace::set_snoop
void set_snoop(snoop_e)
set the AxSNOOP value
Definition: axi_tlm.h:1445
+
axi::ar_ace
Definition: signal_if.h:488
+
axi::aw_ace
Definition: signal_if.h:550
+
axi::axi4::set_exclusive
void set_exclusive(bool=true)
get the exclusive bit of AxLOCK (AxLOCK[0])
Definition: axi_tlm.h:1324
+
axi::b_axi
Definition: signal_if.h:227
+
axi::cd_ace
snoop data(cd) channel signals
Definition: signal_if.h:658
+
axi::common::set_id
void set_id(unsigned int value)
Definition: axi_tlm.h:1252
+
axi::common::set_user
void set_user(id_type chnl, unsigned int value)
Definition: axi_tlm.h:1256
+
axi::common::get_id
unsigned int get_id() const
Definition: axi_tlm.h:1254
+
axi::cr_ace
snoop response(cr) channel signals
Definition: signal_if.h:680
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
axi::pin::ace_target
Definition: ace_target.h:48
+
axi::request::set_length
void set_length(uint8_t)
set the AxLEN value of the transaction, the value denotes the burst length - 1
Definition: axi_tlm.h:1380
+
axi::request::set_qos
void set_qos(uint8_t)
set the AxQOS (quality of service) value
Definition: axi_tlm.h:1426
+
axi::request::set_cache
void set_cache(uint8_t)
set the AxCACHE value as POD, only value from 0..15 are allowed
Definition: axi_tlm.h:1434
+
axi::request::set_region
void set_region(uint8_t)
set the AxREGION value
Definition: axi_tlm.h:1430
+
axi::request::set_burst
void set_burst(burst_e)
set the AxBURST value,
Definition: axi_tlm.h:1391
+
axi::request::set_size
void set_size(uint8_t)
get the AxSIZE value of the transaction, the length is 2^size. It needs to be less than 10 (512 bit w...
Definition: axi_tlm.h:1384
+
axi::request::get_prot
uint8_t get_prot() const
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1400
+
axi::request::set_prot
void set_prot(uint8_t)
set the AxPROT value as POD, only values from 0...7 are allowed
Definition: axi_tlm.h:1395
+
axi::response::get_resp
resp_e get_resp() const
get the response status as POD
Definition: axi_tlm.h:1502
+
axi::rresp_ace
Definition: signal_if.h:344
+
axi::wdata_axi
Definition: signal_if.h:186
+ +
+
+ + + + diff --git a/main/ace__target__pe_8cpp_source.html b/main/ace__target__pe_8cpp_source.html new file mode 100644 index 00000000..7c8842d6 --- /dev/null +++ b/main/ace__target__pe_8cpp_source.html @@ -0,0 +1,286 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/ace_target_pe.cpp Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target_pe.cpp
+
+
+
1 /*
+
2  * Copyright 2020 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #ifndef SC_INCLUDE_DYNAMIC_PROCESSES
+
18 #define SC_INCLUDE_DYNAMIC_PROCESSES
+
19 #endif
+
20 
+
21 #include <axi/pe/ace_target_pe.h>
+
22 #include <axi/fsm/protocol_fsm.h>
+
23 #include <axi/fsm/types.h>
+
24 #include <scc/report.h>
+
25 #include <scc/utilities.h>
+
26 #include <systemc>
+
27 #include <tuple>
+
28 
+
29 using namespace sc_core;
+
30 using namespace tlm;
+
31 using namespace axi;
+
32 using namespace axi::fsm;
+
33 using namespace axi::pe;
+
34 
+
35 /******************************************************************************
+
36  * target
+
37  ******************************************************************************/
+
38 struct ace_target_pe::bw_intor_impl : public tlm::scc::pe::intor_bw_nb {
+
39  ace_target_pe* const that;
+
40  bw_intor_impl(ace_target_pe* that)
+
41  : that(that) {}
+
42  unsigned transport(tlm::tlm_generic_payload& payload) override {
+
43  if((payload.is_read() && that->rd_resp_fifo.num_free())){
+
44  that->rd_resp_fifo.write(&payload);
+
45  return 0;
+
46  } else if((payload.is_write() && that->wr_resp_fifo.num_free())){
+
47  that->wr_resp_fifo.write(&payload);
+
48  return 0;
+
49  }
+
50  return std::numeric_limits<unsigned>::max();
+
51  }
+
52 };
+
53 
+
54 SC_HAS_PROCESS(ace_target_pe);
+
55 
+
56 ace_target_pe::ace_target_pe(const sc_core::sc_module_name& nm, size_t transfer_width)
+
57 : sc_module(nm)
+
58 , base(transfer_width, true) // coherent true
+
59 , bw_intor(new bw_intor_impl(this)) {
+
60  isckt_axi.bind(*this);
+
61  instance_name = name();
+
62 
+
63  add_attribute(rd_resp_delay);
+
64  add_attribute(wr_resp_delay);
+
65  bw_i.bind(*bw_intor);
+
66 
+
67  SC_METHOD(fsm_clk_method);
+
68  dont_initialize();
+
69  sensitive << clk_i.pos();
+
70 }
+
71 
+
72 ace_target_pe::~ace_target_pe() = default;
+
73 
+
74 void ace_target_pe::end_of_elaboration() {
+
75  clk_if = dynamic_cast<sc_core::sc_clock*>(clk_i.get_interface());
+
76 }
+
77 
+
78 void ace_target_pe::start_of_simulation() {
+
79  if (!socket_bw)
+
80  SCCFATAL(SCMOD) << "No backward interface registered!";
+
81 }
+
82 
+
83 
+
84 void ace_target_pe::b_transport(payload_type& trans, sc_time& t) {
+
85  auto latency = operation_cb ? operation_cb(trans) : trans.is_read() ? rd_resp_delay.get_value() : wr_resp_delay.get_value();
+
86  trans.set_dmi_allowed(false);
+
87  trans.set_response_status(tlm::TLM_OK_RESPONSE);
+
88  if(clk_if)
+
89  t += clk_if->period() * latency;
+
90 }
+
91 
+
92 tlm_sync_enum ace_target_pe::nb_transport_fw(payload_type& trans, phase_type& phase, sc_time& t) {
+
93  SCCTRACE(SCMOD)<<"in nb_transport_fw receives pahse " << phase;
+
94  auto ret = TLM_ACCEPTED;
+
95  if( phase == END_REQ) { // snoop
+
96  schedule(phase == END_REQ ? EndReqE : EndPartReqE, &trans, t, false);
+
97  } else if(phase == BEGIN_PARTIAL_RESP || phase == BEGIN_RESP) { // snoop response
+
98  schedule(phase == BEGIN_RESP ? BegRespE : BegPartRespE, &trans, t, false);
+
99  } else { // forward read/Write
+
100  if(phase==axi::ACK)
+
101  return tlm::TLM_COMPLETED;
+
102  SCCTRACE(SCMOD) << " forward via axi_i_sckt, in nb_transport_fw () with phase "<<phase ;
+
103  return isckt_axi->nb_transport_fw(trans, phase, t);
+
104  }
+
105  return ret;
+
106 }
+
107 
+
108 bool ace_target_pe::get_direct_mem_ptr(payload_type& trans, tlm_dmi& dmi_data) {
+
109  trans.set_dmi_allowed(false);
+
110  return false;
+
111 }
+
112 
+
113 unsigned int ace_target_pe::transport_dbg(payload_type& trans) { return 0; }
+
114 
+
115 fsm_handle* ace_target_pe::create_fsm_handle() { return new fsm_handle(); }
+
116 
+
117 void ace_target_pe::setup_callbacks(fsm_handle* fsm_hndl) {
+
118  fsm_hndl->fsm->cb[RequestPhaseBeg] = [this, fsm_hndl]() -> void {
+
119  fsm_hndl->beat_count = 0;
+
120  outstanding_cnt[fsm_hndl->trans->get_command()]++;
+
121  };
+
122  fsm_hndl->fsm->cb[BegPartReqE] = [this, fsm_hndl]() -> void {
+
123  // for snoop, state will not receive this event
+
124  };
+
125  fsm_hndl->fsm->cb[EndPartReqE] = [this, fsm_hndl]() -> void {
+
126  // for snoop, state will not receive this event
+
127  };
+
128  fsm_hndl->fsm->cb[BegReqE] = [this, fsm_hndl]() -> void {
+
129  SCCTRACE(SCMOD)<< "in BegReq of setup_cb";
+
130  if(fsm_hndl->is_snoop) {
+
131  sc_time t;
+
132  tlm::tlm_phase phase = tlm::BEGIN_REQ;
+
133  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
134  }
+
135  };
+
136  fsm_hndl->fsm->cb[EndReqE] = [this, fsm_hndl]() -> void {
+
137  SCCTRACE(SCMOD)<<" EndReqE in setup_cb";
+
138  };
+
139  fsm_hndl->fsm->cb[BegPartRespE] = [this, fsm_hndl]() -> void {
+
140  SCCTRACE(SCMOD) <<"in BegPartRespE of setup_cb, ";
+
141  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
142  schedule(EndPartRespE, fsm_hndl->trans, t);
+
143  };
+
144  fsm_hndl->fsm->cb[EndPartRespE] = [this, fsm_hndl]() -> void {
+
145  SCCTRACE(SCMOD) <<"in EndPartRespE of setup_cb";
+
146  //sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
147  sc_time t(SC_ZERO_TIME);
+
148  tlm::tlm_phase phase = axi::END_PARTIAL_RESP;
+
149  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
150  fsm_hndl->beat_count++;
+
151  };
+
152  fsm_hndl->fsm->cb[BegRespE] = [this, fsm_hndl]() -> void {
+
153  SCCTRACE(SCMOD) <<"in BegRespE of setup_cb";
+
154  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
155  tlm::tlm_phase phase = tlm::END_RESP;
+
156  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
157  t=::scc::time_to_next_posedge(clk_if);
+
158  /* here *3 because after send() of intiator ,there is one cycle wait
+
159  * target here need to wait long cycles so that gp_shared_ptr can be released
+
160  */
+
161  schedule(EndRespE, fsm_hndl->trans, 3*t);
+
162  };
+
163  fsm_hndl->fsm->cb[EndRespE] = [this, fsm_hndl]() -> void {
+
164  /*
+
165  sc_time t(clk_if ? ::scc::time_to_next_posedge(clk_if) - 1_ps : SC_ZERO_TIME);
+
166  tlm::tlm_phase phase = tlm::END_RESP;
+
167  auto ret = socket_bw->nb_transport_bw(*fsm_hndl->trans, phase, t);
+
168  */
+
169  SCCTRACE(SCMOD)<< "notifying finish ";
+
170  fsm_hndl->finish.notify();
+
171  };
+
172  /*TBD threre is ack for snoop_trans
+
173  * */
+
174 }
+
175 
+
176 void ace_target_pe::snoop(payload_type& trans) {
+
177  SCCTRACE(SCMOD) << "got transport snoop trans ";
+
178  bool ace= true;
+
179  fsm_handle* fsm = find_or_create(&trans,true);
+
180  fsm->is_snoop = true;
+
181  react(RequestPhaseBeg, fsm->trans); //
+
182  SCCTRACE(SCMOD) << "started non-blocking protocol";
+
183  sc_core::wait(fsm->finish);
+
184  SCCTRACE(SCMOD) << "finished non-blocking protocol";
+
185 }
+
186 
+
187 
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::ace_target_pe::create_fsm_handle
fsm::fsm_handle * create_fsm_handle() override
Definition: ace_target_pe.cpp:115
+
axi::pe::ace_target_pe::wr_resp_delay
scc::sc_attribute_randomized< int > wr_resp_delay
the latency between request and response phase. Will be overwritten by the return of the callback fun...
Definition: ace_target_pe.h:66
+
axi::pe::ace_target_pe::setup_callbacks
void setup_callbacks(fsm::fsm_handle *) override
Definition: ace_target_pe.cpp:117
+
axi::pe
protocol engine implementations
Definition: ace_target_pe.h:37
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
tlm
SystemC TLM.
Definition: initiator_mixin.h:26
+
axi::pe::ace_target_pe::bw_intor_impl
Definition: ace_target_pe.cpp:38
+
axi::pe::ace_target_pe::bw_intor_impl::transport
unsigned transport(tlm::tlm_generic_payload &payload) override
Definition: ace_target_pe.cpp:42
+ +
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::react
void react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
triggers the FSM with event and given transaction
Definition: base.h:134
+
axi::fsm::base::schedule
void schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling...
Definition: base.h:107
+
axi::fsm::base::find_or_create
axi::fsm::fsm_handle * find_or_create(payload_type *gp=nullptr, bool ace=false)
retrieve the FSM handle based on the transaction passed. If non exist one will be created
Definition: base.cpp:65
+
axi::fsm::fsm_handle
Definition: types.h:58
+
axi::fsm::fsm_handle::trans
tlm::scc::tlm_gp_shared_ptr trans
pointer to the associated AXITLM payload
Definition: types.h:62
+
axi::fsm::fsm_handle::finish
sc_core::sc_event finish
event indicating the end of the transaction
Definition: types.h:68
+
axi::fsm::fsm_handle::beat_count
size_t beat_count
beat count of this transaction
Definition: types.h:64
+
axi::fsm::fsm_handle::fsm
AxiProtocolFsm *const fsm
pointer to the FSM
Definition: types.h:60
+
axi::fsm::fsm_handle::is_snoop
bool is_snoop
indicator if this is a snoop access
Definition: types.h:66
+
tlm::scc::pe::intor_bw_nb
Definition: intor_if.h:64
+
+
+ + + + diff --git a/main/ace__target__pe_8h_source.html b/main/ace__target__pe_8h_source.html new file mode 100644 index 00000000..000aa57b --- /dev/null +++ b/main/ace__target__pe_8h_source.html @@ -0,0 +1,227 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/ace_target_pe.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ace_target_pe.h
+
+
+
1 /*
+
2  * Copyright 2020-2022 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #pragma once
+
18 
+
19 #ifndef SC_INCLUDE_DYNAMIC_PROCESSES
+
20 #define SC_INCLUDE_DYNAMIC_PROCESSES
+
21 #endif
+
22 
+
23 #include <array>
+
24 #include <axi/fsm/base.h>
+
25 #include <functional>
+
26 #include <memory>
+
27 #include <scc/ordered_semaphore.h>
+
28 #include <scc/sc_attribute_randomized.h>
+
29 #include <scc/sc_variable.h>
+
30 #include <tlm/scc/pe/intor_if.h>
+
31 #include <tlm_utils/peq_with_cb_and_phase.h>
+
32 #include <unordered_set>
+
33 
+
35 namespace axi {
+
37 namespace pe {
+
41 class ace_target_pe : public sc_core::sc_module,
+
42  protected axi::fsm::base,
+
43  public axi::axi_bw_transport_if<axi::axi_protocol_types>,
+
44  public axi::ace_fw_transport_if<axi::axi_protocol_types> {
+
45  struct bw_intor_impl;
+
46 public:
+
47 
+
48  using payload_type = axi::axi_protocol_types::tlm_payload_type;
+
49  using phase_type = axi::axi_protocol_types::tlm_phase_type;
+
50 
+
51  sc_core::sc_in<bool> clk_i{"clk_i"};
+
52 
+
53  // hongyu?? here first hardcoded
+
54  axi::axi_initiator_socket<64> isckt_axi{"isckt_axi"};
+
55 
+
56  sc_core::sc_port<tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND> fw_o{"fw_o"};
+
57 
+
58  sc_core::sc_export<tlm::scc::pe::intor_bw_nb> bw_i{"bw_i"};
+
59 
+
60 
+
61  scc::sc_attribute_randomized<int> rd_resp_delay{"rd_resp_delay", 0};
+
66  scc::sc_attribute_randomized<int> wr_resp_delay{"wr_resp_delay", 0};
+
67 
+
68  void b_transport(payload_type& trans, sc_core::sc_time& t) override;
+
69 
+
70  tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
+
71 
+
72  bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override;
+
73 
+
74  unsigned int transport_dbg(payload_type& trans) override;
+
85  void set_operation_cb(std::function<unsigned(payload_type& trans)> cb) { operation_cb = cb; }
+
92  void operation_resp(payload_type& trans, unsigned clk_delay = 0);
+
98  bool is_active() { return !active_fsm.empty(); }
+
104  const sc_core::sc_event& tx_finish_event() { return finish_evt; }
+
105 
+
106  /* overwrite function, defined in axi_bw_transport_if */
+
107  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override {
+
108  SCCTRACE(SCMOD) << " in nb_transport_bw () " ;
+
109  return socket_bw->nb_transport_bw(trans, phase, t);
+
110  }
+
111 
+
112  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override {}
+
113 
+
114 
+
115  ~ace_target_pe();
+
116 
+
122  explicit ace_target_pe(const sc_core::sc_module_name& nm, size_t transfer_width);
+
123 
+
124  void set_bw_interface(axi::axi_bw_transport_if<axi_protocol_types>* ifs) {socket_bw=ifs;}
+
125 
+
126  void snoop(payload_type& trans);
+
127 
+
128 protected:
+
129  ace_target_pe() = delete;
+
130 
+
131  ace_target_pe(ace_target_pe const&) = delete;
+
132 
+
133  ace_target_pe(ace_target_pe&&) = delete;
+
134 
+
135  ace_target_pe& operator=(ace_target_pe const&) = delete;
+
136 
+
137  ace_target_pe& operator=(ace_target_pe&&) = delete;
+
138 
+
139  void end_of_elaboration() override;
+
140 
+
141  void start_of_simulation() override;
+
142 
+
143  void fsm_clk_method() { process_fsm_clk_queue(); }
+
147  fsm::fsm_handle* create_fsm_handle() override;
+
151  void setup_callbacks(fsm::fsm_handle*) override;
+
152 
+
153  unsigned operations_callback(payload_type& trans);
+
154 
+
155  axi::axi_bw_transport_if<axi_protocol_types>* socket_bw{nullptr};
+
156  std::function<unsigned(payload_type& trans)> operation_cb;
+
157  sc_core::sc_fifo<payload_type*> rd_resp_fifo{1}, wr_resp_fifo{1};
+
158 
+
159  sc_core::sc_fifo<std::tuple<fsm::fsm_handle*, axi::fsm::protocol_time_point_e>> wr_resp_beat_fifo{128},
+
160  rd_resp_beat_fifo{128};
+
161  scc::ordered_semaphore rd_resp{1}, wr_resp_ch{1}, rd_resp_ch{1};
+
162 
+
163  sc_core::sc_clock* clk_if{nullptr};
+
164  std::unique_ptr<bw_intor_impl> bw_intor;
+
165  std::array<unsigned, 3> outstanding_cnt{{0, 0, 0}}; // count for limiting
+
166 
+
167  void nb_fw(payload_type& trans, const phase_type& phase) {
+
168  auto delay = sc_core::SC_ZERO_TIME;
+
169  base::nb_fw(trans, phase, delay);
+
170  }
+
171  tlm_utils::peq_with_cb_and_phase<ace_target_pe> fw_peq{this, &ace_target_pe::nb_fw};
+
172  std::unordered_set<unsigned> active_rdresp_id;
+
173 
+
174 };
+
175 
+
176 } // namespace pe
+
177 } // namespace axi
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::ace_target_pe::operation_resp
void operation_resp(payload_type &trans, unsigned clk_delay=0)
+
axi::pe::ace_target_pe::create_fsm_handle
fsm::fsm_handle * create_fsm_handle() override
Definition: ace_target_pe.cpp:115
+
axi::pe::ace_target_pe::wr_resp_delay
scc::sc_attribute_randomized< int > wr_resp_delay
the latency between request and response phase. Will be overwritten by the return of the callback fun...
Definition: ace_target_pe.h:66
+
axi::pe::ace_target_pe::set_operation_cb
void set_operation_cb(std::function< unsigned(payload_type &trans)> cb)
Set the operation callback function.
Definition: ace_target_pe.h:85
+
axi::pe::ace_target_pe::ace_target_pe
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)
Definition: ace_target_pe.cpp:56
+
axi::pe::ace_target_pe::setup_callbacks
void setup_callbacks(fsm::fsm_handle *) override
Definition: ace_target_pe.cpp:117
+
axi::pe::ace_target_pe::tx_finish_event
const sc_core::sc_event & tx_finish_event()
Definition: ace_target_pe.h:104
+
axi::pe::ace_target_pe::is_active
bool is_active()
Definition: ace_target_pe.h:98
+
scc::ordered_semaphore
The ordered_semaphore primitive channel class.
Definition: ordered_semaphore.h:44
+
scc::sc_attribute_randomized< int >
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::axi_bw_transport_if
tlm::tlm_bw_transport_if< TYPES > axi_bw_transport_if
alias declaration for the backward interface:
Definition: axi_tlm.h:918
+
axi::ace_fw_transport_if
tlm::tlm_fw_transport_if< TYPES > ace_fw_transport_if
alias declaration for the ACE forward interface
Definition: axi_tlm.h:920
+
axi::pe::ace_target_pe::bw_intor_impl
Definition: ace_target_pe.cpp:38
+
axi::axi_initiator_socket< 64 >
+
axi::fsm::base
base class of all AXITLM based adapters and interfaces.
Definition: base.h:43
+
axi::fsm::base::process_fsm_clk_queue
void process_fsm_clk_queue()
processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clo...
Definition: base.cpp:107
+
+
+ + + + diff --git a/main/ahb__tlm_8cpp_source.html b/main/ahb__tlm_8cpp_source.html new file mode 100644 index 00000000..abde5869 --- /dev/null +++ b/main/ahb__tlm_8cpp_source.html @@ -0,0 +1,155 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/bus_interfaces/ahb/ahb_tlm.cpp Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
ahb_tlm.cpp
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2019-2023 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 
+
17 #include "ahb_tlm.h"
+
18 
+
19 namespace ahb {
+
20 namespace {
+
21 const std::array<std::string, 3> cmd_str{"R", "W", "I"};
+
22 }
+
23 template <> const char* to_char<burst_e>(burst_e v) {
+
24  switch(v) {
+
25  case burst_e::SINGLE:
+
26  return "SINGLE";
+
27  case burst_e::INCR:
+
28  return "INCR";
+
29  case burst_e::INCR4:
+
30  return "INCR4";
+
31  case burst_e::INCR8:
+
32  return "INCR8";
+
33  case burst_e::INCR16:
+
34  return "INCR16";
+
35  case burst_e::WRAP4:
+
36  return "WRAP4";
+
37  case burst_e::WRAP8:
+
38  return "WRAP8";
+
39  case burst_e::WRAP16:
+
40  return "WRAP16";
+
41  default:
+
42  return "UNKNOWN";
+
43  }
+
44 }
+
45 
+
46 template <> const char* to_char<resp_e>(resp_e v) {
+
47  switch(v) {
+
48  case resp_e::OKAY:
+
49  return "OKAY";
+
50  case resp_e::EXOKAY:
+
51  return "EXOKAY";
+
52  case resp_e::DECERR:
+
53  return "DECERR";
+
54  case resp_e::SLVERR:
+
55  return "SLVERR";
+
56  default:
+
57  return "UNKNOWN";
+
58  }
+
59 }
+
60 
+
61 std::ostream& operator<<(std::ostream& os, const tlm::tlm_generic_payload& t) {
+
62  os << "CMD:" << cmd_str[t.get_command()] << ", "
+
63  << "ADDR:0x" << std::hex << t.get_address() << ", TXLEN:0x" << t.get_data_length();
+
64  if(auto e = t.get_extension<ahb::ahb_extension>()) {
+
65  os << ", "
+
66  << "BURST:" << to_char(e->get_burst()) << ", " << (e->is_seq() ? "SEQ" : "NONSEQ") << ", "
+
67  << "MSTLOCK:" << e->is_locked() << ", "
+
68  << "PROT:0x" << std::hex << static_cast<unsigned>(e->get_protection());
+
69  }
+
70  os << " [ptr:" << &t << "]";
+
71  return os;
+
72 }
+
73 
+
74 } // namespace ahb
+
ahb
TLM2.0 components modeling AHB.
Definition: ahb_tlm.cpp:19
+
ahb::to_char
const char * to_char(E t)
+
ahb::ahb_extension
Definition: ahb_tlm.h:75
+
+
+ + + + diff --git a/main/cci__param__restricted_8h_source.html b/main/cci__param__restricted_8h_source.html new file mode 100644 index 00000000..52148620 --- /dev/null +++ b/main/cci__param__restricted_8h_source.html @@ -0,0 +1,225 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/sysc/scc/cci_param_restricted.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
cci_param_restricted.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2024 MINRES Technologies GmbH
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.
+
15  *******************************************************************************/
+
16 #ifndef _SCC_CCI_PARAM_RESTRICTED_H_
+
17 #define _SCC_CCI_PARAM_RESTRICTED_H_
+
18 
+
19 #include <cci_cfg/cci_param_typed.h>
+
20 #include <unordered_set>
+
21 
+
22 namespace scc {
+
23 template <typename T> struct _min_max_restriction {
+
24  _min_max_restriction(T min, T max)
+
25  : min(min)
+
26  , max(max) {}
+
27 
+
28  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value >= min && ev.new_value <= max; }
+
29  T const min;
+
30  T const max;
+
31 };
+
32 
+
33 template <typename T> struct _min_max_excl_restriction {
+
34  _min_max_excl_restriction(T min, T max)
+
35  : min(min)
+
36  , max(max) {}
+
37 
+
38  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value > min && ev.new_value < max; }
+
39  T const min;
+
40  T const max;
+
41 };
+
42 
+
43 template <typename T> struct _min_restriction {
+
44  _min_restriction(T min)
+
45  : min(min) {}
+
46 
+
47  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value >= min; }
+
48  T const min;
+
49 };
+
50 
+
51 template <typename T> struct _min_excl_restriction {
+
52  _min_excl_restriction(T min)
+
53  : min(min) {}
+
54 
+
55  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value > min; }
+
56  T const min;
+
57 };
+
58 
+
59 template <typename T> struct _max_restriction {
+
60  _max_restriction(T max)
+
61  : max(max) {}
+
62 
+
63  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value <= max; }
+
64  T const max;
+
65 };
+
66 
+
67 template <typename T> struct _max_excl_restriction {
+
68  _max_excl_restriction(T max)
+
69  : max(max) {}
+
70 
+
71  bool operator()(cci::cci_param_write_event<T> const& ev) const { return ev.new_value < max; }
+
72  T const max;
+
73 };
+
74 
+
75 template <typename T> struct _discrete_restriction {
+
76  template <typename COLLECTION_TYPE>
+
77  _discrete_restriction(COLLECTION_TYPE values)
+
78  : values(std::begin(values), std::end(values)) {}
+
79 
+
80  bool operator()(cci::cci_param_write_event<T> const& ev) const { return values.count(ev.new_value) > 0; }
+
81  std::unordered_set<T> const values;
+
82 };
+
91 template <typename T> inline _min_max_restriction<T> min_max_restriction(T min, T max) { return _min_max_restriction<T>(min, max); }
+
100 template <typename T> inline _min_max_excl_restriction<T> min_max_excl_restriction(T min, T max) {
+
101  return _min_max_excl_restriction<T>(min, max);
+
102 }
+
110 template <typename T> inline _min_restriction<T> min_restriction(T min) { return _min_restriction<T>(min); }
+
112 template <typename T> inline _min_restriction<T> gte_restriction(T min) { return _min_restriction<T>(min); }
+
120 template <typename T> inline _min_excl_restriction<T> min_excl_restriction(T min) { return _min_excl_restriction<T>(min); }
+
122 template <typename T> inline _min_excl_restriction<T> gt_excl_restriction(T min) { return _min_excl_restriction<T>(min); }
+
130 template <typename T> inline _max_restriction<T> max_restriction(T max) { return _max_restriction<T>(max); }
+
132 template <typename T> inline _max_restriction<T> lte_restriction(T max) { return _max_restriction<T>(max); }
+
140 template <typename T> inline _max_excl_restriction<T> max_excl_restriction(T max) { return _max_excl_restriction<T>(max); }
+
142 template <typename T> inline _max_excl_restriction<T> lt_excl_restriction(T max) { return _max_excl_restriction<T>(max); }
+
150 template <typename T> inline _discrete_restriction<T> discrete_restriction(std::initializer_list<T> values) {
+
151  return _discrete_restriction<T>(values);
+
152 }
+
161 template <typename T, size_t SZ> inline _discrete_restriction<T> discrete_restriction(std::array<T, SZ> values) {
+
162  return _discrete_restriction<T>(values);
+
163 }
+
171 template <typename T> inline _discrete_restriction<T> discrete_restriction(std::vector<T> values) {
+
172  return _discrete_restriction<T>(values);
+
173 }
+
180 template <typename T, cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM> struct cci_param_restricted : public cci::cci_param<T, TM> {
+
181 
+
195  template <typename RESTR>
+
196  cci_param_restricted(const std::string& name, const T& default_value, RESTR const& restr, const std::string& desc = "",
+
197  cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
+
198  const cci::cci_originator& originator = cci::cci_originator())
+
199  : cci::cci_param<T, TM>(name, default_value, desc, name_type, originator) {
+
200  this->template register_pre_write_callback(restr);
+
201  this->template reset();
+
202  }
+
203 
+
216  template <typename RESTR>
+
217  cci_param_restricted(const std::string& name, const T& default_value, RESTR const& restr, cci::cci_broker_handle private_broker,
+
218  const std::string& desc = "", cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
+
219  const cci::cci_originator& originator = cci::cci_originator())
+
220  : cci::cci_param<T, TM>(name, default_value, desc, name_type, originator) {
+
221  this->template register_pre_write_callback(restr);
+
222  this->template reset();
+
223  }
+
225 };
+
226 } // namespace scc
+
227 #endif /* _SCC_CCI_PARAM_RESTRICTED_H_ */
+
scc
SCC SystemC utilities.
Definition: clock_if_mixins.h:25
+
scc::max_excl_restriction
_max_excl_restriction< T > max_excl_restriction(T max)
creates a maximum restriction excluding the maximum value
Definition: cci_param_restricted.h:140
+
scc::max_restriction
_max_restriction< T > max_restriction(T max)
creates a maximum restriction including the maximum value
Definition: cci_param_restricted.h:130
+
scc::gte_restriction
_min_restriction< T > gte_restriction(T min)
alias for min_restriction(T min)
Definition: cci_param_restricted.h:112
+
scc::min_max_restriction
_min_max_restriction< T > min_max_restriction(T min, T max)
creates a min/max restriction with including the limits
Definition: cci_param_restricted.h:91
+
scc::gt_excl_restriction
_min_excl_restriction< T > gt_excl_restriction(T min)
alias for min_excl_restriction(T min)
Definition: cci_param_restricted.h:122
+
scc::discrete_restriction
_discrete_restriction< T > discrete_restriction(std::initializer_list< T > values)
creates a restriction for a discrete values set
Definition: cci_param_restricted.h:150
+
scc::min_restriction
_min_restriction< T > min_restriction(T min)
creates a minimum restriction including the minimum value
Definition: cci_param_restricted.h:110
+
scc::min_excl_restriction
_min_excl_restriction< T > min_excl_restriction(T min)
creates a minimum restriction excluding the minimum value
Definition: cci_param_restricted.h:120
+
scc::lt_excl_restriction
_max_excl_restriction< T > lt_excl_restriction(T max)
alias for max_excl_restriction(T max)
Definition: cci_param_restricted.h:142
+
scc::lte_restriction
_max_restriction< T > lte_restriction(T max)
alias for max_restriction(T max)
Definition: cci_param_restricted.h:132
+
scc::min_max_excl_restriction
_min_max_excl_restriction< T > min_max_excl_restriction(T min, T max)
creates a min/max restriction with excluding the limits
Definition: cci_param_restricted.h:100
+
scc::_discrete_restriction
Definition: cci_param_restricted.h:75
+
scc::_max_excl_restriction
Definition: cci_param_restricted.h:67
+
scc::_max_restriction
Definition: cci_param_restricted.h:59
+
scc::_min_excl_restriction
Definition: cci_param_restricted.h:51
+
scc::_min_max_excl_restriction
Definition: cci_param_restricted.h:33
+
scc::_min_max_restriction
Definition: cci_param_restricted.h:23
+
scc::_min_restriction
Definition: cci_param_restricted.h:43
+
scc::cci_param_restricted
extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values ...
Definition: cci_param_restricted.h:180
+
scc::cci_param_restricted::cci_param_restricted
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
Definition: cci_param_restricted.h:196
+
scc::cci_param_restricted::cci_param_restricted
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
Definition: cci_param_restricted.h:217
+
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1ace__target__pe-members.html b/main/classaxi_1_1pe_1_1ace__target__pe-members.html new file mode 100644 index 00000000..be21b741 --- /dev/null +++ b/main/classaxi_1_1pe_1_1ace__target__pe-members.html @@ -0,0 +1,153 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::pe::ace_target_pe Member List
+
+
+ +

This is the complete list of members for axi::pe::ace_target_pe, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)axi::pe::ace_target_peexplicit
ace_target_pe()=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
active_rdresp_id (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
b_transport(payload_type &trans, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bw_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
bw_intor (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
clk_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
clk_if (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
create_fsm_handle() overrideaxi::pe::ace_target_peprotectedvirtual
end_of_elaboration() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_method() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fw_o (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
fw_peq (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
get_direct_mem_ptr(payload_type &trans, tlm::tlm_dmi &dmi_data) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
is_active()axi::pe::ace_target_peinline
isckt_axi (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, const phase_type &phase) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_transport_bw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
nb_transport_fw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
operation_cb (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operation_resp(payload_type &trans, unsigned clk_delay=0)axi::pe::ace_target_pe
operations_callback(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
outstanding_cnt (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
payload_type typedef (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
phase_type typedef (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
rd_resp (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_delay (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
rd_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
set_bw_interface(axi::axi_bw_transport_if< axi_protocol_types > *ifs) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
set_operation_cb(std::function< unsigned(payload_type &trans)> cb)axi::pe::ace_target_peinline
setup_callbacks(fsm::fsm_handle *) overrideaxi::pe::ace_target_peprotectedvirtual
snoop(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
socket_bw (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
start_of_simulation() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
transport_dbg(payload_type &trans) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
tx_finish_event()axi::pe::ace_target_peinline
wr_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_delayaxi::pe::ace_target_pe
wr_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~ace_target_pe() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1ace__target__pe.html b/main/classaxi_1_1pe_1_1ace__target__pe.html new file mode 100644 index 00000000..2fa5a71f --- /dev/null +++ b/main/classaxi_1_1pe_1_1ace__target__pe.html @@ -0,0 +1,618 @@ + + + + + + + +scc: axi::pe::ace_target_pe Class Reference + + + + + + + + + + + +
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+Classes | +Public Types | +Public Member Functions | +Public Attributes | +Protected Member Functions | +Protected Attributes | +List of all members
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axi::pe::ace_target_pe Class Reference
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#include <ace_target_pe.h>

+
+Inheritance diagram for axi::pe::ace_target_pe:
+
+
Inheritance graph
+ + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::ace_target_pe:
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+ + + + +

+Classes

struct  bw_intor_impl
 
+ + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+void b_transport (payload_type &trans, sc_core::sc_time &t) override
 
+tlm::tlm_sync_enum nb_transport_fw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+bool get_direct_mem_ptr (payload_type &trans, tlm::tlm_dmi &dmi_data) override
 
+unsigned int transport_dbg (payload_type &trans) override
 
void set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
 Set the operation callback function. More...
 
void operation_resp (payload_type &trans, unsigned clk_delay=0)
 
bool is_active ()
 
const sc_core::sc_event & tx_finish_event ()
 
+tlm::tlm_sync_enum nb_transport_bw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+void invalidate_direct_mem_ptr (sc_dt::uint64 start_range, sc_dt::uint64 end_range) override
 
 ace_target_pe (const sc_core::sc_module_name &nm, size_t transfer_width)
 
+void set_bw_interface (axi::axi_bw_transport_if< axi_protocol_types > *ifs)
 
+void snoop (payload_type &trans)
 
+ + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< 64 > isckt_axi {"isckt_axi"}
 
+sc_core::sc_port< tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND > fw_o {"fw_o"}
 
+sc_core::sc_export< tlm::scc::pe::intor_bw_nb > bw_i {"bw_i"}
 
+scc::sc_attribute_randomized< int > rd_resp_delay {"rd_resp_delay", 0}
 
+scc::sc_attribute_randomized< int > wr_resp_delay {"wr_resp_delay", 0}
 the latency between request and response phase. Will be overwritten by the return of the callback function (if registered) -> BV
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Member Functions

+ ace_target_pe (ace_target_pe const &)=delete
 
+ ace_target_pe (ace_target_pe &&)=delete
 
+ace_target_pe & operator= (ace_target_pe const &)=delete
 
+ace_target_pe & operator= (ace_target_pe &&)=delete
 
+void end_of_elaboration () override
 
+void start_of_simulation () override
 
+void fsm_clk_method ()
 
fsm::fsm_handle * create_fsm_handle () override
 
void setup_callbacks (fsm::fsm_handle *) override
 
+unsigned operations_callback (payload_type &trans)
 
+void nb_fw (payload_type &trans, const phase_type &phase)
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Attributes

+axi::axi_bw_transport_if< axi_protocol_types > * socket_bw {nullptr}
 
+std::function< unsigned(payload_type &trans)> operation_cb
 
+sc_core::sc_fifo< payload_type * > rd_resp_fifo {1}
 
+sc_core::sc_fifo< payload_type * > wr_resp_fifo {1}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > wr_resp_beat_fifo {128}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > rd_resp_beat_fifo {128}
 
+scc::ordered_semaphore rd_resp {1}
 
+scc::ordered_semaphore wr_resp_ch {1}
 
+scc::ordered_semaphore rd_resp_ch {1}
 
+sc_core::sc_clock * clk_if {nullptr}
 
+std::unique_ptr< bw_intor_impl > bw_intor
 
+std::array< unsigned, 3 > outstanding_cnt {{0, 0, 0}}
 
+tlm_utils::peq_with_cb_and_phase< ace_target_pe > fw_peq {this, &ace_target_pe::nb_fw}
 
+std::unordered_set< unsigned > active_rdresp_id
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+ + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+

Detailed Description

+

the target protocol engine base class

+ +

Definition at line 41 of file ace_target_pe.h.

+

Constructor & Destructor Documentation

+ +

◆ ace_target_pe()

+ +
+
+ + + + + +
+ + + + + + + + + + + + + + + + + + +
ace_target_pe::ace_target_pe (const sc_core::sc_module_name & nm,
size_t transfer_width 
)
+ 		+explicit
+
+

the constructor. Protected as it should only be called by derived classes

Parameters
+ + + +
port
transfer_width
+
+
+ +

Definition at line 56 of file ace_target_pe.cpp.

+ +
+
+

Member Function Documentation

+ +

◆ create_fsm_handle()

+ +
+
+ + + + + +
+ + + + + + + +
fsm_handle * ace_target_pe::create_fsm_handle ()
+ 		+overrideprotectedvirtual
+
+
See also
base::create_fsm_handle()
+ +

Implements axi::fsm::base.

+ +

Definition at line 115 of file ace_target_pe.cpp.

+ +
+
+ +

◆ is_active()

+ +
+
+ + + + + +
+ + + + + + + +
bool axi::pe::ace_target_pe::is_active ()
+ 		+inline
+
+

returns true if any transaction is still in flight

+
Returns
+ +

Definition at line 98 of file ace_target_pe.h.

+ +
+
+ +

◆ operation_resp()

+ +
+
+ + + + + + + + + + + + + + + + + + +
void axi::pe::ace_target_pe::operation_resp (payload_type & trans,
unsigned clk_delay = 0 
)
+
+

start the response from an operation callback if latency is not set by the callback

+
Parameters
+ + + +
trans
sync
+
+
+ +
+
+ +

◆ set_operation_cb()

+ +
+
+ + + + + +
+ + + + + + + + +
void axi::pe::ace_target_pe::set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
+ 		+inline
+
+ +

Set the operation callback function.

+

This callback is invoked once a transaction arrives. This function is not allowed to block and returns the latency of the operation i.e. the duration until the reponse phase starts

Todo:
refine API
+
Parameters
+ + +
cbthe callback function
+
+
+ +

Definition at line 85 of file ace_target_pe.h.

+ +
+
+ +

◆ setup_callbacks()

+ +
+
+ + + + + +
+ + + + + + + + +
void ace_target_pe::setup_callbacks (fsm::fsm_handle * fsm_hndl)
+ 		+overrideprotectedvirtual
+
+
See also
base::setup_callbacks(fsm::fsm_handle*)
+ +

Implements axi::fsm::base.

+ +

Definition at line 117 of file ace_target_pe.cpp.

+ +
+
+ +

◆ tx_finish_event()

+ +
+
+ + + + + +
+ + + + + + + +
const sc_core::sc_event& axi::pe::ace_target_pe::tx_finish_event ()
+ 		+inline
+
+

get the event being notfied upon the finishing of a transaction

+
Returns
reference to sc_event
+ +

Definition at line 104 of file ace_target_pe.h.

+ +
+
+
The documentation for this class was generated from the following files: +
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1ace__target__pe.js b/main/classaxi_1_1pe_1_1ace__target__pe.js new file mode 100644 index 00000000..387cc5da --- /dev/null +++ b/main/classaxi_1_1pe_1_1ace__target__pe.js @@ -0,0 +1,52 @@ +var classaxi_1_1pe_1_1ace__target__pe = +[ + [ "bw_intor_impl", "structace__target__pe_1_1bw__intor__impl.html", "structace__target__pe_1_1bw__intor__impl" ], + [ "payload_type", "classaxi_1_1pe_1_1ace__target__pe.html#ae889973eb131a8543f875092f70598cb", null ], + [ "phase_type", "classaxi_1_1pe_1_1ace__target__pe.html#a9d0786e799837fae2fe45b2cef0df1d9", null ], + [ "~ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#a2656ccc3d9d7bb084f00d0f7b4c730d7", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#a82790b1a10222ec1ba65ba11d4d176ee", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#aecde5dc99c5532dd8b686129cbee2bb7", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#ad3c15b4d3f2a7b5aa936af058e927200", null ], + [ "ace_target_pe", "classaxi_1_1pe_1_1ace__target__pe.html#ab69463b27a55bc1e38eebe542182184e", null ], + [ "b_transport", "classaxi_1_1pe_1_1ace__target__pe.html#aee6de2689874daf44969119e7fe666a0", null ], + [ "create_fsm_handle", "classaxi_1_1pe_1_1ace__target__pe.html#a3ea7193538db51859e6389130e185686", null ], + [ "end_of_elaboration", "classaxi_1_1pe_1_1ace__target__pe.html#a56e215e2f32c1b25b0ec3ce060b59a1d", null ], + [ "fsm_clk_method", "classaxi_1_1pe_1_1ace__target__pe.html#a3e54ff4ab8f6e7265efe51939e8ef7df", null ], + [ "get_direct_mem_ptr", "classaxi_1_1pe_1_1ace__target__pe.html#ab04d4d967c53804ae54bdae8f715e4d8", null ], + [ "invalidate_direct_mem_ptr", "classaxi_1_1pe_1_1ace__target__pe.html#a9d15f27415ffccf2f95cd45329793d1b", null ], + [ "is_active", "classaxi_1_1pe_1_1ace__target__pe.html#aff66caa477d0b90a7bd4eb32d928616c", null ], + [ "nb_fw", "classaxi_1_1pe_1_1ace__target__pe.html#a770f06a11beac1d1742b2b1b22dacd5a", null ], + [ "nb_transport_bw", "classaxi_1_1pe_1_1ace__target__pe.html#a7b44dab1263ee848a00578ca38ec8c67", null ], + [ "nb_transport_fw", "classaxi_1_1pe_1_1ace__target__pe.html#a5c12487466121a9165dc1f21c1f3a1e2", null ], + [ "operation_resp", "classaxi_1_1pe_1_1ace__target__pe.html#a008c71cd290c6e88971ba71b0a36835b", null ], + [ "operations_callback", "classaxi_1_1pe_1_1ace__target__pe.html#a891e960ad36c3430146d53af89fb8380", null ], + [ "operator=", "classaxi_1_1pe_1_1ace__target__pe.html#ada34ebbd220cafcedfa653cfa3211eb0", null ], + [ "operator=", "classaxi_1_1pe_1_1ace__target__pe.html#a4f8a7e54ccdbb8e39e8d47531a75dbbc", null ], + [ "set_bw_interface", "classaxi_1_1pe_1_1ace__target__pe.html#a6c7abb59dea0220e00a8171cc0b284ad", null ], + [ "set_operation_cb", "classaxi_1_1pe_1_1ace__target__pe.html#a5efdb0544aea6dc9e2dd105b86480e54", null ], + [ "setup_callbacks", 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b/main/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.md5 new file mode 100644 index 00000000..d3e8defc --- /dev/null +++ b/main/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.md5 @@ -0,0 +1 @@ +2b27ac6a6195b0400e8cede87aca3ac2 \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png b/main/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png new file mode 100644 index 00000000..5f803794 Binary files /dev/null and b/main/classaxi_1_1pe_1_1ace__target__pe__inherit__graph.png differ diff --git a/main/classaxi_1_1pe_1_1simple__ace__target-members.html b/main/classaxi_1_1pe_1_1simple__ace__target-members.html new file mode 100644 index 00000000..fbef6487 --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target-members.html @@ -0,0 +1,162 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Member List
+
+
+ +

This is the complete list of members for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_target_pe(const sc_core::sc_module_name &nm, size_t transfer_width)axi::pe::ace_target_peexplicit
ace_target_pe()=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
ace_target_pe(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
active_rdresp_id (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
b_transport(payload_type &trans, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
base typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
axi::pe::ace_target_pe::base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::base
bw_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
bw_intor (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
clk_i (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
clk_if (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
create_fsm_handle() overrideaxi::pe::ace_target_peprotectedvirtual
end_of_elaboration() (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inlineprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_method() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fw_o (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
fw_peq (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
get_direct_mem_ptr(payload_type &trans, tlm::tlm_dmi &dmi_data) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
is_active()axi::pe::ace_target_peinline
isckt_axi (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, const phase_type &phase) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinlineprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_transport_bw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
nb_transport_fw(payload_type &trans, phase_type &phase, sc_core::sc_time &t) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
operation_cb (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operation_resp(payload_type &trans, unsigned clk_delay=0)axi::pe::ace_target_pe
operations_callback(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(simple_ace_target const &)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
operator=(simple_ace_target &&)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
operator=(ace_target_pe const &)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
operator=(ace_target_pe &&)=delete (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
outstanding_cnt (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
payload_type typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
phase_type typedef (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
rd_resp (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
rd_resp_delay (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
rd_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
set_bw_interface(axi::axi_bw_transport_if< axi_protocol_types > *ifs) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peinline
set_operation_cb(std::function< unsigned(payload_type &trans)> cb)axi::pe::ace_target_peinline
setup_callbacks(fsm::fsm_handle *) overrideaxi::pe::ace_target_peprotectedvirtual
simple_ace_target(axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inline
simple_ace_target(const sc_core::sc_module_name &nm, axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket) (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >inline
simple_ace_target()=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
simple_ace_target(simple_ace_target const &)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
simple_ace_target(simple_ace_target &&)=delete (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >
snoop(payload_type &trans) (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
socket (defined in axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >)axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >protected
socket_bw (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
start_of_simulation() override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
transport_dbg(payload_type &trans) override (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
tx_finish_event()axi::pe::ace_target_peinline
wr_resp_beat_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_ch (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_resp_delayaxi::pe::ace_target_pe
wr_resp_fifo (defined in axi::pe::ace_target_pe)axi::pe::ace_target_peprotected
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~ace_target_pe() (defined in axi::pe::ace_target_pe)axi::pe::ace_target_pe
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1simple__ace__target.html b/main/classaxi_1_1pe_1_1simple__ace__target.html new file mode 100644 index 00000000..93271e3b --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target.html @@ -0,0 +1,448 @@ + + + + + + + +scc: axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+
+Public Types | +Public Member Functions | +Protected Member Functions | +Protected Attributes | +List of all members
+
+
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL > Class Template Reference
+
+
+
+Inheritance diagram for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >:
+
+
Inheritance graph
+ + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + + + + + + + + +

+Public Types

+using base = ace_target_pe
 
+using payload_type = base::payload_type
 
+using phase_type = base::phase_type
 
- Public Types inherited from axi::pe::ace_target_pe
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

 simple_ace_target (axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
 the constructor More...
 
+ simple_ace_target (const sc_core::sc_module_name &nm, axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
 
+ simple_ace_target (simple_ace_target const &)=delete
 
+ simple_ace_target (simple_ace_target &&)=delete
 
+simple_ace_target & operator= (simple_ace_target const &)=delete
 
+simple_ace_target & operator= (simple_ace_target &&)=delete
 
- Public Member Functions inherited from axi::pe::ace_target_pe
+void b_transport (payload_type &trans, sc_core::sc_time &t) override
 
+tlm::tlm_sync_enum nb_transport_fw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+bool get_direct_mem_ptr (payload_type &trans, tlm::tlm_dmi &dmi_data) override
 
+unsigned int transport_dbg (payload_type &trans) override
 
void set_operation_cb (std::function< unsigned(payload_type &trans)> cb)
 Set the operation callback function. More...
 
void operation_resp (payload_type &trans, unsigned clk_delay=0)
 
bool is_active ()
 
const sc_core::sc_event & tx_finish_event ()
 
+tlm::tlm_sync_enum nb_transport_bw (payload_type &trans, phase_type &phase, sc_core::sc_time &t) override
 
+void invalidate_direct_mem_ptr (sc_dt::uint64 start_range, sc_dt::uint64 end_range) override
 
 ace_target_pe (const sc_core::sc_module_name &nm, size_t transfer_width)
 
+void set_bw_interface (axi::axi_bw_transport_if< axi_protocol_types > *ifs)
 
+void snoop (payload_type &trans)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Member Functions

+void end_of_elaboration ()
 
- Protected Member Functions inherited from axi::pe::ace_target_pe
+ ace_target_pe (ace_target_pe const &)=delete
 
+ ace_target_pe (ace_target_pe &&)=delete
 
+ace_target_pe & operator= (ace_target_pe const &)=delete
 
+ace_target_pe & operator= (ace_target_pe &&)=delete
 
+void end_of_elaboration () override
 
+void start_of_simulation () override
 
+void fsm_clk_method ()
 
fsm::fsm_handle * create_fsm_handle () override
 
void setup_callbacks (fsm::fsm_handle *) override
 
+unsigned operations_callback (payload_type &trans)
 
+void nb_fw (payload_type &trans, const phase_type &phase)
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Protected Attributes

+axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > & socket
 
- Protected Attributes inherited from axi::pe::ace_target_pe
+axi::axi_bw_transport_if< axi_protocol_types > * socket_bw {nullptr}
 
+std::function< unsigned(payload_type &trans)> operation_cb
 
+sc_core::sc_fifo< payload_type * > rd_resp_fifo {1}
 
+sc_core::sc_fifo< payload_type * > wr_resp_fifo {1}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > wr_resp_beat_fifo {128}
 
+sc_core::sc_fifo< std::tuple< fsm::fsm_handle *, axi::fsm::protocol_time_point_e > > rd_resp_beat_fifo {128}
 
+scc::ordered_semaphore rd_resp {1}
 
+scc::ordered_semaphore wr_resp_ch {1}
 
+scc::ordered_semaphore rd_resp_ch {1}
 
+sc_core::sc_clock * clk_if {nullptr}
 
+std::unique_ptr< bw_intor_impl > bw_intor
 
+std::array< unsigned, 3 > outstanding_cnt {{0, 0, 0}}
 
+tlm_utils::peq_with_cb_and_phase< ace_target_pe > fw_peq {this, &ace_target_pe::nb_fw}
 
+std::unordered_set< unsigned > active_rdresp_id
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+ + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Public Attributes inherited from axi::pe::ace_target_pe
+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< 64 > isckt_axi {"isckt_axi"}
 
+sc_core::sc_port< tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND > fw_o {"fw_o"}
 
+sc_core::sc_export< tlm::scc::pe::intor_bw_nb > bw_i {"bw_i"}
 
+scc::sc_attribute_randomized< int > rd_resp_delay {"rd_resp_delay", 0}
 
+scc::sc_attribute_randomized< int > wr_resp_delay {"wr_resp_delay", 0}
 the latency between request and response phase. Will be overwritten by the return of the callback function (if registered) -> BV
 
- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+

Detailed Description

+

template<unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1, sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+class axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >

+ + +

Definition at line 29 of file simple_ace_target.h.

+

Constructor & Destructor Documentation

+ +

◆ simple_ace_target()

+ +
+
+
+template<unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1, sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+ + + + + +
+ + + + + + + + +
axi::pe::simple_ace_target< BUSWIDTH, TYPES, N, POL >::simple_ace_target (axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > & socket)
+ 		+inline
+
+ +

the constructor

+
Parameters
+ + +
socketreference to the initiator socket used to send and receive transactions
+
+
+ +

Definition at line 39 of file simple_ace_target.h.

+ +
+
+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1simple__ace__target.js b/main/classaxi_1_1pe_1_1simple__ace__target.js new file mode 100644 index 00000000..09248d4a --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target.js @@ -0,0 +1,15 @@ +var classaxi_1_1pe_1_1simple__ace__target = +[ + [ "base", "classaxi_1_1pe_1_1simple__ace__target.html#acbf23f74d25717850fbe7f7489364977", null ], + [ "payload_type", "classaxi_1_1pe_1_1simple__ace__target.html#a9df478707657e5a90f828699d6e48346", null ], + [ "phase_type", "classaxi_1_1pe_1_1simple__ace__target.html#a1650fcfd05a074a1e13161957c275885", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a6ba3fdb7ad9c049d876814d0fe836926", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a969b78419fad753207f7e05f3dd7c63b", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#afaa647f336a95cb1945f02ce3521b45a", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a2a16bd1c0fc796edab64a59d9f1a7fb3", null ], + [ "simple_ace_target", "classaxi_1_1pe_1_1simple__ace__target.html#a5d7cf470b870bfc0d6b8907f510db5a4", null ], + [ "end_of_elaboration", "classaxi_1_1pe_1_1simple__ace__target.html#a012e11d501b45cb3d3e5bc7e78ad1a16", null ], + [ "operator=", "classaxi_1_1pe_1_1simple__ace__target.html#a9133a9faccf7333b1e7852cc2d1dc51a", null ], + [ "operator=", "classaxi_1_1pe_1_1simple__ace__target.html#afabb06b5476d1e0c0b0ed2d717ee0921", null ], + [ "socket", "classaxi_1_1pe_1_1simple__ace__target.html#a640b57953b23173cc21e741a7a46d26c", null ] +]; \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map new file mode 100644 index 00000000..a93561df --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.map @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 new file mode 100644 index 00000000..a7eaaadd --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.md5 @@ -0,0 +1 @@ +6832e2357653c11f914534647c5b4f4b \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png new file mode 100644 index 00000000..b25a1bb3 Binary files /dev/null and b/main/classaxi_1_1pe_1_1simple__ace__target__coll__graph.png differ diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map new file mode 100644 index 00000000..109f5af3 --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 new file mode 100644 index 00000000..0756c513 --- /dev/null +++ b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.md5 @@ -0,0 +1 @@ +9fec7f3567501f2e02831df2e72aefdc \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png new file mode 100644 index 00000000..580dae2f Binary files /dev/null and b/main/classaxi_1_1pe_1_1simple__ace__target__inherit__graph.png differ diff --git a/main/classaxi_1_1pe_1_1target__info__if-members.html b/main/classaxi_1_1pe_1_1target__info__if-members.html new file mode 100644 index 00000000..8237411a --- /dev/null +++ b/main/classaxi_1_1pe_1_1target__info__if-members.html @@ -0,0 +1,82 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::pe::target_info_if Member List
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This is the complete list of members for axi::pe::target_info_if, including all inherited members.

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get_outstanding_tx_count()=0 (defined in axi::pe::target_info_if)axi::pe::target_info_ifpure virtual
~target_info_if()=default (defined in axi::pe::target_info_if)axi::pe::target_info_ifvirtual
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1target__info__if.html b/main/classaxi_1_1pe_1_1target__info__if.html new file mode 100644 index 00000000..4a5f53ca --- /dev/null +++ b/main/classaxi_1_1pe_1_1target__info__if.html @@ -0,0 +1,106 @@ + + + + + + + +scc: axi::pe::target_info_if Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Public Member Functions | +List of all members
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axi::pe::target_info_if Class Referenceabstract
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+Inheritance diagram for axi::pe::target_info_if:
+
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Inheritance graph
+ + + + + + + +
[legend]
+ + + + +

+Public Member Functions

+virtual size_t get_outstanding_tx_count ()=0
 
+

Detailed Description

+
+

Definition at line 14 of file target_info_if.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classaxi_1_1pe_1_1target__info__if.js b/main/classaxi_1_1pe_1_1target__info__if.js new file mode 100644 index 00000000..fd4edc94 --- /dev/null +++ b/main/classaxi_1_1pe_1_1target__info__if.js @@ -0,0 +1,5 @@ +var classaxi_1_1pe_1_1target__info__if = +[ + [ "~target_info_if", "classaxi_1_1pe_1_1target__info__if.html#aaaf50a3ff1ded66912de03102a103d85", null ], + [ "get_outstanding_tx_count", "classaxi_1_1pe_1_1target__info__if.html#a1ccb7acff97230b07b1e9efca056176a", null ] +]; \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.map b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.map new file mode 100644 index 00000000..fe302287 --- /dev/null +++ b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 new file mode 100644 index 00000000..52acb5a6 --- /dev/null +++ b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.md5 @@ -0,0 +1 @@ +5c3a1e0994aebf684f6705c04b654039 \ No newline at end of file diff --git a/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.png b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.png new file mode 100644 index 00000000..4f9a26dc Binary files /dev/null and b/main/classaxi_1_1pe_1_1target__info__if__inherit__graph.png differ diff --git a/main/classscc_1_1sc__in__opt-members.html b/main/classscc_1_1sc__in__opt-members.html new file mode 100644 index 00000000..1b7b0a10 --- /dev/null +++ b/main/classscc_1_1sc__in__opt-members.html @@ -0,0 +1,115 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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base_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
base_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
data_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
default_event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
in_if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
in_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
inout_if_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
inout_port_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
kind() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlinevirtual
operator const data_type &() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
read() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt() (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
this_type typedef (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >
value_changed_event() const (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inline
~sc_in_opt() (defined in scc::sc_in_opt< T >)scc::sc_in_opt< T >inlinevirtual
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt.html b/main/classscc_1_1sc__in__opt.html new file mode 100644 index 00000000..cdb5b451 --- /dev/null +++ b/main/classscc_1_1sc__in__opt.html @@ -0,0 +1,215 @@ + + + + + + + +scc: scc::sc_in_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< T >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< T >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+virtual const char * kind () const
 
+

Detailed Description

+

template<class T>
+class scc::sc_in_opt< T >

+ + +

Definition at line 39 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt.js b/main/classscc_1_1sc__in__opt.js new file mode 100644 index 00000000..fcffb63b --- /dev/null +++ b/main/classscc_1_1sc__in__opt.js @@ -0,0 +1,38 @@ +var classscc_1_1sc__in__opt = +[ + [ "base_port_type", "classscc_1_1sc__in__opt.html#a4382df3bdfb762af71f0f39b7b9b91d2", null ], + [ "base_type", "classscc_1_1sc__in__opt.html#a358ffb2ce8eff5c84b81b20d369bcd3f", null ], + [ "data_type", "classscc_1_1sc__in__opt.html#a11f1f6cc1a56682fbd8f0d37d9d7f5ef", null ], + [ "if_type", "classscc_1_1sc__in__opt.html#a7f23aaf7fa0e4694d42e55b9125912af", null ], + [ "in_if_type", "classscc_1_1sc__in__opt.html#a5b8c1f663e569931451a4236106578ca", null ], + [ "in_port_type", "classscc_1_1sc__in__opt.html#a3e2a03eb9e8eff9e6c956457326d1c8f", null ], + [ "inout_if_type", "classscc_1_1sc__in__opt.html#a36754774d16cddaaac87bc624fea5c98", null ], + [ "inout_port_type", "classscc_1_1sc__in__opt.html#a3878d27e2cce111fcce61b5993fb8c50", null ], + [ "this_type", "classscc_1_1sc__in__opt.html#acac46ff317b8e84689cb0bbc6377df03", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a7a7860e661cb59b2b1519efe4a583311", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#ae3357731d9f210f6d2a25ae488900cf2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a663090a84c2ccc04c282ab13345541c5", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a74a2ae1e0f6af24804d3d086855932e8", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a334f6df18e92f7e7d55ca15b75339e61", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a65f5bf71da783339c780c145a562c2f2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a7c3a0f0008219ef34a8e3e1f287edc73", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a2bbcfc30d6b466bf05bb395901f0fb12", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#aee0c8591eef251f2100d143995dffc07", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#aef05b7102e651b5ea2d831f26502812f", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt.html#a06d2218c1398c5bd3b0f8aee91405cff", null ], + [ "~sc_in_opt", "classscc_1_1sc__in__opt.html#a4f39aa4cc01a847cf3aa1258a3c69393", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a34594ba85e2acdeb7b72bff03ba83097", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a24b9e9ab9a30a9f296a8630c6bc4ed0d", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a978ec8e6940ab222456acba4a3f3de70", null ], + [ "bind", "classscc_1_1sc__in__opt.html#a44d52e1d90722a1881b6fd68e307c0cd", null ], + [ "default_event", "classscc_1_1sc__in__opt.html#af9bfec8ff248bdaa246f7772de9b7fff", null ], + [ "event", "classscc_1_1sc__in__opt.html#ac263423ca1866bee1d670ba6eaad539e", null ], + [ "kind", "classscc_1_1sc__in__opt.html#a62f47a6a5e71645ff5ad96c3220dde7d", null ], + [ "operator const data_type &", "classscc_1_1sc__in__opt.html#adf6da12c8ffe8ed8390dcf4c2e368cfa", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#a11ce8221e4cd00709eff5c58392109fb", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#adbed146f319e78d6b748c6b1e80e7db3", null ], + [ "operator()", "classscc_1_1sc__in__opt.html#a319e4f48d38bfe8d7cd4db983514e646", null ], + [ "operator=", "classscc_1_1sc__in__opt.html#aa2f4d1e4219e87af1de23e9aec72125f", null ], + [ "read", "classscc_1_1sc__in__opt.html#a974d2a0ad850d85addbd85ce1b89e50b", null ], + [ "value_changed_event", "classscc_1_1sc__in__opt.html#ad76a9e660a5cc6887d9442ab90fad9f8", null ] +]; \ No newline at end of file diff --git a/main/classscc_1_1sc__in__opt_3_01bool_01_4-members.html b/main/classscc_1_1sc__in__opt_3_01bool_01_4-members.html new file mode 100644 index 00000000..b1cbdf1c --- /dev/null +++ b/main/classscc_1_1sc__in__opt_3_01bool_01_4-members.html @@ -0,0 +1,119 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_in_opt< bool > Member List
+
+
+ +

This is the complete list of members for scc::sc_in_opt< bool >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
base_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
data_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
default_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
in_if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
in_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
inout_if_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
inout_port_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
kind() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlinevirtual
negedge() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
negedge_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator const data_type &() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
posedge() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
posedge_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
read() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt() (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
this_type typedef (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >
value_changed_event() const (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >inline
~sc_in_opt()=default (defined in scc::sc_in_opt< bool >)scc::sc_in_opt< bool >virtual
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt_3_01bool_01_4.html b/main/classscc_1_1sc__in__opt_3_01bool_01_4.html new file mode 100644 index 00000000..3711c38d --- /dev/null +++ b/main/classscc_1_1sc__in__opt_3_01bool_01_4.html @@ -0,0 +1,224 @@ + + + + + + + +scc: scc::sc_in_opt< bool > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< bool > Class Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< bool >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< bool >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef bool data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+virtual const char * kind () const
 
+

Detailed Description

+
+

Definition at line 127 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt_3_01bool_01_4.js b/main/classscc_1_1sc__in__opt_3_01bool_01_4.js new file mode 100644 index 00000000..7bc6bfcf --- /dev/null +++ b/main/classscc_1_1sc__in__opt_3_01bool_01_4.js @@ -0,0 +1,42 @@ +var classscc_1_1sc__in__opt_3_01bool_01_4 = +[ + [ "base_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a56745c49991c34fd2f49f29d05683dbf", null ], + [ "base_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#af9c315123f7f84f8e125cdef76b0ef63", null ], + [ "data_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aaea19fdc3a66fd8758fb8a7702a59a15", null ], + [ "if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a1091f706cf5b1d9163c025a7173789b0", null ], + [ "in_if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#af21b2f97c8c486ff7d87d5541fdd0c50", null ], + [ "in_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a3ee5ac9543ebee2c8968ac7cedbaf0a3", null ], + [ "inout_if_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad6837ba41d15342486e8cbb69fc2ca75", null ], + [ "inout_port_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab8a71fecaaa3b607c1aa5689146ed14a", null ], + [ "this_type", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a8696d9c4c7e6586f649748ea4b7f3291", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aed0d010e7cc571d06337d903b29c2372", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab1cbdb8d1db15cb0b6d636dcf5d347f1", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a36d87c0655ca88706fc2002dd59f90c2", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aa45a419f804da5dc9f30542939b943dc", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#abe192d0fc1170cd2fd20bf9a80ba8228", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a248c8585852372987673aa3091f1bcd7", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a1ce6f1376c868e7b6c44dd7e54e12b90", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#aa8f014172c70653d04f34ede343eb5bd", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ae4e44b5f5dcb17b5e09779bb2e05a157", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad4ce350770155c9ba364f767960c9466", null ], + [ "sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a0dc23df0bc6b68d884a6d9c05e150346", null ], + [ "~sc_in_opt", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ae51f6057db2cae6bade028c9b624ca06", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a8b7f6b48de0bccd9630033f29f4675d6", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad7fafb46d604a4e65153fe29f0c2192e", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2065d43e6c8c61a7c2575ebe9381f7c3", null ], + [ "bind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a888ae8b3fbd0d661fd7dc2c431c0c039", null ], + [ "default_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2ad682aef251761e033ec88641376ffd", null ], + [ "event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a3284dc277e10907814ecee3cd749e5ec", null ], + [ "kind", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a446f74238bf06597df7970f8a8078228", null ], + [ "negedge", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ab080709e85a15533eaadbf87673c472a", null ], + [ "negedge_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a9acbe36c4e446757ab22803ad5499d72", null ], + [ "operator const data_type &", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a19d36daeafa1a67a2fec097500c09a35", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a59e2dceb06486a1173ff9af0ecaf5109", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a61249c3c155be89cdbf683c643a1ef6a", null ], + [ "operator()", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ac30742b34ad035eecba8130fd5028ea5", null ], + [ "operator=", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a2e26724c90388ecbf1f79a8b2b28597c", null ], + [ "posedge", "classscc_1_1sc__in__opt_3_01bool_01_4.html#ad24d71f08d0ed12b70b4dc6dbfb7d47a", null ], + [ "posedge_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a882d42f88020a78d7b484de2954dcdb6", null ], + [ "read", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a636bd1df276252e2af659b45f0c95160", null ], + [ "value_changed_event", "classscc_1_1sc__in__opt_3_01bool_01_4.html#a4456ba9eedde54aa91627c550202799e", null ] +]; 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+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_in_opt< sc_dt::sc_logic > Member List
+
+
+ +

This is the complete list of members for scc::sc_in_opt< sc_dt::sc_logic >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
base_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
bind(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
bind(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
data_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
default_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
in_if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
in_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
inout_if_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
inout_port_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
kind() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlinevirtual
negedge() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
negedge_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator const data_type &() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator()(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
operator=(const this_type &)=delete (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
posedge() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
posedge_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
read() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt() (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const char *name_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, const in_if_type &interface_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, in_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inlineexplicit
sc_in_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(this_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const char *name_, this_type &parent_) (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
sc_in_opt(const this_type &)=delete (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
this_type typedef (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >
value_changed_event() const (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >inline
~sc_in_opt()=default (defined in scc::sc_in_opt< sc_dt::sc_logic >)scc::sc_in_opt< sc_dt::sc_logic >virtual
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html b/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html new file mode 100644 index 00000000..61b58ef8 --- /dev/null +++ b/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html @@ -0,0 +1,224 @@ + + + + + + + +scc: scc::sc_in_opt< sc_dt::sc_logic > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_in_opt< sc_dt::sc_logic > Class Reference
+
+
+
+Inheritance diagram for scc::sc_in_opt< sc_dt::sc_logic >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_in_opt< sc_dt::sc_logic >:
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+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef sc_dt::sc_logic data_type
 
+typedef sc_core::sc_signal_in_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_in_opt< data_type > this_type
 
+typedef base_type::port_type base_port_type
 
+typedef if_type in_if_type
 
+typedef base_type in_port_type
 
+typedef sc_core::sc_signal_inout_if< data_type > inout_if_type
 
+typedef sc_core::sc_port< inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_in_opt (const char *name_)
 
+ sc_in_opt (const in_if_type &interface_)
 
+ sc_in_opt (const char *name_, const in_if_type &interface_)
 
+ sc_in_opt (in_port_type &parent_)
 
+ sc_in_opt (const char *name_, in_port_type &parent_)
 
+ sc_in_opt (inout_port_type &parent_)
 
+ sc_in_opt (const char *name_, inout_port_type &parent_)
 
+ sc_in_opt (this_type &parent_)
 
+ sc_in_opt (const char *name_, this_type &parent_)
 
+ sc_in_opt (const this_type &)=delete
 
+this_type & operator= (const this_type &)=delete
 
+SCC_VIRT void bind (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_if_type &interface_)
 
+void operator() (const in_if_type &interface_)
 
+SCC_VIRT void bind (in_port_type &parent_)
 
+void operator() (in_port_type &parent_)
 
+SCC_VIRT void bind (inout_port_type &parent_)
 
+void operator() (inout_port_type &parent_)
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+virtual const char * kind () const
 
+

Detailed Description

+
+

Definition at line 223 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js b/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js new file mode 100644 index 00000000..4d4ae737 --- /dev/null +++ b/main/classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.js @@ -0,0 +1,42 @@ +var classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4 = +[ + [ "base_port_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#aa84e5227a01388b8357514d8145e94c9", null ], + [ "base_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a615d83ba4d4d1f2ca6ea75e9c14f9e78", null ], + [ "data_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a7283a171a666a3f68757e989c85e3c93", null ], + [ "if_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#a20f837fcc144564d5c82dafb3420ff61", null ], + [ "in_if_type", "classscc_1_1sc__in__opt_3_01sc__dt_1_1sc__logic_01_4.html#aa42f6bbfe19b676cb38d21dc1e6e9a08", null ], + [ "in_port_type", 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a/main/classscc_1_1sc__inout__opt-members.html b/main/classscc_1_1sc__inout__opt-members.html new file mode 100644 index 00000000..75a79f0a --- /dev/null +++ b/main/classscc_1_1sc__inout__opt-members.html @@ -0,0 +1,114 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< T > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< T >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
data_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
default_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_port_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
inout_if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
inout_port_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
kind() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >protected
operator const data_type &() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
read() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt() (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
this_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
value_changed_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >virtual
+
+ + + + diff --git a/main/classscc_1_1sc__inout__opt.html b/main/classscc_1_1sc__inout__opt.html new file mode 100644 index 00000000..63c26916 --- /dev/null +++ b/main/classscc_1_1sc__inout__opt.html @@ -0,0 +1,218 @@ + + + + + + + +scc: scc::sc_inout_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< T >:
+
+
Inheritance graph
+ + + + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< T >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+

template<class T>
+class scc::sc_inout_opt< T >

+ + +

Definition at line 314 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__inout__opt.js b/main/classscc_1_1sc__inout__opt.js new file mode 100644 index 00000000..f389399c --- /dev/null +++ b/main/classscc_1_1sc__inout__opt.js @@ -0,0 +1,37 @@ +var classscc_1_1sc__inout__opt = +[ + [ "base_type", "classscc_1_1sc__inout__opt.html#af285a031936bae6f608ba67e6a7ef77d", null ], + [ "data_type", "classscc_1_1sc__inout__opt.html#a41430f6efc502149b8e3b6ad695769d8", null ], + [ "if_type", "classscc_1_1sc__inout__opt.html#a234939be32081957f5c5c1cf8322ba36", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt.html#a0b7dd44918a468585d66285430dac129", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt.html#a3f18aa4eae4da8c3fe3c826fd0433db3", null ], + [ "inout_if_type", "classscc_1_1sc__inout__opt.html#ab5a054fa7031d4e50e3dbd37e9cb3448", null ], + [ "inout_port_type", "classscc_1_1sc__inout__opt.html#a64ca3502a5534eec3a5e70056744771a", null ], + [ "this_type", "classscc_1_1sc__inout__opt.html#ac8a108aca04c2c503fce90e62c949047", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a7716f1859642b4c01f27247284ac3cc3", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a526b55a33226798050ef7ad82ac03aef", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a969eda7bc3a02031664302a2907e0245", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#afe1b6d6446f231b8eda67ae187225882", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a2738d7d28fbe0f1e1c0f64e4ac0daa6c", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a5c1281be3833562e106094a5df25735b", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#aeeb235f7fc678d4915d7033fff4f0c2d", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a7f4fc6310bded783c228c552889d33ac", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt.html#a45e14b3ab30dee3a39fc692d5a567841", null ], + [ "~sc_inout_opt", "classscc_1_1sc__inout__opt.html#a81b73209c4283d2e47e42eee0f762843", null ], + [ "default_event", "classscc_1_1sc__inout__opt.html#a12f0b446329367dcca450701b8693c3c", null ], + [ "end_of_elaboration", "classscc_1_1sc__inout__opt.html#a016fa8a6fc5e187aa52fb609f14889a3", null ], + [ "event", "classscc_1_1sc__inout__opt.html#ab0b1fba3844d25d347e2b2be552940ec", null ], + [ "initialize", "classscc_1_1sc__inout__opt.html#a1f044189e16aab8bf98de880b638a68c", null ], + [ "initialize", "classscc_1_1sc__inout__opt.html#ab1a6aef6ad5a51c82723a74c24b3b0b0", null ], + [ "kind", "classscc_1_1sc__inout__opt.html#aaead6c067289ec4afd623106cb12b92a", null ], + [ "operator const data_type &", "classscc_1_1sc__inout__opt.html#af47b867524b650867fc41b411ca4ee04", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a009c1e98f720c21586c544f53fd217ba", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#aba8814b31b8165a93f26dcd53fe30be4", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a95bc49a4da2cfbf41645628e61f3958d", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#a31263843e83964719447551716a4a0f9", null ], + [ "operator=", "classscc_1_1sc__inout__opt.html#aa07066c21c0d5dc6feed74d14817a76f", null ], + [ "read", "classscc_1_1sc__inout__opt.html#aef88e80fcc2a3aef497b7856a6f08b00", null ], + [ "value_changed_event", "classscc_1_1sc__inout__opt.html#a9298ba5a89b9c4fabba531cd1ffe42cf", null ], + [ "write", "classscc_1_1sc__inout__opt.html#ac39bc6165ff428d942619b5853d8df9a", null ], + [ "m_init_val", "classscc_1_1sc__inout__opt.html#a34955da8b061b2f331387a394ab2fc3c", null ] +]; \ No newline at end of file diff --git a/main/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html b/main/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html new file mode 100644 index 00000000..8b1f2816 --- /dev/null +++ b/main/classscc_1_1sc__inout__opt_3_01bool_01_4-members.html @@ -0,0 +1,118 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< bool > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< bool >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
data_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
default_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
in_if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
in_port_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
inout_if_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
inout_port_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
kind() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >protected
negedge() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
negedge_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator const data_type &() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
posedge() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
posedge_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
read() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt() (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
this_type typedef (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >
value_changed_event() const (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< bool >)scc::sc_inout_opt< bool >virtual
+
+ + + + diff --git a/main/classscc_1_1sc__inout__opt_3_01bool_01_4.html b/main/classscc_1_1sc__inout__opt_3_01bool_01_4.html new file mode 100644 index 00000000..cfd74ace --- /dev/null +++ b/main/classscc_1_1sc__inout__opt_3_01bool_01_4.html @@ -0,0 +1,225 @@ + + + + + + + +scc: scc::sc_inout_opt< bool > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
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+
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+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< bool > Class Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< bool >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< bool >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef bool data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+
+

Definition at line 440 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__inout__opt_3_01bool_01_4.js b/main/classscc_1_1sc__inout__opt_3_01bool_01_4.js new file mode 100644 index 00000000..a740cd3e --- /dev/null +++ b/main/classscc_1_1sc__inout__opt_3_01bool_01_4.js @@ -0,0 +1,41 @@ +var classscc_1_1sc__inout__opt_3_01bool_01_4 = +[ + [ "base_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac06302b2655cd63054b02b17914f19b7", null ], + [ "data_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a73af6e1fcbedeaf67d821b5a62b730f2", null ], + [ "if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a8c2e707e9a82051244ee6bebcccf2e76", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ab46aa025fdf0754ee3c24cda67e7cc18", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a0cf8561f5c33a952fb91347eb2655198", null ], + [ "inout_if_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a49c3b60c6d6c763018cfc298c0a04fff", null ], + [ "inout_port_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a4f44adc09b4c1c73189c5befe054df76", null ], + [ "this_type", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a359383a2bfed11eea866e1c702b6d574", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a79bb2267f5419a7d93cd5f11777bf659", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae2579559af35b24e395e99d5d12c4f21", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ad7a5433305d4e336f58acde36ecabff4", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a800968ea8895cbca8dd91092c96a4813", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7d38f2b51eb7bae0f4a677d1f9f53d62", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae47daae279119b189bb77cd1f9e1a023", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a17bc12b0c5c5ec6228f609bada3018b4", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a84a9eecffeb0238d8979abe180551fb6", null ], + [ "sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#aee86aa895f7c707700c4518ca35a40cb", null ], + [ "~sc_inout_opt", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a5b2029cb58031cbb56070c0fabe1f0b2", null ], + [ "default_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a805979f1ac4a3d31b29013f4511acdba", null ], + [ "end_of_elaboration", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a12620bd0f1cddb179cece7bdcde3ca80", null ], + [ "event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7b2cca8c1fe4e76da7b9c5354281f91f", null ], + [ "initialize", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac4c8f786acabc874f3b4b5f3458eb1e5", null ], + [ "initialize", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a131c79bbf4ebeb32c3afa59a05b40fdb", null ], + [ "kind", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ad3db89100bb4c9eac4bf92ccb24f1b37", null ], + [ "negedge", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ae986972cfdb52472aea3179a719aa2ee", null ], + [ "negedge_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a720f33c501e4a420d51e1bb5b9d4cf58", null ], + [ "operator const data_type &", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a980968def660224555a78ea196e86c10", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a9d5dd105fca7bda0e6d4d50f03dd43d6", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#acc2c199ee9c84dd4f0a8d27f54ca5f2a", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a7ef52c5ebe3c1178ce4126cbded4a471", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a1a7e561cfc77abeb7ecf0ae198c52946", null ], + [ "operator=", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#abad433d53b0886ff432d1576a0d897af", null ], + [ "posedge", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a951b30e353938feb999b31686f3b2360", null ], + [ "posedge_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a16a5e567d3cb0c9768c6b94ef26ea6c3", null ], + [ "read", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a6dba440040f34e34a51864f80a700ad6", null ], + [ "value_changed_event", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a690f36bd2a27f3c80196a82bf953eaec", null ], + [ "write", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#ac95ce8fbef6cafe44dcf088b92e1a13c", null ], + [ "m_init_val", "classscc_1_1sc__inout__opt_3_01bool_01_4.html#a71332131c3871ef2ab7336e42d43e03a", null ] +]; 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+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_inout_opt< sc_dt::sc_logic > Member List
+
+
+ +

This is the complete list of members for scc::sc_inout_opt< sc_dt::sc_logic >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
data_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
default_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
in_if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
in_port_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
inout_if_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
inout_port_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
kind() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >protected
negedge() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
negedge_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator const data_type &() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const in_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const in_port_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const inout_port_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
operator=(const this_type &port_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
posedge() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
posedge_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
read() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt() (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
this_type typedef (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >
value_changed_event() const (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >inline
~sc_inout_opt() (defined in scc::sc_inout_opt< sc_dt::sc_logic >)scc::sc_inout_opt< sc_dt::sc_logic >virtual
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+ + + + diff --git a/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html b/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html new file mode 100644 index 00000000..a81e662d --- /dev/null +++ b/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html @@ -0,0 +1,225 @@ + + + + + + + +scc: scc::sc_inout_opt< sc_dt::sc_logic > Class Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Protected Attributes | +List of all members
+
+
scc::sc_inout_opt< sc_dt::sc_logic > Class Reference
+
+
+
+Inheritance diagram for scc::sc_inout_opt< sc_dt::sc_logic >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::sc_inout_opt< sc_dt::sc_logic >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + + + + + + + + + + +

+Public Types

+typedef sc_dt::sc_logic data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const sc_core::sc_event & posedge_event () const
 
+const sc_core::sc_event & negedge_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+bool posedge () const
 
+bool negedge () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+virtual const char * kind () const
 
+ + + +

+Protected Attributes

+data_type * m_init_val
 
+

Detailed Description

+
+

Definition at line 558 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
+ + + + diff --git a/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js b/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js new file mode 100644 index 00000000..c6c51951 --- /dev/null +++ b/main/classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.js @@ -0,0 +1,41 @@ +var classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4 = +[ + [ "base_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a9063b2c9a086d2d32984e7dddbb39a3c", null ], + [ "data_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#ab01bc331e110c98481f5e15099ef2c77", null ], + [ "if_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a03f30d59ead3401572807533f583f0ed", null ], + [ "in_if_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#ae844b461209c984714dd9637d45cdef5", null ], + [ "in_port_type", "classscc_1_1sc__inout__opt_3_01sc__dt_1_1sc__logic_01_4.html#a45445992e8be53330b9c4ad8834d629f", null ], + [ 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and b/main/classscc_1_1sc__inout__opt__inherit__graph.png differ diff --git a/main/classscc_1_1sc__out__opt-members.html b/main/classscc_1_1sc__out__opt-members.html new file mode 100644 index 00000000..509d8de7 --- /dev/null +++ b/main/classscc_1_1sc__out__opt-members.html @@ -0,0 +1,123 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::sc_out_opt< T > Member List
+
+
+ +

This is the complete list of members for scc::sc_out_opt< T >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
base_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
data_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
default_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
end_of_elaboration() override (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
if_type typedef (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
in_if_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
in_port_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
initialize(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
initialize(const in_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
inout_if_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
inout_port_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
kind() const (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlinevirtual
m_init_val (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >protected
operator const data_type &() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
operator=(const data_type &value_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const in_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const in_port_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const inout_port_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
operator=(const this_type &port_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
read() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt() (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inlineexplicit
sc_inout_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const char *name_, this_type &parent_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
sc_inout_opt(const this_type &)=delete (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >
sc_out_opt() (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(const char *name_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(inout_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(const char *name_, inout_if_type &interface_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(inout_port_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlineexplicit
sc_out_opt(const char *name_, inout_port_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(this_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
sc_out_opt(const char *name_, this_type &parent_) (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inline
this_type typedef (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >
value_changed_event() const (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
write(const data_type &value_) (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >inline
~sc_inout_opt()=default (defined in scc::sc_inout_opt< T >)scc::sc_inout_opt< T >virtual
~sc_out_opt() (defined in scc::sc_out_opt< T >)scc::sc_out_opt< T >inlinevirtual
+
+ + + + diff --git a/main/classscc_1_1sc__out__opt.html b/main/classscc_1_1sc__out__opt.html new file mode 100644 index 00000000..e74901dc --- /dev/null +++ b/main/classscc_1_1sc__out__opt.html @@ -0,0 +1,277 @@ + + + + + + + +scc: scc::sc_out_opt< T > Class Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +List of all members
+
+
scc::sc_out_opt< T > Class Template Reference
+
+
+
+Inheritance diagram for scc::sc_out_opt< T >:
+
+
Inheritance graph
+ + + + + +
[legend]
+
+Collaboration diagram for scc::sc_out_opt< T >:
+
+
Collaboration graph
+ + + + + +
[legend]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Types

+typedef T data_type
 
+typedef sc_out_opt< data_type > this_type
 
+typedef sc_inout_opt< data_type > base_type
 
+typedef base_type::in_if_type in_if_type
 
+typedef base_type::in_port_type in_port_type
 
+typedef base_type::inout_if_type inout_if_type
 
+typedef base_type::inout_port_type inout_port_type
 
- Public Types inherited from scc::sc_inout_opt< T >
+typedef T data_type
 
+typedef sc_core::sc_signal_inout_if< data_type > if_type
 
+typedef sc_core::sc_port< if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > base_type
 
+typedef sc_inout_opt< data_type > this_type
 
+typedef sc_core::sc_signal_in_if< data_type > in_if_type
 
+typedef sc_core::sc_port< in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND > in_port_type
 
+typedef if_type inout_if_type
 
+typedef base_type inout_port_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ sc_out_opt (const char *name_)
 
+ sc_out_opt (inout_if_type &interface_)
 
+ sc_out_opt (const char *name_, inout_if_type &interface_)
 
+ sc_out_opt (inout_port_type &parent_)
 
+ sc_out_opt (const char *name_, inout_port_type &parent_)
 
+ sc_out_opt (this_type &parent_)
 
+ sc_out_opt (const char *name_, this_type &parent_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+virtual const char * kind () const
 
- Public Member Functions inherited from scc::sc_inout_opt< T >
+ sc_inout_opt (const char *name_)
 
+ sc_inout_opt (inout_if_type &interface_)
 
+ sc_inout_opt (const char *name_, inout_if_type &interface_)
 
+ sc_inout_opt (inout_port_type &parent_)
 
+ sc_inout_opt (const char *name_, inout_port_type &parent_)
 
+ sc_inout_opt (this_type &parent_)
 
+ sc_inout_opt (const char *name_, this_type &parent_)
 
+ sc_inout_opt (const this_type &)=delete
 
+const sc_core::sc_event & default_event () const
 
+const sc_core::sc_event & value_changed_event () const
 
+const data_type & read () const
 
+ operator const data_type & () const
 
+bool event () const
 
+void write (const data_type &value_)
 
+this_type & operator= (const data_type &value_)
 
+this_type & operator= (const in_if_type &interface_)
 
+this_type & operator= (const in_port_type &port_)
 
+this_type & operator= (const inout_port_type &port_)
 
+this_type & operator= (const this_type &port_)
 
+void initialize (const data_type &value_)
 
+void initialize (const in_if_type &interface_)
 
+void end_of_elaboration () override
 
+ + + + +

+Additional Inherited Members

- Protected Attributes inherited from scc::sc_inout_opt< T >
+data_type * m_init_val
 
+

Detailed Description

+

template<class T>
+class scc::sc_out_opt< T >

+ + +

Definition at line 673 of file signal_opt_ports.h.

+
The documentation for this class was generated from the following file: +
+
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+ + + + + + +scc: /home/eyck/git/SystemC-Components/src/sysc/scc/signal_opt_ports.cpp Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
signal_opt_ports.cpp
+
+
+
1 #include "signal_opt_ports.h"
+
2 template class sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
3 template class sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
4 template class sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
5 template class sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
+
+ + + + diff --git a/main/signal__opt__ports_8h_source.html b/main/signal__opt__ports_8h_source.html new file mode 100644 index 00000000..84fa24b8 --- /dev/null +++ b/main/signal__opt__ports_8h_source.html @@ -0,0 +1,856 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/src/sysc/scc/signal_opt_ports.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
signal_opt_ports.h
+
+
+
1 /*******************************************************************************
+
2  * Copyright 2001 - 2023 Accellera Systems Initiative Inc. (Accellera)
+
3  * Copyright 2023 MINRES Technologies GmbH
+
4  *
+
5  * Licensed under the Apache License, Version 2.0 (the "License");
+
6  * you may not use this file except in compliance with the License.
+
7  * You may obtain a copy of the License at
+
8  *
+
9  * http://www.apache.org/licenses/LICENSE-2.0
+
10  *
+
11  * Unless required by applicable law or agreed to in writing, software
+
12  * distributed under the License is distributed on an "AS IS" BASIS,
+
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
14  * See the License for the specific language governing permissions and
+
15  * limitations under the License.
+
16  *******************************************************************************/
+
17 /*
+
18  * Created on: Dec 17, 2023
+
19  * Author: eyck
+
20  */
+
21 
+
22 #ifndef _SYSC_SCC_OPT_SIGNAL_PORTS_H_
+
23 #define _SYSC_SCC_OPT_SIGNAL_PORTS_H_
+
24 
+
25 #include "sysc/communication/sc_event_finder.h"
+
26 #include "sysc/communication/sc_port.h"
+
27 #include "sysc/communication/sc_signal_ifs.h"
+
28 #include "sysc/datatypes/bit/sc_logic.h"
+
29 #include "sysc/tracing/sc_trace.h"
+
30 
+
31 #if !defined(SC_DISABLE_VIRTUAL_BIND)
+
32 #define SCC_VIRT virtual
+
33 #else
+
34 #define SCC_VIRT /* non-virtual */
+
35 #endif
+
36 
+
37 namespace scc {
+
38 
+
39 template <class T> class sc_in_opt : public sc_core::sc_port<sc_core::sc_signal_in_if<T>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
40 public:
+
41  typedef T data_type;
+
42 
+
43  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
44  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
45  typedef sc_in_opt<data_type> this_type;
+
46  typedef typename base_type::port_type base_port_type;
+
47 
+
48  typedef if_type in_if_type;
+
49  typedef base_type in_port_type;
+
50  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
51  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
52 
+
53 public:
+
54  sc_in_opt()
+
55  : base_type() {}
+
56 
+
57  explicit sc_in_opt(const char* name_)
+
58  : base_type(name_) {}
+
59 
+
60  explicit sc_in_opt(const in_if_type& interface_)
+
61  : base_type(const_cast<in_if_type&>(interface_)) {}
+
62 
+
63  sc_in_opt(const char* name_, const in_if_type& interface_)
+
64  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
65 
+
66  explicit sc_in_opt(in_port_type& parent_)
+
67  : base_type(parent_) {}
+
68 
+
69  sc_in_opt(const char* name_, in_port_type& parent_)
+
70  : base_type(name_, parent_) {}
+
71 
+
72  explicit sc_in_opt(inout_port_type& parent_)
+
73  : base_type() {
+
74  sc_core::sc_port_base::bind(parent_);
+
75  }
+
76 
+
77  sc_in_opt(const char* name_, inout_port_type& parent_)
+
78  : base_type(name_) {
+
79  sc_core::sc_port_base::bind(parent_);
+
80  }
+
81 
+
82  sc_in_opt(this_type& parent_)
+
83  : base_type(parent_) {}
+
84 
+
85  sc_in_opt(const char* name_, this_type& parent_)
+
86  : base_type(name_, parent_) {}
+
87 
+
88  sc_in_opt(const this_type&) = delete;
+
89 
+
90  virtual ~sc_in_opt() {}
+
91 
+
92  this_type& operator=(const this_type&) = delete;
+
93 
+
94  SCC_VIRT void bind(const in_if_type& interface_) { sc_core::sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
95 
+
96  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
97 
+
98  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
99 
+
100  SCC_VIRT void bind(in_port_type& parent_) { sc_core::sc_port_base::bind(parent_); }
+
101 
+
102  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
103 
+
104  SCC_VIRT void bind(inout_port_type& parent_) { sc_core::sc_port_base::bind(parent_); }
+
105 
+
106  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
107 
+
108  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
109 
+
110  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
111 
+
112  const data_type& read() const { return (*this)->read(); }
+
113 
+
114  operator const data_type&() const { return (*this)->read(); }
+
115 
+
116  bool event() const { return (*this)->event(); }
+
117 
+
118  virtual const char* kind() const { return "sc_in"; }
+
119 };
+
120 
+
121 template <typename T>::std::ostream& operator<<(::std::ostream& os, const sc_in_opt<T>& a) { return os << a->read(); }
+
122 } // namespace scc
+
123 
+
124 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
125 
+
126 namespace scc {
+
127 template <> class SC_API sc_in_opt<bool> : public sc_core::sc_port<sc_core::sc_signal_in_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
128 public:
+
129  typedef bool data_type;
+
130 
+
131  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
132  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
133  typedef sc_in_opt<data_type> this_type;
+
134  typedef /* typename */ base_type::port_type base_port_type;
+
135 
+
136  typedef if_type in_if_type;
+
137  typedef base_type in_port_type;
+
138  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
139  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
140 
+
141 public:
+
142  sc_in_opt()
+
143  : base_type() {}
+
144 
+
145  explicit sc_in_opt(const char* name_)
+
146  : base_type(name_) {}
+
147 
+
148  explicit sc_in_opt(const in_if_type& interface_)
+
149  : base_type(const_cast<in_if_type&>(interface_)) {}
+
150 
+
151  sc_in_opt(const char* name_, const in_if_type& interface_)
+
152  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
153 
+
154  explicit sc_in_opt(in_port_type& parent_)
+
155  : base_type(parent_) {}
+
156 
+
157  sc_in_opt(const char* name_, in_port_type& parent_)
+
158  : base_type(name_, parent_) {}
+
159 
+
160  explicit sc_in_opt(inout_port_type& parent_)
+
161  : base_type() {
+
162  sc_port_base::bind(parent_);
+
163  }
+
164 
+
165  sc_in_opt(const char* name_, inout_port_type& parent_)
+
166  : base_type(name_) {
+
167  sc_port_base::bind(parent_);
+
168  }
+
169 
+
170  sc_in_opt(this_type& parent_)
+
171  : base_type(parent_) {}
+
172 
+
173  sc_in_opt(const char* name_, this_type& parent_)
+
174  : base_type(name_, parent_) {}
+
175 
+
176  sc_in_opt(const this_type&) = delete;
+
177 
+
178  virtual ~sc_in_opt() = default;
+
179 
+
180  this_type& operator=(const this_type&) = delete;
+
181 
+
182  SCC_VIRT void bind(const in_if_type& interface_) { sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
183 
+
184  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
185 
+
186  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
187 
+
188  SCC_VIRT void bind(in_port_type& parent_) { sc_port_base::bind(parent_); }
+
189 
+
190  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
191 
+
192  SCC_VIRT void bind(inout_port_type& parent_) { sc_port_base::bind(parent_); }
+
193 
+
194  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
195 
+
196  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
197 
+
198  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
199 
+
200  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
201 
+
202  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
203 
+
204  const data_type& read() const { return (*this)->read(); }
+
205 
+
206  operator const data_type&() const { return (*this)->read(); }
+
207 
+
208  bool event() const { return (*this)->event(); }
+
209 
+
210  bool posedge() const { return (*this)->posedge(); }
+
211 
+
212  bool negedge() const { return (*this)->negedge(); }
+
213 
+
214  virtual const char* kind() const { return "sc_in"; }
+
215 };
+
216 
+
217 } // namespace scc
+
218 
+
219 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
220 
+
221 namespace scc {
+
222 template <>
+
223 class SC_API sc_in_opt<sc_dt::sc_logic>
+
224 : public sc_core::sc_port<sc_core::sc_signal_in_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
225 public:
+
226  typedef sc_dt::sc_logic data_type;
+
227 
+
228  typedef sc_core::sc_signal_in_if<data_type> if_type;
+
229  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
230  typedef sc_in_opt<data_type> this_type;
+
231  typedef /* typename */ base_type::port_type base_port_type;
+
232 
+
233  typedef if_type in_if_type;
+
234  typedef base_type in_port_type;
+
235  typedef sc_core::sc_signal_inout_if<data_type> inout_if_type;
+
236  typedef sc_core::sc_port<inout_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> inout_port_type;
+
237 
+
238 public:
+
239  sc_in_opt()
+
240  : base_type() {}
+
241 
+
242  explicit sc_in_opt(const char* name_)
+
243  : base_type(name_) {}
+
244 
+
245  explicit sc_in_opt(const in_if_type& interface_)
+
246  : base_type(const_cast<in_if_type&>(interface_)) {}
+
247 
+
248  sc_in_opt(const char* name_, const in_if_type& interface_)
+
249  : base_type(name_, const_cast<in_if_type&>(interface_)) {}
+
250 
+
251  explicit sc_in_opt(in_port_type& parent_)
+
252  : base_type(parent_) {}
+
253 
+
254  sc_in_opt(const char* name_, in_port_type& parent_)
+
255  : base_type(name_, parent_) {}
+
256 
+
257  explicit sc_in_opt(inout_port_type& parent_)
+
258  : base_type() {
+
259  sc_port_base::bind(parent_);
+
260  }
+
261 
+
262  sc_in_opt(const char* name_, inout_port_type& parent_)
+
263  : base_type(name_) {
+
264  sc_port_base::bind(parent_);
+
265  }
+
266 
+
267  sc_in_opt(this_type& parent_)
+
268  : base_type(parent_) {}
+
269 
+
270  sc_in_opt(const char* name_, this_type& parent_)
+
271  : base_type(name_, parent_) {}
+
272 
+
273  sc_in_opt(const this_type&) = delete;
+
274 
+
275  virtual ~sc_in_opt() = default;
+
276 
+
277  this_type& operator=(const this_type&) = delete;
+
278 
+
279  SCC_VIRT void bind(const in_if_type& interface_) { sc_port_base::bind(const_cast<in_if_type&>(interface_)); }
+
280 
+
281  SCC_VIRT void bind(in_if_type& interface_) { this->bind(const_cast<const in_if_type&>(interface_)); }
+
282 
+
283  void operator()(const in_if_type& interface_) { this->bind(interface_); }
+
284 
+
285  SCC_VIRT void bind(in_port_type& parent_) { sc_port_base::bind(parent_); }
+
286 
+
287  void operator()(in_port_type& parent_) { this->bind(parent_); }
+
288 
+
289  SCC_VIRT void bind(inout_port_type& parent_) { sc_port_base::bind(parent_); }
+
290 
+
291  void operator()(inout_port_type& parent_) { this->bind(parent_); }
+
292 
+
293  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
294 
+
295  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
296 
+
297  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
298 
+
299  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
300 
+
301  const data_type& read() const { return (*this)->read(); }
+
302 
+
303  operator const data_type&() const { return (*this)->read(); }
+
304 
+
305  bool event() const { return (*this)->event(); }
+
306 
+
307  bool posedge() const { return (*this)->posedge(); }
+
308 
+
309  bool negedge() const { return (*this)->negedge(); }
+
310 
+
311  virtual const char* kind() const { return "sc_in"; }
+
312 };
+
313 
+
314 template <class T> class sc_inout_opt : public sc_core::sc_port<sc_core::sc_signal_inout_if<T>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
315 public:
+
316  typedef T data_type;
+
317 
+
318  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
319  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
320  typedef sc_inout_opt<data_type> this_type;
+
321 
+
322  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
323  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
324  typedef if_type inout_if_type;
+
325  typedef base_type inout_port_type;
+
326 
+
327 public:
+
328  sc_inout_opt()
+
329  : base_type()
+
330  , m_init_val(0) {}
+
331 
+
332  explicit sc_inout_opt(const char* name_)
+
333  : base_type(name_)
+
334  , m_init_val(0) {}
+
335 
+
336  explicit sc_inout_opt(inout_if_type& interface_)
+
337  : base_type(interface_)
+
338  , m_init_val(0) {}
+
339 
+
340  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
341  : base_type(name_, interface_)
+
342  , m_init_val(0) {}
+
343 
+
344  explicit sc_inout_opt(inout_port_type& parent_)
+
345  : base_type(parent_)
+
346  , m_init_val(0) {}
+
347 
+
348  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
349  : base_type(name_, parent_)
+
350  , m_init_val(0) {}
+
351 
+
352  sc_inout_opt(this_type& parent_)
+
353  : base_type(parent_)
+
354  , m_init_val(0) {}
+
355 
+
356  sc_inout_opt(const char* name_, this_type& parent_)
+
357  : base_type(name_, parent_)
+
358  , m_init_val(0) {}
+
359 
+
360  sc_inout_opt(const this_type&) = delete;
+
361 
+
362  virtual ~sc_inout_opt() = default;
+
363 
+
364  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
365 
+
366  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
367 
+
368  const data_type& read() const { return (*this)->read(); }
+
369 
+
370  operator const data_type&() const { return (*this)->read(); }
+
371 
+
372  bool event() const { return (*this)->event(); }
+
373 
+
374  void write(const data_type& value_) { (*this)->write(value_); }
+
375 
+
376  this_type& operator=(const data_type& value_) {
+
377  (*this)->write(value_);
+
378  return *this;
+
379  }
+
380 
+
381  this_type& operator=(const in_if_type& interface_) {
+
382  (*this)->write(interface_.read());
+
383  return *this;
+
384  }
+
385 
+
386  this_type& operator=(const in_port_type& port_) {
+
387  (*this)->write(port_->read());
+
388  return *this;
+
389  }
+
390 
+
391  this_type& operator=(const inout_port_type& port_) {
+
392  (*this)->write(port_->read());
+
393  return *this;
+
394  }
+
395 
+
396  this_type& operator=(const this_type& port_) {
+
397  (*this)->write(port_->read());
+
398  return *this;
+
399  }
+
400 
+
401  void initialize(const data_type& value_);
+
402 
+
403  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
404 
+
405  void end_of_elaboration() override;
+
406 
+
407  virtual const char* kind() const { return "sc_inout"; }
+
408 
+
409 protected:
+
410  data_type* m_init_val;
+
411 };
+
412 
+
413 template <typename T>::std::ostream& operator<<(::std::ostream& os, const sc_inout_opt<T>& a) { return os << a->read(); }
+
414 
+
415 template <class T> inline void sc_inout_opt<T>::initialize(const data_type& value_) {
+
416  inout_if_type* iface = dynamic_cast<inout_if_type*>(this->get_interface());
+
417  if(iface != 0) {
+
418  iface->write(value_);
+
419  } else {
+
420  if(m_init_val == 0) {
+
421  m_init_val = new data_type;
+
422  }
+
423  *m_init_val = value_;
+
424  }
+
425 }
+
426 
+
427 template <class T> inline void sc_inout_opt<T>::end_of_elaboration() {
+
428  if(m_init_val != 0) {
+
429  write(*m_init_val);
+
430  delete m_init_val;
+
431  m_init_val = 0;
+
432  }
+
433 }
+
434 } // namespace scc
+
435 
+
436 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
437 
+
438 namespace scc {
+
439 template <>
+
440 class SC_API sc_inout_opt<bool> : public sc_core::sc_port<sc_core::sc_signal_inout_if<bool>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
441 public:
+
442  typedef bool data_type;
+
443 
+
444  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
445  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
446  typedef sc_inout_opt<data_type> this_type;
+
447 
+
448  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
449  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
450  typedef if_type inout_if_type;
+
451  typedef base_type inout_port_type;
+
452 
+
453 public:
+
454  sc_inout_opt()
+
455  : base_type()
+
456  , m_init_val(0) {}
+
457 
+
458  explicit sc_inout_opt(const char* name_)
+
459  : base_type(name_)
+
460  , m_init_val(0) {}
+
461 
+
462  explicit sc_inout_opt(inout_if_type& interface_)
+
463  : base_type(interface_)
+
464  , m_init_val(0) {}
+
465 
+
466  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
467  : base_type(name_, interface_)
+
468  , m_init_val(0) {}
+
469 
+
470  explicit sc_inout_opt(inout_port_type& parent_)
+
471  : base_type(parent_)
+
472  , m_init_val(0) {}
+
473 
+
474  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
475  : base_type(name_, parent_)
+
476  , m_init_val(0) {}
+
477 
+
478  sc_inout_opt(this_type& parent_)
+
479  : base_type(parent_)
+
480  , m_init_val(0) {}
+
481 
+
482  sc_inout_opt(const char* name_, this_type& parent_)
+
483  : base_type(name_, parent_)
+
484  , m_init_val(0) {}
+
485 
+
486  sc_inout_opt(const this_type&) = delete;
+
487 
+
488  virtual ~sc_inout_opt() = default;
+
489 
+
490  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
491 
+
492  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
493 
+
494  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
495 
+
496  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
497 
+
498  const data_type& read() const { return (*this)->read(); }
+
499 
+
500  operator const data_type&() const { return (*this)->read(); }
+
501 
+
502  bool event() const { return (*this)->event(); }
+
503 
+
504  bool posedge() const { return (*this)->posedge(); }
+
505 
+
506  bool negedge() const { return (*this)->negedge(); }
+
507 
+
508  void write(const data_type& value_) { (*this)->write(value_); }
+
509 
+
510  this_type& operator=(const data_type& value_) {
+
511  (*this)->write(value_);
+
512  return *this;
+
513  }
+
514 
+
515  this_type& operator=(const in_if_type& interface_) {
+
516  (*this)->write(interface_.read());
+
517  return *this;
+
518  }
+
519 
+
520  this_type& operator=(const in_port_type& port_) {
+
521  (*this)->write(port_->read());
+
522  return *this;
+
523  }
+
524 
+
525  this_type& operator=(const inout_port_type& port_) {
+
526  (*this)->write(port_->read());
+
527  return *this;
+
528  }
+
529 
+
530  this_type& operator=(const this_type& port_) {
+
531  (*this)->write(port_->read());
+
532  return *this;
+
533  }
+
534 
+
535  void initialize(const data_type& value_);
+
536 
+
537  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
538 
+
539  void end_of_elaboration() override {
+
540  if(m_init_val != 0) {
+
541  write(*m_init_val);
+
542  delete m_init_val;
+
543  m_init_val = 0;
+
544  }
+
545  }
+
546 
+
547  virtual const char* kind() const { return "sc_inout"; }
+
548 
+
549 protected:
+
550  data_type* m_init_val;
+
551 };
+
552 } // namespace scc
+
553 
+
554 SC_API_TEMPLATE_DECL_ sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND>;
+
555 
+
556 namespace scc {
+
557 template <>
+
558 class SC_API sc_inout_opt<sc_dt::sc_logic>
+
559 : public sc_core::sc_port<sc_core::sc_signal_inout_if<sc_dt::sc_logic>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> {
+
560 public:
+
561  typedef sc_dt::sc_logic data_type;
+
562 
+
563  typedef sc_core::sc_signal_inout_if<data_type> if_type;
+
564  typedef sc_core::sc_port<if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> base_type;
+
565  typedef sc_inout_opt<data_type> this_type;
+
566 
+
567  typedef sc_core::sc_signal_in_if<data_type> in_if_type;
+
568  typedef sc_core::sc_port<in_if_type, 1, sc_core::SC_ZERO_OR_MORE_BOUND> in_port_type;
+
569  typedef if_type inout_if_type;
+
570  typedef base_type inout_port_type;
+
571 
+
572 public:
+
573  sc_inout_opt()
+
574  : base_type()
+
575  , m_init_val(0) {}
+
576 
+
577  explicit sc_inout_opt(const char* name_)
+
578  : base_type(name_)
+
579  , m_init_val(0) {}
+
580 
+
581  explicit sc_inout_opt(inout_if_type& interface_)
+
582  : base_type(interface_)
+
583  , m_init_val(0) {}
+
584 
+
585  sc_inout_opt(const char* name_, inout_if_type& interface_)
+
586  : base_type(name_, interface_)
+
587  , m_init_val(0) {}
+
588 
+
589  explicit sc_inout_opt(inout_port_type& parent_)
+
590  : base_type(parent_)
+
591  , m_init_val(0) {}
+
592 
+
593  sc_inout_opt(const char* name_, inout_port_type& parent_)
+
594  : base_type(name_, parent_)
+
595  , m_init_val(0) {}
+
596 
+
597  sc_inout_opt(this_type& parent_)
+
598  : base_type(parent_)
+
599  , m_init_val(0) {}
+
600 
+
601  sc_inout_opt(const char* name_, this_type& parent_)
+
602  : base_type(name_, parent_)
+
603  , m_init_val(0) {}
+
604 
+
605  sc_inout_opt(const this_type&) = delete;
+
606 
+
607  virtual ~sc_inout_opt();
+
608 
+
609  const sc_core::sc_event& default_event() const { return (*this)->default_event(); }
+
610 
+
611  const sc_core::sc_event& value_changed_event() const { return (*this)->value_changed_event(); }
+
612 
+
613  const sc_core::sc_event& posedge_event() const { return (*this)->posedge_event(); }
+
614 
+
615  const sc_core::sc_event& negedge_event() const { return (*this)->negedge_event(); }
+
616 
+
617  const data_type& read() const { return (*this)->read(); }
+
618 
+
619  operator const data_type&() const { return (*this)->read(); }
+
620 
+
621  bool event() const { return (*this)->event(); }
+
622 
+
623  bool posedge() const { return (*this)->posedge(); }
+
624 
+
625  bool negedge() const { return (*this)->negedge(); }
+
626 
+
627  void write(const data_type& value_) { (*this)->write(value_); }
+
628 
+
629  this_type& operator=(const data_type& value_) {
+
630  (*this)->write(value_);
+
631  return *this;
+
632  }
+
633 
+
634  this_type& operator=(const in_if_type& interface_) {
+
635  (*this)->write(interface_.read());
+
636  return *this;
+
637  }
+
638 
+
639  this_type& operator=(const in_port_type& port_) {
+
640  (*this)->write(port_->read());
+
641  return *this;
+
642  }
+
643 
+
644  this_type& operator=(const inout_port_type& port_) {
+
645  (*this)->write(port_->read());
+
646  return *this;
+
647  }
+
648 
+
649  this_type& operator=(const this_type& port_) {
+
650  (*this)->write(port_->read());
+
651  return *this;
+
652  }
+
653 
+
654  void initialize(const data_type& value_);
+
655 
+
656  void initialize(const in_if_type& interface_) { initialize(interface_.read()); }
+
657 
+
658  // called when elaboration is done
+
659  void end_of_elaboration() override {
+
660  if(m_init_val != 0) {
+
661  write(*m_init_val);
+
662  delete m_init_val;
+
663  m_init_val = 0;
+
664  }
+
665  }
+
666 
+
667  virtual const char* kind() const { return "sc_inout"; }
+
668 
+
669 protected:
+
670  data_type* m_init_val;
+
671 };
+
672 
+
673 template <class T> class sc_out_opt : public sc_inout_opt<T> {
+
674 public:
+
675  typedef T data_type;
+
676 
+
677  typedef sc_out_opt<data_type> this_type;
+
678  typedef sc_inout_opt<data_type> base_type;
+
679 
+
680  typedef typename base_type::in_if_type in_if_type;
+
681  typedef typename base_type::in_port_type in_port_type;
+
682  typedef typename base_type::inout_if_type inout_if_type;
+
683  typedef typename base_type::inout_port_type inout_port_type;
+
684 
+
685 public:
+
686  sc_out_opt()
+
687  : base_type() {}
+
688 
+
689  explicit sc_out_opt(const char* name_)
+
690  : base_type(name_) {}
+
691 
+
692  explicit sc_out_opt(inout_if_type& interface_)
+
693  : base_type(interface_) {}
+
694 
+
695  sc_out_opt(const char* name_, inout_if_type& interface_)
+
696  : base_type(name_, interface_) {}
+
697 
+
698  explicit sc_out_opt(inout_port_type& parent_)
+
699  : base_type(parent_) {}
+
700 
+
701  sc_out_opt(const char* name_, inout_port_type& parent_)
+
702  : base_type(name_, parent_) {}
+
703 
+
704  sc_out_opt(this_type& parent_)
+
705  : base_type(parent_) {}
+
706 
+
707  sc_out_opt(const char* name_, this_type& parent_)
+
708  : base_type(name_, parent_) {}
+
709 
+
710  virtual ~sc_out_opt() {}
+
711 
+
712  this_type& operator=(const data_type& value_) {
+
713  (*this)->write(value_);
+
714  return *this;
+
715  }
+
716 
+
717  this_type& operator=(const in_if_type& interface_) {
+
718  (*this)->write(interface_.read());
+
719  return *this;
+
720  }
+
721 
+
722  this_type& operator=(const in_port_type& port_) {
+
723  (*this)->write(port_->read());
+
724  return *this;
+
725  }
+
726 
+
727  this_type& operator=(const inout_port_type& port_) {
+
728  (*this)->write(port_->read());
+
729  return *this;
+
730  }
+
731 
+
732  this_type& operator=(const this_type& port_) {
+
733  (*this)->write(port_->read());
+
734  return *this;
+
735  }
+
736 
+
737  virtual const char* kind() const { return "sc_out"; }
+
738 
+
739 private:
+
740  sc_out_opt(const this_type&) = delete;
+
741 };
+
742 
+
743 template <class T> inline void sc_trace(sc_core::sc_trace_file* tf, const sc_in_opt<T>& port, const std::string& name) {
+
744  const sc_core::sc_signal_in_if<T>* iface = 0;
+
745  if(sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+
746  iface = dynamic_cast<const sc_core::sc_signal_in_if<T>*>(port.get_interface());
+
747  }
+
748  if(iface)
+
749  sc_trace(tf, iface->read(), name);
+
750  else
+
751  port.add_trace_internal(tf, name);
+
752 }
+
753 
+
754 template <class T> inline void sc_trace(sc_core::sc_trace_file* tf, const sc_inout_opt<T>& port, const std::string& name) {
+
755  const sc_core::sc_signal_in_if<T>* iface = 0;
+
756  if(sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+
757  iface = dynamic_cast<const sc_core::sc_signal_in_if<T>*>(port.get_interface());
+
758  }
+
759 
+
760  if(iface)
+
761  sc_trace(tf, iface->read(), name);
+
762  else
+
763  port.add_trace_internal(tf, name);
+
764 }
+
765 
+
766 } // namespace scc
+
767 
+
768 #undef SCC_VIRT
+
769 
+
770 #if defined(_MSC_VER) && !defined(SC_WIN_DLL_WARN)
+
771 #pragma warning(pop)
+
772 #endif
+
773 #endif /* SCC_SRC_SYSC_SCC_OPT_SIGNAL_PORTS_H_ */
+
scc::sc_in_opt
Definition: signal_opt_ports.h:39
+
scc::sc_inout_opt
Definition: signal_opt_ports.h:314
+
scc::sc_out_opt
Definition: signal_opt_ports.h:673
+
scc
SCC SystemC utilities.
Definition: clock_if_mixins.h:25
+
scc::operator<<
std::ostream & operator<<(std::ostream &os, log const &val)
output the textual representation of the log level
Definition: report.h:124
+
+
+ + + + diff --git a/main/simple__ace__target_8h_source.html b/main/simple__ace__target_8h_source.html new file mode 100644 index 00000000..ccdcbc48 --- /dev/null +++ b/main/simple__ace__target_8h_source.html @@ -0,0 +1,149 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/simple_ace_target.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
simple_ace_target.h
+
+
+
1 /*
+
2  * Copyright 2020 Arteris IP
+
3  *
+
4  * Licensed under the Apache License, Version 2.0 (the "License");
+
5  * you may not use this file except in compliance with the License.
+
6  * You may obtain a copy of the License at
+
7  *
+
8  * http://www.apache.org/licenses/LICENSE-2.0
+
9  *
+
10  * Unless required by applicable law or agreed to in writing, software
+
11  * distributed under the License is distributed on an "AS IS" BASIS,
+
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+
13  * See the License for the specific language governing permissions and
+
14  * limitations under the License.axi_util.cpp
+
15  */
+
16 
+
17 #pragma once
+
18 
+
19 #include <axi/pe/ace_target_pe.h>
+
20 
+
22 namespace axi {
+
24 namespace pe {
+
25 
+
26 
+
27 template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
+
28  sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
+
29 class simple_ace_target : public ace_target_pe {
+
30 public:
+
31  using base = ace_target_pe;
+
32  using payload_type = base::payload_type;
+
33  using phase_type = base::phase_type;
+
34 
+
39  simple_ace_target(axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket)
+
40  : // @suppress("Class members should be properly initialized")
+
41  simple_ace_target(sc_core::sc_gen_unique_name("simple_ace_target"), socket) {}
+
42 
+
43  simple_ace_target(const sc_core::sc_module_name& nm, axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket)
+
44  : ace_target_pe(nm, BUSWIDTH)
+
45  , socket(socket) {
+
46  socket(*this);
+
47  this->instance_name = name();
+
48  }
+
49 
+
50  simple_ace_target() = delete;
+
51 
+
52  simple_ace_target(simple_ace_target const&) = delete;
+
53 
+
54  simple_ace_target(simple_ace_target&&) = delete;
+
55 
+
56  simple_ace_target& operator=(simple_ace_target const&) = delete;
+
57 
+
58  simple_ace_target& operator=(simple_ace_target&&) = delete;
+
59 
+
60 protected:
+
61  axi::ace_target_socket<BUSWIDTH, TYPES, N, POL>& socket;
+
62 
+
63  void end_of_elaboration(){
+
64  base::end_of_elaboration();
+
65  set_bw_interface(socket.get_base_port().operator -> ());
+
66  }
+
67 };
+
68 
+
69 } // namespace pe
+
70 } // namespace axi
+
axi::pe::ace_target_pe
Definition: ace_target_pe.h:44
+
axi::pe::simple_ace_target
Definition: simple_ace_target.h:29
+
axi::pe::simple_ace_target::simple_ace_target
simple_ace_target(axi::ace_target_socket< BUSWIDTH, TYPES, N, POL > &socket)
the constructor
Definition: simple_ace_target.h:39
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
axi::ace_target_socket
Definition: axi_tlm.h:1031
+
axi::axi_protocol_types
The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicate...
Definition: axi_tlm.h:890
+
axi::fsm::base::payload_type
axi::axi_protocol_types::tlm_payload_type payload_type
aliases used in the class
Definition: base.h:45
+
+
+ + + + diff --git a/main/structace__target__pe_1_1bw__intor__impl-members.html b/main/structace__target__pe_1_1bw__intor__impl-members.html new file mode 100644 index 00000000..7c0130e4 --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::pe::ace_target_pe::bw_intor_impl Member List
+
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+ +

This is the complete list of members for axi::pe::ace_target_pe::bw_intor_impl, including all inherited members.

+ + + + +
bw_intor_impl(ace_target_pe *that) (defined in axi::pe::ace_target_pe::bw_intor_impl)axi::pe::ace_target_pe::bw_intor_implinline
that (defined in axi::pe::ace_target_pe::bw_intor_impl)axi::pe::ace_target_pe::bw_intor_impl
transport(tlm::tlm_generic_payload &payload) overrideaxi::pe::ace_target_pe::bw_intor_implinlinevirtual
+
+ + + + diff --git a/main/structace__target__pe_1_1bw__intor__impl.html b/main/structace__target__pe_1_1bw__intor__impl.html new file mode 100644 index 00000000..36066abd --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl.html @@ -0,0 +1,179 @@ + + + + + + + +scc: axi::pe::ace_target_pe::bw_intor_impl Struct Reference + + + + + + + + + + + +
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scc +  2022.4.0 +
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SystemC components library
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+Public Member Functions | +Public Attributes | +List of all members
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axi::pe::ace_target_pe::bw_intor_impl Struct Reference
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+Inheritance diagram for axi::pe::ace_target_pe::bw_intor_impl:
+
+
Inheritance graph
+ + + + + + +
[legend]
+
+Collaboration diagram for axi::pe::ace_target_pe::bw_intor_impl:
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Collaboration graph
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[legend]
+ + + + + + +

+Public Member Functions

+ bw_intor_impl (ace_target_pe *that)
 
unsigned transport (tlm::tlm_generic_payload &payload) override
 
+ + + +

+Public Attributes

+ace_target_pe *const that
 
+

Detailed Description

+
+

Definition at line 38 of file ace_target_pe.cpp.

+

Member Function Documentation

+ +

◆ transport()

+ +
+
+ + + + + +
+ + + + + + + + +
unsigned axi::pe::ace_target_pe::bw_intor_impl::transport (tlm::tlm_generic_payload & payload)
+ 		+inlineoverridevirtual
+
+

callback from the pe top if there is a backward transaction e.g. a snoop

+
Parameters
+ + +
payloadobject with (optional) extensions return the latency until reponse is sent by the protocol engine
+
+
+ +

Implements tlm::scc::pe::intor_bw< type::NB >.

+ +

Definition at line 42 of file ace_target_pe.cpp.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structace__target__pe_1_1bw__intor__impl.js b/main/structace__target__pe_1_1bw__intor__impl.js new file mode 100644 index 00000000..ce1949ac --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl.js @@ -0,0 +1,6 @@ +var structace__target__pe_1_1bw__intor__impl = +[ + [ "bw_intor_impl", "structace__target__pe_1_1bw__intor__impl.html#a99569fc326770365b9844b3ce154cfe4", null ], + [ "transport", "structace__target__pe_1_1bw__intor__impl.html#a90ed1a3696a519297b09babd152dd046", null ], + [ "that", "structace__target__pe_1_1bw__intor__impl.html#aebe7f1b2a24d09f05ed1691c08a239ba", null ] +]; \ No newline at end of file diff --git a/main/structace__target__pe_1_1bw__intor__impl__coll__graph.map b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.map new file mode 100644 index 00000000..f7da658a --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.map @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/main/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 new file mode 100644 index 00000000..f104b799 --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.md5 @@ -0,0 +1 @@ +82ac6046c0e9c7e3fc1a54c7d9f8a466 \ No newline at end of file diff --git a/main/structace__target__pe_1_1bw__intor__impl__coll__graph.png b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.png new file mode 100644 index 00000000..bdcb251e Binary files /dev/null and b/main/structace__target__pe_1_1bw__intor__impl__coll__graph.png differ diff --git a/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.map b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.map new file mode 100644 index 00000000..0c30f2e7 --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 new file mode 100644 index 00000000..7f21655e --- /dev/null +++ b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.md5 @@ -0,0 +1 @@ +82cb9a46a71dc54713dfbe73ce543aea \ No newline at end of file diff --git a/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.png b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.png new file mode 100644 index 00000000..7de8ba40 Binary files /dev/null and b/main/structace__target__pe_1_1bw__intor__impl__inherit__graph.png differ diff --git a/main/structahb_1_1enable__for__enum-members.html b/main/structahb_1_1enable__for__enum-members.html new file mode 100644 index 00000000..13a8785e --- /dev/null +++ b/main/structahb_1_1enable__for__enum-members.html @@ -0,0 +1,81 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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ahb::enable_for_enum< Enum > Member List
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This is the complete list of members for ahb::enable_for_enum< Enum >, including all inherited members.

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value (defined in ahb::enable_for_enum< Enum >)ahb::enable_for_enum< Enum >static
+
+ + + + diff --git a/main/structahb_1_1enable__for__enum.html b/main/structahb_1_1enable__for__enum.html new file mode 100644 index 00000000..00291178 --- /dev/null +++ b/main/structahb_1_1enable__for__enum.html @@ -0,0 +1,100 @@ + + + + + + + +scc: ahb::enable_for_enum< Enum > Struct Template Reference + + + + + + + + + + + +
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scc +  2022.4.0 +
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ahb::enable_for_enum< Enum > Struct Template Reference
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#include <ahb_tlm.h>

+ + + + +

+Static Public Attributes

+static const bool value = false
 
+

Detailed Description

+

template<typename Enum>
+struct ahb::enable_for_enum< Enum >

+ +

helper function to allow SFINAE

+ +

Definition at line 30 of file ahb_tlm.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ac__ace-members.html b/main/structaxi_1_1ac__ace-members.html new file mode 100644 index 00000000..b872da6b --- /dev/null +++ b/main/structaxi_1_1ac__ace-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::ac_ace< CFG, TYPES > Member List
+
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+ +

This is the complete list of members for axi::ac_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + +
ac_ace()=default (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >inline
ac_addr (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_prot (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_ready (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_snoop (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_trace (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_valid (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
ac_vmidext (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, TYPES >)axi::ac_ace< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1ac__ace.html b/main/structaxi_1_1ac__ace.html new file mode 100644 index 00000000..4684e1fd --- /dev/null +++ b/main/structaxi_1_1ac__ace.html @@ -0,0 +1,132 @@ + + + + + + + +scc: axi::ac_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
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+Public Member Functions | +Public Attributes | +List of all members
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axi::ac_ace< CFG, TYPES > Struct Template Reference
+
+
+ +

snoop address(AC) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ ac_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ac (ac_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > ac_valid {"ac_valid"}
 
+TYPES::template m2s_t< bool > ac_ready {"ac_ready"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr {"ac_addr"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop {"ac_snoop"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot {"ac_prot"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext {"ac_vmidext"}
 
+TYPES::template s2m_opt_t< bool > ac_trace {"ac_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ac_ace< CFG, TYPES >

+ +

snoop address(AC) channel signals

+ +

Definition at line 629 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ac__ace.js b/main/structaxi_1_1ac__ace.js new file mode 100644 index 00000000..78d6b7a5 --- /dev/null +++ b/main/structaxi_1_1ac__ace.js @@ -0,0 +1,13 @@ +var structaxi_1_1ac__ace = +[ + [ "ac_ace", "structaxi_1_1ac__ace.html#a7f12a6f26a78eb889b8781f3b628807a", null ], + [ "ac_ace", "structaxi_1_1ac__ace.html#a205a0442d29ba62d0091e87db7456fee", null ], + [ "bind_ac", "structaxi_1_1ac__ace.html#a99c00143c3549fbe9243150371eed801", null ], + [ "ac_addr", "structaxi_1_1ac__ace.html#a12e62c4e4093cd4781a72044c1fc41d9", null ], + [ "ac_prot", "structaxi_1_1ac__ace.html#ac7c27ec04577d0403244e8d1b0b384d7", null ], + [ "ac_ready", "structaxi_1_1ac__ace.html#a481ba2d3cfb5ba45c25c91280819397c", null ], + [ "ac_snoop", "structaxi_1_1ac__ace.html#abbdc4b67011cb8c1233e4620c4a8eac4", null ], + [ "ac_trace", "structaxi_1_1ac__ace.html#a1ca7353b7d234a60cd312c16d8d5dca0", null ], + [ "ac_valid", "structaxi_1_1ac__ace.html#a41e8de8b8cad6c59c90ec3ce22db01d7", null ], + [ "ac_vmidext", "structaxi_1_1ac__ace.html#abaad313f5f0621be668749e31b03fd26", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1ace__cfg-members.html b/main/structaxi_1_1ace__cfg-members.html new file mode 100644 index 00000000..a7a099d8 --- /dev/null +++ b/main/structaxi_1_1ace__cfg-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Member List
+
+
+ +

This is the complete list of members for axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >, including all inherited members.

+ + + + + + + + + + + +
ADDRWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
AWSNOOPWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
BUSWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
data_t typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
IDWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
IS_LITE (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
master_types typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
RESPWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
slave_types typedef (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >
USERWIDTH (defined in axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >)axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >static
+
+ + + + diff --git a/main/structaxi_1_1ace__cfg.html b/main/structaxi_1_1ace__cfg.html new file mode 100644 index 00000000..1291f722 --- /dev/null +++ b/main/structaxi_1_1ace__cfg.html @@ -0,0 +1,140 @@ + + + + + + + +scc: axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Struct Template Reference + + + + + + + + + + + +
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scc +  2022.4.0 +
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SystemC components library
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+Public Types | +Static Public Attributes | +List of all members
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axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH > Struct Template Reference
+
+
+ +

#include <signal_if.h>

+ + + + + + + + +

+Public Types

+using data_t = typename select_if< BUSWDTH<=64, sc_dt::sc_uint< BUSWIDTH >, sc_dt::sc_biguint< BUSWIDTH > >::type
 
+using slave_types = ::axi::slave_types
 
+using master_types = ::axi::master_types
 
+ + + + + + + + + + + + + + + +

+Static Public Attributes

+constexpr static bool IS_LITE = false
 
+constexpr static unsigned int BUSWIDTH = BUSWDTH
 
+constexpr static unsigned int ADDRWIDTH = ADDRWDTH
 
+constexpr static unsigned int IDWIDTH = IDWDTH
 
+constexpr static unsigned int USERWIDTH = USERWDTH
 
+constexpr static unsigned int AWSNOOPWIDTH = AWSNOOPWDTH
 
+constexpr static unsigned int RESPWIDTH = RESPWDTH
 
+

Detailed Description

+

template<unsigned int BUSWDTH = 32, unsigned int ADDRWDTH = 32, unsigned int IDWDTH = 32, unsigned int USERWDTH = 1, unsigned int AWSNOOPWDTH = 3, unsigned int RESPWDTH = 4>
+struct axi::ace_cfg< BUSWDTH, ADDRWDTH, IDWDTH, USERWDTH, AWSNOOPWDTH, RESPWDTH >

+ +
Template Parameters
+ + + + + + +
BUSWDTH
ADDRWDTH
IDWDTH
USERWDTH
CACHELINEcacheline size in Bytes, defaults value is 64 bytes
+
+
+ +

Definition at line 113 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ace__cfg.js b/main/structaxi_1_1ace__cfg.js new file mode 100644 index 00000000..b0332d08 --- /dev/null +++ b/main/structaxi_1_1ace__cfg.js @@ -0,0 +1,6 @@ +var structaxi_1_1ace__cfg = +[ + [ "data_t", "structaxi_1_1ace__cfg.html#aaa70a4bef1d89a1f227fe6c01d47c3b2", null ], + [ "master_types", "structaxi_1_1ace__cfg.html#acb32c494beb36754cc37b59f5d6d19ad", null ], + [ "slave_types", "structaxi_1_1ace__cfg.html#a78a51e9fafdc11aa1c95fe096288a8b5", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1ar__ace-members.html b/main/structaxi_1_1ar__ace-members.html new file mode 100644 index 00000000..25817697 --- /dev/null +++ b/main/structaxi_1_1ar__ace-members.html @@ -0,0 +1,101 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::ar_ace< CFG, TYPES > Member List
+
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+ +

This is the complete list of members for axi::ar_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + +
ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1ar__ace.html b/main/structaxi_1_1ar__ace.html new file mode 100644 index 00000000..4b35d7b4 --- /dev/null +++ b/main/structaxi_1_1ar__ace.html @@ -0,0 +1,169 @@ + + + + + + + +scc: axi::ar_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_ace< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::ar_ace< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + +

+Public Member Functions

+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ar_ace< CFG, TYPES >

+ + +

Definition at line 488 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ar__ace.js b/main/structaxi_1_1ar__ace.js new file mode 100644 index 00000000..65af5b95 --- /dev/null +++ b/main/structaxi_1_1ar__ace.js @@ -0,0 +1,24 @@ +var structaxi_1_1ar__ace = +[ + [ "ar_ace", "structaxi_1_1ar__ace.html#a90b881d35bc3488833b6cd55a98d4c4f", null ], + [ "ar_ace", "structaxi_1_1ar__ace.html#aecc3da273e810265e10acde32e938080", null ], + [ "bind_ar", "structaxi_1_1ar__ace.html#a537d522808054c2a6fda2d670b4d1cb9", null ], + [ "ar_addr", "structaxi_1_1ar__ace.html#a0ea04250093710e45ff17b00f75212b4", null ], + [ "ar_bar", "structaxi_1_1ar__ace.html#a5816b68546b33fbacced3b8dbde34b59", null ], + [ "ar_burst", "structaxi_1_1ar__ace.html#a17eb2d5684c969e223346b02d21e3836", null ], + [ "ar_cache", "structaxi_1_1ar__ace.html#a9ca24e158c57ac4907a62e1277e2b4df", null ], + [ "ar_domain", "structaxi_1_1ar__ace.html#a448022ff0d7125cc951e1cebe5846b64", null ], + [ "ar_id", "structaxi_1_1ar__ace.html#a1dfadab2afde4f4dc8051b3e9bdc4b0a", null ], + [ "ar_len", "structaxi_1_1ar__ace.html#a2eb71a5b9e3472016b25da6a341ce339", null ], + [ "ar_lock", "structaxi_1_1ar__ace.html#a67f5551e5b440323b0b27e5b1176507e", null ], + [ "ar_prot", "structaxi_1_1ar__ace.html#a5135b590c14902d99574caddb9dc53fc", null ], + [ "ar_qos", "structaxi_1_1ar__ace.html#a53d7554423db040830f93e63b7eb83d6", null ], + [ "ar_ready", "structaxi_1_1ar__ace.html#a93458ad756a0ba69d7a41ee02cd7f0df", null ], + [ "ar_region", "structaxi_1_1ar__ace.html#a3d5af287233effc36acd3e2c56347b8e", null ], + [ "ar_size", "structaxi_1_1ar__ace.html#a5857dbefcb30209dfbb5a8a1d5c790d1", null ], + [ "ar_snoop", "structaxi_1_1ar__ace.html#af14c027656574ad6f5b9574d7c4baf42", null ], + [ "ar_trace", "structaxi_1_1ar__ace.html#a6f8b3e19c552127f973c606eba66937b", null ], + [ "ar_user", "structaxi_1_1ar__ace.html#a6f41cad331ee6365c58190f423c3c7dc", null ], + [ "ar_valid", "structaxi_1_1ar__ace.html#a6309b646ad504d6b406dc75d3d0b9366", null ], + [ "ar_vmidext", "structaxi_1_1ar__ace.html#ac239789e2bc9463280c2f06774c39c8b", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1ar__ace__inherit__graph.map b/main/structaxi_1_1ar__ace__inherit__graph.map new file mode 100644 index 00000000..059f8ef9 --- /dev/null +++ b/main/structaxi_1_1ar__ace__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/main/structaxi_1_1ar__ace__inherit__graph.md5 b/main/structaxi_1_1ar__ace__inherit__graph.md5 new file mode 100644 index 00000000..430384b8 --- /dev/null +++ b/main/structaxi_1_1ar__ace__inherit__graph.md5 @@ -0,0 +1 @@ +dff80b7d67681589801b80cd072c9aba \ No newline at end of file diff --git a/main/structaxi_1_1ar__ace__inherit__graph.png b/main/structaxi_1_1ar__ace__inherit__graph.png new file mode 100644 index 00000000..3102a9af Binary files /dev/null and b/main/structaxi_1_1ar__ace__inherit__graph.png differ diff --git a/main/structaxi_1_1ar__axi-members.html b/main/structaxi_1_1ar__axi-members.html new file mode 100644 index 00000000..92a32ec9 --- /dev/null +++ b/main/structaxi_1_1ar__axi-members.html @@ -0,0 +1,97 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+
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+
+
axi::ar_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::ar_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
ar_addr (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_axi()=default (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_axi(const char *prefix) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
ar_burst (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_cache (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_id (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_len (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_lock (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_prot (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_qos (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_ready (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_region (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_size (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_user (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
ar_valid (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >
bind_ar(ar_axi< CFG, OTYPES > &o) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
bind_ar(ar_axi_lite< CFG, OTYPES > &o) (defined in axi::ar_axi< CFG, TYPES >)axi::ar_axi< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1ar__axi.html b/main/structaxi_1_1ar__axi.html new file mode 100644 index 00000000..a0cced52 --- /dev/null +++ b/main/structaxi_1_1ar__axi.html @@ -0,0 +1,148 @@ + + + + + + + +scc: axi::ar_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_axi< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ ar_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_ar (ar_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_full_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::ar_axi< CFG, TYPES >

+ + +

Definition at line 257 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ar__axi.js b/main/structaxi_1_1ar__axi.js new file mode 100644 index 00000000..ef561e1a --- /dev/null +++ b/main/structaxi_1_1ar__axi.js @@ -0,0 +1,20 @@ +var structaxi_1_1ar__axi = +[ + [ "ar_axi", "structaxi_1_1ar__axi.html#a3d195e95fdbc646ec15d0bdc0b32b496", null ], + [ "ar_axi", "structaxi_1_1ar__axi.html#a88f351ac148f13a7d15db8d3087179f6", null ], + [ "bind_ar", "structaxi_1_1ar__axi.html#a1c92de6db75ee6be9d107b1d183ea025", null ], + [ "bind_ar", "structaxi_1_1ar__axi.html#a7b81c3af189dc0b86fa2dd50707057bf", null ], + [ "ar_addr", "structaxi_1_1ar__axi.html#af7a334ef7ad2a7d378df2e1c98f88b54", null ], + [ "ar_burst", "structaxi_1_1ar__axi.html#a36d4e904cba5fb734690635cd8c733c2", null ], + [ "ar_cache", "structaxi_1_1ar__axi.html#a5446d572d85ddcd34454b8f5a51c55e0", null ], + [ "ar_id", "structaxi_1_1ar__axi.html#ab7ba8d1f07e6509b54538820025629fe", null ], + [ "ar_len", "structaxi_1_1ar__axi.html#a96f91b9fe4f0ede97b7cd7021789e6e0", null ], + [ "ar_lock", "structaxi_1_1ar__axi.html#ae080cabb8f779ad17eaef647968cbd34", null ], + [ "ar_prot", "structaxi_1_1ar__axi.html#a050a8869e3931ef03ab7907d5073fa4e", null ], + [ "ar_qos", "structaxi_1_1ar__axi.html#ace6839efc234fb3f41de97fa8d6b1365", null ], + [ "ar_ready", "structaxi_1_1ar__axi.html#a2e34821f1ed6f199613f3bca9d1a82e4", null ], + [ "ar_region", "structaxi_1_1ar__axi.html#a6374ac4e68b9d3fb489bf62e9fb06b91", null ], + [ "ar_size", "structaxi_1_1ar__axi.html#a75477f2b16d8c58eafd30a145216b1c6", null ], + [ "ar_user", "structaxi_1_1ar__axi.html#a1eb42419f6809b929b604f67f95bc56d", null ], + [ "ar_valid", "structaxi_1_1ar__axi.html#a56f558bc72b0439837e4bf9e649908d9", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1ar__axi__lite-members.html b/main/structaxi_1_1ar__axi__lite-members.html new file mode 100644 index 00000000..b857d501 --- /dev/null +++ b/main/structaxi_1_1ar__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
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+ +
+
+
+
axi::ar_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::ar_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
ar_addr (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_axi_lite()=default (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_axi_lite(const char *prefix) (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >inline
ar_prot (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_ready (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
ar_valid (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >
bind_ar(ar_axi< CFG, OTYPES > &o) (defined in axi::ar_axi_lite< CFG, TYPES >)axi::ar_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1ar__axi__lite.html b/main/structaxi_1_1ar__axi__lite.html new file mode 100644 index 00000000..c06c556d --- /dev/null +++ b/main/structaxi_1_1ar__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::ar_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::ar_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

read address channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ ar_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::ar_axi_lite< CFG, TYPES >

+ +

read address channel signals

+ +

Definition at line 445 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1ar__axi__lite.js b/main/structaxi_1_1ar__axi__lite.js new file mode 100644 index 00000000..8c8dc75f --- /dev/null +++ b/main/structaxi_1_1ar__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1ar__axi__lite = +[ + [ "ar_axi_lite", "structaxi_1_1ar__axi__lite.html#acc231e9b1de65fe2617694e002441f90", null ], + [ "ar_axi_lite", "structaxi_1_1ar__axi__lite.html#a9147e4184e018b567f6bbcd4309a5981", null ], + [ "bind_ar", "structaxi_1_1ar__axi__lite.html#a3b1a092a6041f144398a215a5cda1bde", null ], + [ "ar_addr", "structaxi_1_1ar__axi__lite.html#a001192fae236f6a7904e2a014f0603cc", null ], + [ "ar_prot", "structaxi_1_1ar__axi__lite.html#abf9619f836bf24ce99e25164e1ab7190", null ], + [ "ar_ready", "structaxi_1_1ar__axi__lite.html#a80e012a3eafa442047977c4b938d738e", null ], + [ "ar_valid", "structaxi_1_1ar__axi__lite.html#adce67c05ec447d5b9fa1381b64229178", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1aw__ace-members.html b/main/structaxi_1_1aw__ace-members.html new file mode 100644 index 00000000..1bfed79e --- /dev/null +++ b/main/structaxi_1_1aw__ace-members.html @@ -0,0 +1,106 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::aw_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1aw__ace.html b/main/structaxi_1_1aw__ace.html new file mode 100644 index 00000000..dbdb8748 --- /dev/null +++ b/main/structaxi_1_1aw__ace.html @@ -0,0 +1,184 @@ + + + + + + + +scc: axi::aw_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_ace< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::aw_ace< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + +

+Public Member Functions

+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::aw_ace< CFG, TYPES >

+ + +

Definition at line 550 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1aw__ace.js b/main/structaxi_1_1aw__ace.js new file mode 100644 index 00000000..89dd9d5f --- /dev/null +++ b/main/structaxi_1_1aw__ace.js @@ -0,0 +1,29 @@ +var structaxi_1_1aw__ace = +[ + [ "aw_ace", "structaxi_1_1aw__ace.html#a8ee008f32c5bad39b223590ff99c1671", null ], + [ "aw_ace", "structaxi_1_1aw__ace.html#a11230182f78eaf3f14a076742c761bd5", null ], + [ "bind_aw", "structaxi_1_1aw__ace.html#a2920186581f940ac01a8cf6e65e332e8", null ], + [ "aw_addr", "structaxi_1_1aw__ace.html#a227425ac3a4a9059a55f4b9cd2e08645", null ], + [ "aw_atop", "structaxi_1_1aw__ace.html#a6120844e144f5096d90c43b2f4cd49fd", null ], + [ "aw_bar", "structaxi_1_1aw__ace.html#af35c8a880ac498e46b8408a99e2b1215", null ], + [ "aw_burst", "structaxi_1_1aw__ace.html#a66a26a833eac2a5a2c923bd99e822560", null ], + [ "aw_cache", "structaxi_1_1aw__ace.html#a0abb831248bd51a87cab07e5bfa5326c", null ], + [ "aw_domain", "structaxi_1_1aw__ace.html#a1e1d9b044a7d2c93fc23e182043d0b4c", null ], + [ "aw_id", "structaxi_1_1aw__ace.html#a6e6e4bdea813509885c202405576425a", null ], + [ "aw_len", "structaxi_1_1aw__ace.html#a75f8e6386453d35c47f3242263260159", null ], + [ "aw_lock", "structaxi_1_1aw__ace.html#ae22068addc19cb0d5333928de7657657", null ], + [ "aw_prot", "structaxi_1_1aw__ace.html#acf0b2cba1d81ea66aa17aa46bea138e3", null ], + [ "aw_qos", "structaxi_1_1aw__ace.html#a8d59ed12058ef90947f89e12957d24ed", null ], + [ "aw_ready", "structaxi_1_1aw__ace.html#a737c40bb0af91ed2b5423a9e6e0500d8", null ], + [ "aw_region", "structaxi_1_1aw__ace.html#aee512fbdbbf76668bd4a7d5df0398236", null ], + [ "aw_size", "structaxi_1_1aw__ace.html#a8adc53ed71650ae6176bbfffd282849f", null ], + [ "aw_snoop", "structaxi_1_1aw__ace.html#a278a0012a959e89bd53b4529b3e31f6d", null ], + [ "aw_stashlpid", "structaxi_1_1aw__ace.html#a46e59beaec42e5d591f7ee10510d0cc4", null ], + [ "aw_stashlpiden", "structaxi_1_1aw__ace.html#aee71386e70c4067ecfe5a83bc845aef7", null ], + [ "aw_stashnid", "structaxi_1_1aw__ace.html#a8aec42a4e6c64ffdd8e0e3be6999be31", null ], + [ "aw_stashniden", "structaxi_1_1aw__ace.html#a06f156cb8a10a0b9242fe3dcacb67a81", null ], + [ "aw_trace", "structaxi_1_1aw__ace.html#a6adb34349525bbbb298b7d193563e29f", null ], + [ "aw_unique", "structaxi_1_1aw__ace.html#aaf3e6c9c513c53f08d6b2c9ad28b8f94", null ], + [ "aw_user", "structaxi_1_1aw__ace.html#ad8d4f3e1467b8d39c11cb8b12cf555d9", null ], + [ "aw_valid", "structaxi_1_1aw__ace.html#ac0f33b39f6092d7292f4867b0c3e146f", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1aw__ace__inherit__graph.map b/main/structaxi_1_1aw__ace__inherit__graph.map new file mode 100644 index 00000000..6a175d4c --- /dev/null +++ b/main/structaxi_1_1aw__ace__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/main/structaxi_1_1aw__ace__inherit__graph.md5 b/main/structaxi_1_1aw__ace__inherit__graph.md5 new file mode 100644 index 00000000..715376fa --- /dev/null +++ b/main/structaxi_1_1aw__ace__inherit__graph.md5 @@ -0,0 +1 @@ +fbf849779eef827ae547685ae28b43ec \ No newline at end of file diff --git a/main/structaxi_1_1aw__ace__inherit__graph.png b/main/structaxi_1_1aw__ace__inherit__graph.png new file mode 100644 index 00000000..b41f12d5 Binary files /dev/null and b/main/structaxi_1_1aw__ace__inherit__graph.png differ diff --git a/main/structaxi_1_1aw__axi-members.html b/main/structaxi_1_1aw__axi-members.html new file mode 100644 index 00000000..5793ddc8 --- /dev/null +++ b/main/structaxi_1_1aw__axi-members.html @@ -0,0 +1,97 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
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+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
axi::aw_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + + + +
aw_addr (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_axi()=default (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_axi(const char *prefix) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
aw_burst (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_cache (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_id (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_len (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_lock (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_prot (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_qos (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_ready (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_region (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_size (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_user (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
aw_valid (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >
bind_aw(aw_axi< CFG, OTYPES > &o) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
bind_aw(aw_axi_lite< CFG, OTYPES > &o) (defined in axi::aw_axi< CFG, TYPES >)axi::aw_axi< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1aw__axi.html b/main/structaxi_1_1aw__axi.html new file mode 100644 index 00000000..beeeffe5 --- /dev/null +++ b/main/structaxi_1_1aw__axi.html @@ -0,0 +1,148 @@ + + + + + + + +scc: axi::aw_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_axi< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ aw_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_aw (aw_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_full_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::aw_axi< CFG, TYPES >

+ + +

Definition at line 135 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1aw__axi.js b/main/structaxi_1_1aw__axi.js new file mode 100644 index 00000000..76e90546 --- /dev/null +++ b/main/structaxi_1_1aw__axi.js @@ -0,0 +1,20 @@ +var structaxi_1_1aw__axi = +[ + [ "aw_axi", "structaxi_1_1aw__axi.html#a1ae93639fa8f621657d69356d2b35324", null ], + [ "aw_axi", "structaxi_1_1aw__axi.html#ad4ed11f8b322a5e0547aea12cafc647a", null ], + [ "bind_aw", "structaxi_1_1aw__axi.html#a06386e5df3ec241ae73754d4d29deeed", null ], + [ "bind_aw", "structaxi_1_1aw__axi.html#a1b945e5d450793b96dbded157dc023f0", null ], + [ "aw_addr", "structaxi_1_1aw__axi.html#a95a93f2d5500c2ca9400d4acbee084b4", null ], + [ "aw_burst", "structaxi_1_1aw__axi.html#a8ef8cd22ff3ede0a331a09778f65e9e2", null ], + [ "aw_cache", "structaxi_1_1aw__axi.html#a69784a13ffeb6cd87a5dc1c4d24b46ab", null ], + [ "aw_id", "structaxi_1_1aw__axi.html#af184c6dbb307ee13984dcf07d5c3dd16", null ], + [ "aw_len", "structaxi_1_1aw__axi.html#a5378c903a0efeb261545ec42d003cf0b", null ], + [ "aw_lock", "structaxi_1_1aw__axi.html#a32f51690a61b12b1096a768f15ba1e1c", null ], + [ "aw_prot", "structaxi_1_1aw__axi.html#aa86baacec21734c5b925100c873f49c4", null ], + [ "aw_qos", "structaxi_1_1aw__axi.html#ae22c275884bb540adc44a6a87e429d31", null ], + [ "aw_ready", "structaxi_1_1aw__axi.html#a41eb358c188d504cdcc4e2e1ef8a5e27", null ], + [ "aw_region", "structaxi_1_1aw__axi.html#a746f5b3bb1578552b1594f111e08c2b2", null ], + [ "aw_size", "structaxi_1_1aw__axi.html#ac616e988c71577925667f6b4a9b7ce65", null ], + [ "aw_user", "structaxi_1_1aw__axi.html#a5ad9cabdddca274251a5262bb6bb0a89", null ], + [ "aw_valid", "structaxi_1_1aw__axi.html#a52fe9d89ec42d12567530fed5f4f25e9", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1aw__axi__lite-members.html b/main/structaxi_1_1aw__axi__lite-members.html new file mode 100644 index 00000000..7ef4af29 --- /dev/null +++ b/main/structaxi_1_1aw__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
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+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
axi::aw_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::aw_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
aw_addr (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_axi_lite()=default (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_axi_lite(const char *prefix) (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >inline
aw_prot (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_ready (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
aw_valid (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >
bind_aw(aw_axi< CFG, OTYPES > &o) (defined in axi::aw_axi_lite< CFG, TYPES >)axi::aw_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1aw__axi__lite.html b/main/structaxi_1_1aw__axi__lite.html new file mode 100644 index 00000000..7668756a --- /dev/null +++ b/main/structaxi_1_1aw__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::aw_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::aw_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

Write address channel signals. + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ aw_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::aw_axi_lite< CFG, TYPES >

+ +

Write address channel signals.

+ +

Definition at line 382 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1aw__axi__lite.js b/main/structaxi_1_1aw__axi__lite.js new file mode 100644 index 00000000..ffbf7a15 --- /dev/null +++ b/main/structaxi_1_1aw__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1aw__axi__lite = +[ + [ "aw_axi_lite", "structaxi_1_1aw__axi__lite.html#a6d89a287f208379c2ffbc61ac659311e", null ], + [ "aw_axi_lite", "structaxi_1_1aw__axi__lite.html#a3f955b7919c8445f760e6b34fa50af16", null ], + [ "bind_aw", "structaxi_1_1aw__axi__lite.html#a2215df66981d5092a8d042e6cb4b4081", null ], + [ "aw_addr", "structaxi_1_1aw__axi__lite.html#a7a883a2e12c40851edb1392040c7be24", null ], + [ "aw_prot", "structaxi_1_1aw__axi__lite.html#a2cd35c3d538e7c5c67c352e6f2341ef2", null ], + [ "aw_ready", "structaxi_1_1aw__axi__lite.html#ad2c3880d655c73a5dacb55eac53c7812", null ], + [ "aw_valid", "structaxi_1_1aw__axi__lite.html#a00c5c087758f4deed41eb9b37f634685", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1b__axi-members.html b/main/structaxi_1_1b__axi-members.html new file mode 100644 index 00000000..fbd85dd9 --- /dev/null +++ b/main/structaxi_1_1b__axi-members.html @@ -0,0 +1,90 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::b_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::b_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + +
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1b__axi.html b/main/structaxi_1_1b__axi.html new file mode 100644 index 00000000..feb4eb8c --- /dev/null +++ b/main/structaxi_1_1b__axi.html @@ -0,0 +1,139 @@ + + + + + + + +scc: axi::b_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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axi::b_axi< CFG, TYPES > Struct Template Reference
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+Inheritance diagram for axi::b_axi< CFG, TYPES >:
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Inheritance graph
+ + + + + + + +
[legend]
+ + + + + + + + + + +

+Public Member Functions

+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::b_axi< CFG, TYPES >

+ + +

Definition at line 227 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1b__axi.js b/main/structaxi_1_1b__axi.js new file mode 100644 index 00000000..a2f3ad47 --- /dev/null +++ b/main/structaxi_1_1b__axi.js @@ -0,0 +1,13 @@ +var structaxi_1_1b__axi = +[ + [ "b_axi", "structaxi_1_1b__axi.html#ac8b64af8a73506bbd755d3e2355de575", null ], + [ "b_axi", "structaxi_1_1b__axi.html#a2f0552ce13ab10650d258017b9f6d499", null ], + [ "bind_b", "structaxi_1_1b__axi.html#a5384501b6dd4d2fd4ad9a22120b89b4e", null ], + [ "bind_b", "structaxi_1_1b__axi.html#ab71b6877ad0df31c81ac916faedfd04e", null ], + [ "b_id", "structaxi_1_1b__axi.html#ad778ea1b2d6c4f86aad167a4ee2b5e1a", null ], + [ "b_ready", "structaxi_1_1b__axi.html#ac3e7e99f64569f52ab1450b226b5d5e3", null ], + [ "b_resp", "structaxi_1_1b__axi.html#ac8fb04c79763f46cf5bfdb7fe8f627f2", null ], + [ "b_trace", "structaxi_1_1b__axi.html#adf4625698a24b9d4611b6b086fa07e53", null ], + [ "b_user", "structaxi_1_1b__axi.html#ad526d28d79c2e1c67b197e864b71124f", null ], + [ "b_valid", "structaxi_1_1b__axi.html#a59d42372be2059cf18737170bfc0e52f", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1b__axi__inherit__graph.map b/main/structaxi_1_1b__axi__inherit__graph.map new file mode 100644 index 00000000..e4edc223 --- /dev/null +++ b/main/structaxi_1_1b__axi__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/main/structaxi_1_1b__axi__inherit__graph.md5 b/main/structaxi_1_1b__axi__inherit__graph.md5 new file mode 100644 index 00000000..dcd12e29 --- /dev/null +++ b/main/structaxi_1_1b__axi__inherit__graph.md5 @@ -0,0 +1 @@ +4db927dc6c0fd526952e19b3bd8d5ff5 \ No newline at end of file diff --git a/main/structaxi_1_1b__axi__inherit__graph.png b/main/structaxi_1_1b__axi__inherit__graph.png new file mode 100644 index 00000000..fc0ba9e7 Binary files /dev/null and b/main/structaxi_1_1b__axi__inherit__graph.png differ diff --git a/main/structaxi_1_1b__axi__lite-members.html b/main/structaxi_1_1b__axi__lite-members.html new file mode 100644 index 00000000..1a8e694a --- /dev/null +++ b/main/structaxi_1_1b__axi__lite-members.html @@ -0,0 +1,86 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::b_axi_lite< CFG, TYPES > Member List
+
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+ +

This is the complete list of members for axi::b_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + +
b_axi_lite()=default (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_axi_lite(const char *prefix) (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >inline
b_ready (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_resp (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
b_valid (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi_lite< CFG, TYPES >)axi::b_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1b__axi__lite.html b/main/structaxi_1_1b__axi__lite.html new file mode 100644 index 00000000..76b88eaf --- /dev/null +++ b/main/structaxi_1_1b__axi__lite.html @@ -0,0 +1,120 @@ + + + + + + + +scc: axi::b_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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axi::b_axi_lite< CFG, TYPES > Struct Template Reference
+
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+ +

write response channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ b_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+ + + + + + + +

+Public Attributes

+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::b_axi_lite< CFG, TYPES >

+ +

write response channel signals

+ +

Definition at line 426 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1b__axi__lite.js b/main/structaxi_1_1b__axi__lite.js new file mode 100644 index 00000000..78963aa2 --- /dev/null +++ b/main/structaxi_1_1b__axi__lite.js @@ -0,0 +1,9 @@ +var structaxi_1_1b__axi__lite = +[ + [ "b_axi_lite", "structaxi_1_1b__axi__lite.html#a4b31a8b0dbf6f7c81d8ff4ec0a172b4a", null ], + [ "b_axi_lite", "structaxi_1_1b__axi__lite.html#a5eed554019dc9cdf02cf49d3f79ff4c8", null ], + [ "bind_b", "structaxi_1_1b__axi__lite.html#a4870cdf806fce130c00c47c28bcdf65b", null ], + [ "b_ready", "structaxi_1_1b__axi__lite.html#aaa75388c9fde2795604c5d02aa2ba93f", null ], + [ "b_resp", "structaxi_1_1b__axi__lite.html#ae70877ef1a3ed10b950a9f68c19dc83c", null ], + [ "b_valid", "structaxi_1_1b__axi__lite.html#ad4d5afb18405db41942c158db9900f7f", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1cd__ace-members.html b/main/structaxi_1_1cd__ace-members.html new file mode 100644 index 00000000..e6cd4e2a --- /dev/null +++ b/main/structaxi_1_1cd__ace-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
+
axi::cd_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::cd_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >inline
cd_ace()=default (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >inline
cd_data (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_last (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_ready (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
cd_valid (defined in axi::cd_ace< CFG, TYPES >)axi::cd_ace< CFG, TYPES >
+
+ + + + diff --git a/main/structaxi_1_1cd__ace.html b/main/structaxi_1_1cd__ace.html new file mode 100644 index 00000000..7c331430 --- /dev/null +++ b/main/structaxi_1_1cd__ace.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::cd_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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axi::cd_ace< CFG, TYPES > Struct Template Reference
+
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+ +

snoop data(cd) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ cd_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_cd (cd_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< bool > cd_valid {"cd_valid"}
 
+TYPES::template s2m_t< bool > cd_ready {"cd_ready"}
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data {"cd_data"}
 
+TYPES::template m2s_full_t< bool > cd_last {"cd_last"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::cd_ace< CFG, TYPES >

+ +

snoop data(cd) channel signals

+ +

Definition at line 658 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1cd__ace.js b/main/structaxi_1_1cd__ace.js new file mode 100644 index 00000000..aed6ccbb --- /dev/null +++ b/main/structaxi_1_1cd__ace.js @@ -0,0 +1,10 @@ +var structaxi_1_1cd__ace = +[ + [ "cd_ace", "structaxi_1_1cd__ace.html#a3d53f0b6b46f592b722c61d02c4ba92a", null ], + [ "cd_ace", "structaxi_1_1cd__ace.html#aae1cd6099a2dcd6abdbeb67d8249c722", null ], + [ "bind_cd", "structaxi_1_1cd__ace.html#a7dec2b4407bfaa57eb5a085f8d3f3812", null ], + [ "cd_data", "structaxi_1_1cd__ace.html#a00284bf066c2c49329287071dd739609", null ], + [ "cd_last", "structaxi_1_1cd__ace.html#a431355e2ad70a5f63b5ea43a3f3af178", null ], + [ "cd_ready", "structaxi_1_1cd__ace.html#ad2946289ea7761c5f0b90694452ae674", null ], + [ "cd_valid", "structaxi_1_1cd__ace.html#a39db9eb2463e91e8098cb72def40323c", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1cr__ace-members.html b/main/structaxi_1_1cr__ace-members.html new file mode 100644 index 00000000..a366e6e4 --- /dev/null +++ b/main/structaxi_1_1cr__ace-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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axi::cr_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::cr_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >inline
cr_ace()=default (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >inline
cr_ready (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_resp (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_trace (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
cr_valid (defined in axi::cr_ace< CFG, TYPES >)axi::cr_ace< CFG, TYPES >
+
+ + + + diff --git a/main/structaxi_1_1cr__ace.html b/main/structaxi_1_1cr__ace.html new file mode 100644 index 00000000..0c063e74 --- /dev/null +++ b/main/structaxi_1_1cr__ace.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::cr_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Public Member Functions | +Public Attributes | +List of all members
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axi::cr_ace< CFG, TYPES > Struct Template Reference
+
+
+ +

snoop response(cr) channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ cr_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_cr (cr_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< bool > cr_valid {"cr_valid"}
 
+TYPES::template s2m_t< bool > cr_ready {"cr_ready"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp {"cr_resp"}
 
+TYPES::template m2s_opt_t< bool > cr_trace {"cr_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::cr_ace< CFG, TYPES >

+ +

snoop response(cr) channel signals

+ +

Definition at line 680 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1cr__ace.js b/main/structaxi_1_1cr__ace.js new file mode 100644 index 00000000..394158a9 --- /dev/null +++ b/main/structaxi_1_1cr__ace.js @@ -0,0 +1,10 @@ +var structaxi_1_1cr__ace = +[ + [ "cr_ace", "structaxi_1_1cr__ace.html#a7f57b89834f5f20169c3cae39c2b5fd3", null ], + [ "cr_ace", "structaxi_1_1cr__ace.html#a756a5dfcc5423df7dd22bf23f7a388d4", null ], + [ "bind_cr", "structaxi_1_1cr__ace.html#ac5960e32578fb91509ae62abb41a9a9a", null ], + [ "cr_ready", "structaxi_1_1cr__ace.html#ab6d7c05c328f52372f888aae360160df", null ], + [ "cr_resp", "structaxi_1_1cr__ace.html#a925927830e3bb5264db0b7f5a022bde3", null ], + [ "cr_trace", "structaxi_1_1cr__ace.html#a80dcfde5dd8cfd0aa895564346901bad", null ], + [ "cr_valid", "structaxi_1_1cr__ace.html#acfc5e6ca6da8ef7281ae3df05b41a924", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__initiator-members.html b/main/structaxi_1_1pin_1_1ace__initiator-members.html new file mode 100644 index 00000000..9ad1ae9b --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator-members.html @@ -0,0 +1,221 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
+
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+
+
axi::pin::ace_initiator< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_initiator< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ac_ace()=default (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >inline
ac_addr (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_prot (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_ready (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_snoop (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_trace (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_valid (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ac_vmidext (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >
ace_initiator(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >inline
ar_addr (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_bar (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_burst (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_cache (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_domain (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_id (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_len (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_lock (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_prot (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_qos (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_ready (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_region (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_size (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_snoop (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_trace (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_user (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_valid (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
ar_vmidext (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >
aw_ace()=default (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >inline
aw_addr (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_atop (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_bar (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_burst (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_cache (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_domain (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_id (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_len (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_lock (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_prot (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_qos (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_ready (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_region (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_size (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_snoop (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashlpid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashlpiden (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashnid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_stashniden (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_trace (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_unique (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_user (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
aw_valid (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, CFG::master_types >)axi::ac_ace< CFG, CFG::master_types >inline
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, CFG::master_types >)axi::ar_ace< CFG, CFG::master_types >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, CFG::master_types >)axi::aw_ace< CFG, CFG::master_types >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >inline
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >inline
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
CACHELINE_SZ enum value (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
cd_ace()=default (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >inline
cd_data (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_last (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_ready (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
cd_valid (defined in axi::cd_ace< CFG, CFG::master_types >)axi::cd_ace< CFG, CFG::master_types >
clk_i (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
cr_ace()=default (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >inline
cr_ready (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_resp (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_trace (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
cr_valid (defined in axi::cr_ace< CFG, CFG::master_types >)axi::cr_ace< CFG, CFG::master_types >
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
phase_type typedef (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_ack (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_data (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_id (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_last (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_ready (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_resp (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_trace (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_user (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
r_valid (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_ace()=default (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, CFG::master_types >)axi::rresp_ace< CFG, CFG::master_types >inline
SC_HAS_PROCESS(ace_initiator) (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
tsckt (defined in axi::pin::ace_initiator< CFG >)axi::pin::ace_initiator< CFG >
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__initiator.html b/main/structaxi_1_1pin_1_1ace__initiator.html new file mode 100644 index 00000000..0d2fe920 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator.html @@ -0,0 +1,585 @@ + + + + + + + +scc: axi::pin::ace_initiator< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_initiator< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_initiator< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_initiator< CFG >:
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+
Collaboration graph
+ + + + + + + + + + + + + + + + + + + + +
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+ + + + + + + + +

+Public Types

enum  { CACHELINE_SZ = 64 + }
 
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_initiator)
 
+ ace_initiator (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, CFG::master_types >
+ aw_ace (const char *prefix)
 
+void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, CFG::master_types >
+ ar_ace (const char *prefix)
 
+void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_ace< CFG, CFG::master_types >
+ rresp_ace (const char *prefix)
 
+void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ac_ace< CFG, CFG::master_types >
+ ac_ace (const char *prefix)
 
+void bind_ac (ac_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cr_ace< CFG, CFG::master_types >
+ cr_ace (const char *prefix)
 
+void bind_cr (cr_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cd_ace< CFG, CFG::master_types >
+ cd_ace (const char *prefix)
 
+void bind_cd (cd_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::ace_target_socket< CFG::BUSWIDTH > tsckt {"tsckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, CFG::master_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr
 
+TYPES::template s2m_t< bool > aw_ready
 
+TYPES::template m2s_t< bool > aw_lock
 
+TYPES::template m2s_t< bool > aw_valid
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar
 
+TYPES::template m2s_t< bool > aw_unique
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user
 
+TYPES::template m2s_t< bool > aw_stashniden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid
 
+TYPES::template m2s_t< bool > aw_stashlpiden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop
 
+TYPES::template m2s_opt_t< bool > aw_trace
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, CFG::master_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst
 
+TYPES::template m2s_t< bool > ar_lock
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region
 
+TYPES::template m2s_t< bool > ar_valid
 
+TYPES::template s2m_t< bool > ar_ready
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user
 
+TYPES::template m2s_opt_t< bool > ar_trace
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext
 
- Public Attributes inherited from axi::rresp_ace< CFG, CFG::master_types >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id
 
+TYPES::template s2m_t< typename CFG::data_t > r_data
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp
 
+TYPES::template s2m_full_t< bool > r_last
 
+TYPES::template s2m_t< bool > r_valid
 
+TYPES::template m2s_t< bool > r_ready
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user
 
+TYPES::template s2m_opt_t< bool > r_trace
 
+TYPES::template m2s_t< bool > r_ack
 
- Public Attributes inherited from axi::ac_ace< CFG, CFG::master_types >
+TYPES::template s2m_t< bool > ac_valid
 
+TYPES::template m2s_t< bool > ac_ready
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext
 
+TYPES::template s2m_opt_t< bool > ac_trace
 
- Public Attributes inherited from axi::cr_ace< CFG, CFG::master_types >
+TYPES::template m2s_t< bool > cr_valid
 
+TYPES::template s2m_t< bool > cr_ready
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp
 
+TYPES::template m2s_opt_t< bool > cr_trace
 
- Public Attributes inherited from axi::cd_ace< CFG, CFG::master_types >
+TYPES::template m2s_t< bool > cd_valid
 
+TYPES::template s2m_t< bool > cd_ready
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data
 
+TYPES::template m2s_full_t< bool > cd_last
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_initiator< CFG >

+ + +

Definition at line 36 of file ace_initiator.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__initiator.js b/main/structaxi_1_1pin_1_1ace__initiator.js new file mode 100644 index 00000000..f30d6e20 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__initiator = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__initiator.html#ad638947a22e1cf0a460b89537b8c120f", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__initiator.html#a40110f88df445005684d5ce4f6e5d847", null ], + [ "ace_initiator", "structaxi_1_1pin_1_1ace__initiator.html#ae3ea71803abf5439d7f739b099681490", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__initiator.html#a69a885243b851c2a38b0fe64598877ae", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__initiator.html#ac97c937183d8c8a9ca51e2b2f4d05e6e", null ], + [ "tsckt", "structaxi_1_1pin_1_1ace__initiator.html#a1e0e18e90549401a60832e66ccb25e63", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.map b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.map new file mode 100644 index 00000000..01687720 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.map @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 new file mode 100644 index 00000000..5765ff53 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.md5 @@ -0,0 +1 @@ +6d3172af64431c871f05a273be532a32 \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.png b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.png new file mode 100644 index 00000000..d51011ca Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__initiator__coll__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map new file mode 100644 index 00000000..52fcea89 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.map @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 new file mode 100644 index 00000000..381cc4a3 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.md5 @@ -0,0 +1 @@ +50e5ea5162ea1b5eeac879bb9ef400c8 \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png new file mode 100644 index 00000000..0e605051 Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__initiator__inherit__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator-members.html b/main/structaxi_1_1pin_1_1ace__lite__initiator-members.html new file mode 100644 index 00000000..a889995c --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator-members.html @@ -0,0 +1,197 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pin::ace_lite_initiator< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_lite_initiator< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_lite_initiator(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
clk_i (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
axi::fsm::base::nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
phase_type typedef (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
SC_HAS_PROCESS(ace_lite_initiator) (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
tsckt (defined in axi::pin::ace_lite_initiator< CFG >)axi::pin::ace_lite_initiator< CFG >
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator.html b/main/structaxi_1_1pin_1_1ace__lite__initiator.html new file mode 100644 index 00000000..cea5abaa --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator.html @@ -0,0 +1,516 @@ + + + + + + + +scc: axi::pin::ace_lite_initiator< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_lite_initiator< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_lite_initiator< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_lite_initiator< CFG >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_lite_initiator)
 
+ ace_lite_initiator (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, TYPES >
+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, TYPES >
+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_axi< CFG, TYPES >
+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_target_socket< CFG::BUSWIDTH > tsckt {"tsckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
- Public Attributes inherited from axi::rresp_axi< CFG, TYPES >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_lite_initiator< CFG >

+ + +

Definition at line 34 of file ace_lite_initiator.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator.js b/main/structaxi_1_1pin_1_1ace__lite__initiator.js new file mode 100644 index 00000000..8ec7e455 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__lite__initiator = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__lite__initiator.html#aaab85a1a64a60b759d2da2796f3e5e2a", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__lite__initiator.html#aff5dcb4ab83c887df553fac56a98f661", null ], + [ "ace_lite_initiator", "structaxi_1_1pin_1_1ace__lite__initiator.html#af18b263b5032f4ec3c3447e25b637aec", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__lite__initiator.html#a7c2961050fea91c88fb82be819816823", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__lite__initiator.html#aba822315e15d051f6cd17bd085f00607", null ], + [ "tsckt", "structaxi_1_1pin_1_1ace__lite__initiator.html#a78f346ce1a33dcb8672ea86509439c0e", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map new file mode 100644 index 00000000..9601dcf8 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 new file mode 100644 index 00000000..2a203dd1 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.md5 @@ -0,0 +1 @@ +d33842d48b78faf1478fb36df31911cb \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png new file mode 100644 index 00000000..251a66e3 Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__lite__initiator__coll__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map new file mode 100644 index 00000000..d93a4bdd --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 new file mode 100644 index 00000000..19cb918e --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.md5 @@ -0,0 +1 @@ +617f6d29ac38c3de93dd365521139a12 \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png new file mode 100644 index 00000000..70dce472 Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__lite__initiator__inherit__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__lite__target-members.html b/main/structaxi_1_1pin_1_1ace__lite__target-members.html new file mode 100644 index 00000000..f76516c7 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target-members.html @@ -0,0 +1,197 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::pin::ace_lite_target< CFG > Member List
+
+
+ +

This is the complete list of members for axi::pin::ace_lite_target< CFG >, including all inherited members.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ace_lite_target(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
ar_addr (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_bar (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_burst (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_cache (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_domain (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_id (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_len (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_lock (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_prot (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_qos (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_ready (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_region (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_size (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_snoop (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_trace (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_user (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_valid (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
ar_vmidext (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >
aw_ace()=default (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
aw_addr (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_atop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_bar (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_burst (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_cache (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_domain (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_id (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_len (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_lock (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_prot (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_qos (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_ready (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_region (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_size (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_snoop (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashlpiden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashnid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_stashniden (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_trace (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_unique (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_user (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
aw_valid (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, TYPES >)axi::ar_ace< CFG, TYPES >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, TYPES >)axi::aw_ace< CFG, TYPES >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
clk_i (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
isckt (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
phase_type typedef (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
SC_HAS_PROCESS(ace_lite_target) (defined in axi::pin::ace_lite_target< CFG >)axi::pin::ace_lite_target< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__target.html b/main/structaxi_1_1pin_1_1ace__lite__target.html new file mode 100644 index 00000000..6912c90c --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target.html @@ -0,0 +1,517 @@ + + + + + + + +scc: axi::pin::ace_lite_target< CFG > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Classes | +Public Types | +Public Member Functions | +Public Attributes | +List of all members
+
+
axi::pin::ace_lite_target< CFG > Struct Template Reference
+
+
+
+Inheritance diagram for axi::pin::ace_lite_target< CFG >:
+
+
Inheritance graph
+ + + + + + + + + + + +
[legend]
+
+Collaboration diagram for axi::pin::ace_lite_target< CFG >:
+
+
Collaboration graph
+ + + + + + + + + + + + + + + + + +
[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Member Functions

+ SC_HAS_PROCESS (ace_lite_target)
 
+ ace_lite_target (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, TYPES >
+ aw_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, TYPES >
+ ar_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_axi< CFG, TYPES >
+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::axi_initiator_socket< CFG::BUSWIDTH > isckt {"isckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id {"aw_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr {"aw_addr"}
 
+TYPES::template s2m_t< bool > aw_ready {"aw_ready"}
 
+TYPES::template m2s_t< bool > aw_lock {"aw_lock"}
 
+TYPES::template m2s_t< bool > aw_valid {"aw_valid"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot {"aw_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size {"aw_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache {"aw_cache"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst {"aw_burst"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos {"aw_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region {"aw_region"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len {"aw_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain {"aw_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop {"aw_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar {"aw_bar"}
 
+TYPES::template m2s_t< bool > aw_unique {"aw_unique"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user {"aw_user"}
 
+TYPES::template m2s_t< bool > aw_stashniden {"aw_stashniden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid {"aw_stashnid"}
 
+TYPES::template m2s_t< bool > aw_stashlpiden {"aw_stashlpiden"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid {"aw_stashlpid"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop {"aw_atop"}
 
+TYPES::template m2s_opt_t< bool > aw_trace {"aw_trace"}
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, TYPES >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id {"ar_id"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr {"ar_addr"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len {"ar_len"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size {"ar_size"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst {"ar_burst"}
 
+TYPES::template m2s_t< bool > ar_lock {"ar_lock"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache {"ar_cache"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot {"ar_prot"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos {"ar_qos"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region {"ar_region"}
 
+TYPES::template m2s_t< bool > ar_valid {"ar_valid"}
 
+TYPES::template s2m_t< bool > ar_ready {"ar_ready"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain {"ar_domain"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop {"ar_snoop"}
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar {"ar_bar"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user {"ar_user"}
 
+TYPES::template m2s_opt_t< bool > ar_trace {"ar_trace"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext {"ar_vmidext"}
 
- Public Attributes inherited from axi::rresp_axi< CFG, TYPES >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_lite_target< CFG >

+ + +

Definition at line 36 of file ace_lite_target.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__target.js b/main/structaxi_1_1pin_1_1ace__lite__target.js new file mode 100644 index 00000000..e36f5647 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__lite__target = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__lite__target.html#a95b24a90fe94ddc1fe927e622d05812f", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__lite__target.html#ae93064bf1f5e2106957ccd8606f288e2", null ], + [ "ace_lite_target", "structaxi_1_1pin_1_1ace__lite__target.html#a033c18767e51960adf370b598cc3180a", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__lite__target.html#a3b320c9f5846a6130b60a2c4b9206637", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__lite__target.html#a06648b39eae4552c22c492dd05e8d53a", null ], + [ "isckt", "structaxi_1_1pin_1_1ace__lite__target.html#abd1d5a863fa5be71a76a8382f61ae79b", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map new file mode 100644 index 00000000..7faae0fd --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 new file mode 100644 index 00000000..976d3c69 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.md5 @@ -0,0 +1 @@ +396ba8dc1574b4a6bf83b9dfdbf46c37 \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png new file mode 100644 index 00000000..52d356c3 Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__lite__target__coll__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map new file mode 100644 index 00000000..147f147a --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 new file mode 100644 index 00000000..1596aa72 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.md5 @@ -0,0 +1 @@ +74b1daca2e917f2d5b52ccba578f1410 \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png new file mode 100644 index 00000000..a892fc81 Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__lite__target__inherit__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__target-members.html b/main/structaxi_1_1pin_1_1ace__target-members.html new file mode 100644 index 00000000..0a62e4a6 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target-members.html @@ -0,0 +1,221 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
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scc +  2022.4.0 +
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SystemC components library
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axi::pin::ace_target< CFG > Member List
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+ +

This is the complete list of members for axi::pin::ace_target< CFG >, including all inherited members.

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ac_ace()=default (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_ace(const char *prefix) (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >inline
ac_addr (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_prot (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_ready (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_snoop (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_trace (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_valid (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ac_vmidext (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >
ace_target(sc_core::sc_module_name const &nm) (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >inline
active_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
allocated_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
ar_ace()=default (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_ace(const char *prefix) (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >inline
ar_addr (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_bar (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_burst (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_cache (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_domain (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_id (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_len (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_lock (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_prot (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_qos (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_ready (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_region (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_size (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_snoop (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_trace (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_user (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_valid (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
ar_vmidext (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >
aw_ace()=default (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_ace(const char *prefix) (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >inline
aw_addr (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_atop (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_bar (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_burst (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_cache (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_domain (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_id (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_len (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_lock (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_prot (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_qos (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_ready (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_region (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_size (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_snoop (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashlpid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashlpiden (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashnid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_stashniden (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_trace (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_unique (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_user (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
aw_valid (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >
b_axi()=default (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_axi(const char *prefix) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
b_id (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_ready (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_resp (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
ace_bw_transport_if< axi::axi_protocol_types >::b_snoop(TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0axi::bw_blocking_transport_if< TYPES::tlm_payload_type >pure virtual
b_trace (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_user (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
b_valid (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >
base(size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)axi::fsm::baseprotected
bind_ac(ac_ace< CFG, OTYPES > &o) (defined in axi::ac_ace< CFG, CFG::slave_types >)axi::ac_ace< CFG, CFG::slave_types >inline
bind_ar(ar_ace< CFG, OTYPES > &o) (defined in axi::ar_ace< CFG, CFG::slave_types >)axi::ar_ace< CFG, CFG::slave_types >inline
bind_aw(aw_ace< CFG, OTYPES > &o) (defined in axi::aw_ace< CFG, CFG::slave_types >)axi::aw_ace< CFG, CFG::slave_types >inline
bind_b(b_axi< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_b(b_axi_lite< CFG, OTYPES > &o) (defined in axi::b_axi< CFG, TYPES >)axi::b_axi< CFG, TYPES >inline
bind_cd(cd_ace< CFG, OTYPES > &o) (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >inline
bind_cr(cr_ace< CFG, OTYPES > &o) (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >inline
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
cd_ace()=default (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_ace(const char *prefix) (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >inline
cd_data (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_last (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_ready (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
cd_valid (defined in axi::cd_ace< CFG, CFG::slave_types >)axi::cd_ace< CFG, CFG::slave_types >
clk_i (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
coherent (defined in axi::fsm::base)axi::fsm::baseprotected
cr_ace()=default (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_ace(const char *prefix) (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >inline
cr_ready (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_resp (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_trace (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
cr_valid (defined in axi::cr_ace< CFG, CFG::slave_types >)axi::cr_ace< CFG, CFG::slave_types >
find_or_create(payload_type *gp=nullptr, bool ace=false)axi::fsm::baseprotected
finish_evt (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_clk_queue_hndl (defined in axi::fsm::base)axi::fsm::baseprotected
fsm_event_queue (defined in axi::fsm::base)axi::fsm::baseprotected
idle_fsm (defined in axi::fsm::base)axi::fsm::baseprotected
instance_name (defined in axi::fsm::base)axi::fsm::baseprotected
isckt (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
nb_bw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
nb_fw(payload_type &trans, phase_type const &phase, sc_core::sc_time &t)axi::fsm::baseprotected
payload_type typedef (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
phase_type typedef (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
process_fsm_clk_queue()axi::fsm::baseprotected
process_fsm_event()axi::fsm::baseprotected
r_ack (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_data (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_id (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_last (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_ready (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_resp (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_trace (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_user (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
r_valid (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
react(axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e event, payload_type *trans) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
react(axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *) (defined in axi::fsm::base)axi::fsm::baseprotected
rresp_ace()=default (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, CFG::slave_types >)axi::rresp_ace< CFG, CFG::slave_types >inline
SC_HAS_PROCESS(ace_target) (defined in axi::pin::ace_target< CFG >)axi::pin::ace_target< CFG >
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)axi::fsm::baseinlineprotected
schedule(axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false) (defined in axi::fsm::base)axi::fsm::baseinlineprotected
transfer_width_in_bytes (defined in axi::fsm::base)axi::fsm::baseprotected
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
wr_start (defined in axi::fsm::base)axi::fsm::baseprotected
~base()axi::fsm::baseinlineprotectedvirtual
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__target.html b/main/structaxi_1_1pin_1_1ace__target.html new file mode 100644 index 00000000..418bdbdd --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target.html @@ -0,0 +1,597 @@ + + + + + + + +scc: axi::pin::ace_target< CFG > Struct Template Reference + + + + + + + + + + + +
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scc +  2022.4.0 +
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SystemC components library
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+Classes | +Public Types | +Public Member Functions | +Public Attributes | +List of all members
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axi::pin::ace_target< CFG > Struct Template Reference
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+
+
+Inheritance diagram for axi::pin::ace_target< CFG >:
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Inheritance graph
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[legend]
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+Collaboration diagram for axi::pin::ace_target< CFG >:
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Collaboration graph
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[legend]
+ + + + + + +

+Public Types

+using payload_type = axi::axi_protocol_types::tlm_payload_type
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
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+Public Member Functions

+ SC_HAS_PROCESS (ace_target)
 
+ ace_target (sc_core::sc_module_name const &nm)
 
- Public Member Functions inherited from axi::aw_ace< CFG, CFG::slave_types >
+ aw_ace (const char *prefix)
 
+void bind_aw (aw_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::wdata_axi< CFG, TYPES >
+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::b_axi< CFG, TYPES >
+ b_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_b (b_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_b (b_axi_lite< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ar_ace< CFG, CFG::slave_types >
+ ar_ace (const char *prefix)
 
+void bind_ar (ar_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::rresp_ace< CFG, CFG::slave_types >
+ rresp_ace (const char *prefix)
 
+void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::ac_ace< CFG, CFG::slave_types >
+ ac_ace (const char *prefix)
 
+void bind_ac (ac_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cr_ace< CFG, CFG::slave_types >
+ cr_ace (const char *prefix)
 
+void bind_cr (cr_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::cd_ace< CFG, CFG::slave_types >
+ cd_ace (const char *prefix)
 
+void bind_cd (cd_ace< CFG, OTYPES > &o)
 
- Public Member Functions inherited from axi::bw_blocking_transport_if< TYPES::tlm_payload_type >
virtual void b_snoop (TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0
 snoop access to a snooped master More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Public Attributes

+sc_core::sc_in< bool > clk_i {"clk_i"}
 
+axi::ace_initiator_socket< CFG::BUSWIDTH > isckt {"isckt"}
 
- Public Attributes inherited from axi::aw_ace< CFG, CFG::slave_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > aw_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > aw_addr
 
+TYPES::template s2m_t< bool > aw_ready
 
+TYPES::template m2s_t< bool > aw_lock
 
+TYPES::template m2s_t< bool > aw_valid
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > aw_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > aw_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_cache
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_burst
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > aw_region
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > aw_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::AWSNOOPWIDTH > > aw_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > aw_bar
 
+TYPES::template m2s_t< bool > aw_unique
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::USERWIDTH > > aw_user
 
+TYPES::template m2s_t< bool > aw_stashniden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 11 > > aw_stashnid
 
+TYPES::template m2s_t< bool > aw_stashlpiden
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 5 > > aw_stashlpid
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 6 > > aw_atop
 
+TYPES::template m2s_opt_t< bool > aw_trace
 
- Public Attributes inherited from axi::wdata_axi< CFG, TYPES >
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
- Public Attributes inherited from axi::b_axi< CFG, TYPES >
+TYPES::template s2m_t< bool > b_valid {"b_valid"}
 
+TYPES::template m2s_t< bool > b_ready {"b_ready"}
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > b_id {"b_id"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > b_resp {"b_resp"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > b_user {"b_user"}
 
+TYPES::template s2m_opt_t< bool > b_trace {"b_trace"}
 
- Public Attributes inherited from axi::ar_ace< CFG, CFG::slave_types >
+TYPES::template m2s_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > ar_id
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ar_addr
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 8 > > ar_len
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 3 > > ar_size
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_burst
 
+TYPES::template m2s_t< bool > ar_lock
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_cache
 
+TYPES::template m2s_t< sc_dt::sc_uint< 3 > > ar_prot
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_qos
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_region
 
+TYPES::template m2s_t< bool > ar_valid
 
+TYPES::template s2m_t< bool > ar_ready
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_domain
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 4 > > ar_snoop
 
+TYPES::template m2s_full_t< sc_dt::sc_uint< 2 > > ar_bar
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > ar_user
 
+TYPES::template m2s_opt_t< bool > ar_trace
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< 4 > > ar_vmidext
 
- Public Attributes inherited from axi::rresp_ace< CFG, CFG::slave_types >
+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id
 
+TYPES::template s2m_t< typename CFG::data_t > r_data
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp
 
+TYPES::template s2m_full_t< bool > r_last
 
+TYPES::template s2m_t< bool > r_valid
 
+TYPES::template m2s_t< bool > r_ready
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user
 
+TYPES::template s2m_opt_t< bool > r_trace
 
+TYPES::template m2s_t< bool > r_ack
 
- Public Attributes inherited from axi::ac_ace< CFG, CFG::slave_types >
+TYPES::template s2m_t< bool > ac_valid
 
+TYPES::template m2s_t< bool > ac_ready
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::ADDRWIDTH > > ac_addr
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 4 > > ac_snoop
 
+TYPES::template s2m_full_t< sc_dt::sc_uint< 3 > > ac_prot
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< 4 > > ac_vmidext
 
+TYPES::template s2m_opt_t< bool > ac_trace
 
- Public Attributes inherited from axi::cr_ace< CFG, CFG::slave_types >
+TYPES::template m2s_t< bool > cr_valid
 
+TYPES::template s2m_t< bool > cr_ready
 
+TYPES::template m2s_t< sc_dt::sc_uint< 5 > > cr_resp
 
+TYPES::template m2s_opt_t< bool > cr_trace
 
- Public Attributes inherited from axi::cd_ace< CFG, CFG::slave_types >
+TYPES::template m2s_t< bool > cd_valid
 
+TYPES::template s2m_t< bool > cd_ready
 
+TYPES::template m2s_t< typename CFG::data_t > cd_data
 
+TYPES::template m2s_full_t< bool > cd_last
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Additional Inherited Members

- Protected Types inherited from axi::fsm::base
+using payload_type = axi::axi_protocol_types::tlm_payload_type
 aliases used in the class
 
+using phase_type = axi::axi_protocol_types::tlm_phase_type
 
- Protected Member Functions inherited from axi::fsm::base
 base (size_t transfer_width, bool coherent=false, axi::fsm::protocol_time_point_e wr_start=axi::fsm::RequestPhaseBeg)
 the constructor More...
 
+virtual ~base ()
 the destructor
 
tlm::tlm_sync_enum nb_fw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the forward path. Should be called from np_transport_fw of the respective derived class More...
 
tlm::tlm_sync_enum nb_bw (payload_type &trans, phase_type const &phase, sc_core::sc_time &t)
 triggers the FSM based on TLM phases in the backward path. Should be called from np_transport_bw of the respective derived class More...
 
axi::fsm::fsm_handle * find_or_create (payload_type *gp=nullptr, bool ace=false)
 retrieve the FSM handle based on the transaction passed. If non exist one will be created More...
 
+void process_fsm_event ()
 processes the fsm_event_queue and triggers FSM aligned
 
+void process_fsm_clk_queue ()
 processes the fsm_clk_queue and triggers the FSM accordingly. Should be registered as rising-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, unsigned cycles)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, unsigned cycles)
 
+void schedule (axi::fsm::protocol_time_point_e e, tlm::scc::tlm_gp_shared_ptr &gp, sc_core::sc_time delay, bool syncronize=false)
 processes the fsm_sched_queue and propagates events to fsm_clk_queue. Should be registered as falling-edge clock callback
 
+void schedule (axi::fsm::protocol_time_point_e e, payload_type *gp, sc_core::sc_time delay, bool syncronize=false)
 
void react (axi::fsm::protocol_time_point_e event, tlm::scc::tlm_gp_shared_ptr &trans)
 triggers the FSM with event and given transaction More...
 
+void react (axi::fsm::protocol_time_point_e event, payload_type *trans)
 
+void react (axi::fsm::protocol_time_point_e, axi::fsm::fsm_handle *)
 
- Protected Member Functions inherited from axi::bw_blocking_transport_if< TYPES::tlm_payload_type >
virtual void b_snoop (TYPES::tlm_payload_type &trans, sc_core::sc_time &t)=0
 snoop access to a snooped master More...
 
- Protected Attributes inherited from axi::fsm::base
+::scc::peq< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, bool > > fsm_event_queue
 
+::scc::fifo_w_cb< std::tuple< axi::fsm::protocol_time_point_e, payload_type *, unsigned > > fsm_clk_queue
 
+sc_core::sc_process_handle fsm_clk_queue_hndl
 
+size_t transfer_width_in_bytes
 
+const axi::fsm::protocol_time_point_e wr_start
 
+const bool coherent
 
+std::unordered_map< payload_type *, axi::fsm::fsm_handle * > active_fsm
 
+std::deque< axi::fsm::fsm_handle * > idle_fsm
 
+std::vector< std::unique_ptr< axi::fsm::fsm_handle > > allocated_fsm
 
+std::string instance_name
 
+sc_core::sc_event finish_evt
 
+

Detailed Description

+

template<typename CFG>
+struct axi::pin::ace_target< CFG >

+ + +

Definition at line 36 of file ace_target.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1pin_1_1ace__target.js b/main/structaxi_1_1pin_1_1ace__target.js new file mode 100644 index 00000000..0c69019a --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target.js @@ -0,0 +1,9 @@ +var structaxi_1_1pin_1_1ace__target = +[ + [ "payload_type", "structaxi_1_1pin_1_1ace__target.html#a350e9f1d941cd3062057143da4b6472d", null ], + [ "phase_type", "structaxi_1_1pin_1_1ace__target.html#a264ce57e79ffa0392ca9c1968f5ea3f7", null ], + [ "ace_target", "structaxi_1_1pin_1_1ace__target.html#afb6bd99ea0dfd407a18e08454810b6ba", null ], + [ "SC_HAS_PROCESS", "structaxi_1_1pin_1_1ace__target.html#a6c0b1d5568f229baa7009664798d4f9f", null ], + [ "clk_i", "structaxi_1_1pin_1_1ace__target.html#a6cf5d5a6e9c6c89118368dd4a6df05d7", null ], + [ "isckt", "structaxi_1_1pin_1_1ace__target.html#ac049d53eff4b9e7ceb470dc2ac4dfed0", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__target__coll__graph.map b/main/structaxi_1_1pin_1_1ace__target__coll__graph.map new file mode 100644 index 00000000..f99ad1ee --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target__coll__graph.map @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__target__coll__graph.md5 b/main/structaxi_1_1pin_1_1ace__target__coll__graph.md5 new file mode 100644 index 00000000..3c127b3e --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target__coll__graph.md5 @@ -0,0 +1 @@ +7bd68a1dcc2ecf7c996f2cc92951cbdf \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__target__coll__graph.png b/main/structaxi_1_1pin_1_1ace__target__coll__graph.png new file mode 100644 index 00000000..c3c9086e Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__target__coll__graph.png differ diff --git a/main/structaxi_1_1pin_1_1ace__target__inherit__graph.map b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.map new file mode 100644 index 00000000..d06e46a3 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.map @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/main/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 new file mode 100644 index 00000000..5dc67943 --- /dev/null +++ b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.md5 @@ -0,0 +1 @@ +c05e3e0c17af4a4459d73a4906af4d4a \ No newline at end of file diff --git a/main/structaxi_1_1pin_1_1ace__target__inherit__graph.png b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.png new file mode 100644 index 00000000..d01a0cfc Binary files /dev/null and b/main/structaxi_1_1pin_1_1ace__target__inherit__graph.png differ diff --git a/main/structaxi_1_1rresp__ace-members.html b/main/structaxi_1_1rresp__ace-members.html new file mode 100644 index 00000000..b7247d91 --- /dev/null +++ b/main/structaxi_1_1rresp__ace-members.html @@ -0,0 +1,93 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::rresp_ace< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_ace< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + +
bind_r(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
bind_rresp(rresp_ace< CFG, OTYPES > &o) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
r_ack (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_data (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_id (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_last (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_ready (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_resp (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_trace (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_user (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
r_valid (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
rresp_ace()=default (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >
rresp_ace(const char *prefix) (defined in axi::rresp_ace< CFG, TYPES >)axi::rresp_ace< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1rresp__ace.html b/main/structaxi_1_1rresp__ace.html new file mode 100644 index 00000000..5c36af96 --- /dev/null +++ b/main/structaxi_1_1rresp__ace.html @@ -0,0 +1,136 @@ + + + + + + + +scc: axi::rresp_ace< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::rresp_ace< CFG, TYPES > Struct Template Reference
+
+
+ + + + + + + + + + +

+Public Member Functions

+ rresp_ace (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_ace< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_ace< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< CFG::RESPWIDTH > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+TYPES::template m2s_t< bool > r_ack {"r_ack"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::rresp_ace< CFG, TYPES >

+ + +

Definition at line 344 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1rresp__ace.js b/main/structaxi_1_1rresp__ace.js new file mode 100644 index 00000000..5ee47606 --- /dev/null +++ b/main/structaxi_1_1rresp__ace.js @@ -0,0 +1,16 @@ +var structaxi_1_1rresp__ace = +[ + [ "rresp_ace", "structaxi_1_1rresp__ace.html#ae61af314ce8b56e8e7521dc50ee8c0f3", null ], + [ "rresp_ace", "structaxi_1_1rresp__ace.html#a7b3ce32fa6be63bd426e21792a3262d0", null ], + [ "bind_r", "structaxi_1_1rresp__ace.html#a7341dfdd1b7a9139d62ffc93812429ca", null ], + [ "bind_rresp", "structaxi_1_1rresp__ace.html#a092d706292173a77ad831339be10cee3", null ], + [ "r_ack", "structaxi_1_1rresp__ace.html#a2e0aa1b049f4417d89b47448f7221e32", null ], + [ "r_data", "structaxi_1_1rresp__ace.html#a610f4aa1017d01dab7895be7f4fcbcf5", null ], + [ "r_id", "structaxi_1_1rresp__ace.html#a863e27eabf2f61949eb39b0566094224", null ], + [ "r_last", "structaxi_1_1rresp__ace.html#af11a234e23c78f071a0e536f936f201d", null ], + [ "r_ready", "structaxi_1_1rresp__ace.html#ac7d06011cc2092dede8a6b521cfddc53", null ], + [ "r_resp", "structaxi_1_1rresp__ace.html#a1ef63f969b1c7ee839e28fdde1928105", null ], + [ "r_trace", "structaxi_1_1rresp__ace.html#afb2e3415f35c03eb0af557e620aaac52", null ], + [ "r_user", "structaxi_1_1rresp__ace.html#af60b25459380de7461e5ccd1130e6e4a", null ], + [ "r_valid", "structaxi_1_1rresp__ace.html#a57857e73e309fd8fd0b3f8605ad6bd5f", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1rresp__axi-members.html b/main/structaxi_1_1rresp__axi-members.html new file mode 100644 index 00000000..25786f9a --- /dev/null +++ b/main/structaxi_1_1rresp__axi-members.html @@ -0,0 +1,94 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
axi::rresp_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + +
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_r(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
bind_rresp(rresp_axi_lite< CFG, OTYPES > &o) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
r_data (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_id (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_last (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_ready (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_resp (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_trace (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_user (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
r_valid (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi()=default (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >
rresp_axi(const char *prefix) (defined in axi::rresp_axi< CFG, TYPES >)axi::rresp_axi< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1rresp__axi.html b/main/structaxi_1_1rresp__axi.html new file mode 100644 index 00000000..396eec9b --- /dev/null +++ b/main/structaxi_1_1rresp__axi.html @@ -0,0 +1,151 @@ + + + + + + + +scc: axi::rresp_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+Public Member Functions | +Public Attributes | +List of all members
+
+
axi::rresp_axi< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::rresp_axi< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + +
[legend]
+ + + + + + + + + + + + + + + + +

+Public Member Functions

+ rresp_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_r (rresp_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_rresp (rresp_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template s2m_full_t< sc_dt::sc_uint< CFG::IDWIDTH > > r_id {"r_id"}
 
+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_full_t< bool > r_last {"r_last"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+TYPES::template s2m_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > r_user {"r_user"}
 
+TYPES::template s2m_opt_t< bool > r_trace {"r_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::rresp_axi< CFG, TYPES >

+ + +

Definition at line 308 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1rresp__axi.js b/main/structaxi_1_1rresp__axi.js new file mode 100644 index 00000000..92f035ec --- /dev/null +++ b/main/structaxi_1_1rresp__axi.js @@ -0,0 +1,17 @@ +var structaxi_1_1rresp__axi = +[ + [ "rresp_axi", "structaxi_1_1rresp__axi.html#aed5ce2c298bbde49b4ca1a03a355a798", null ], + [ "rresp_axi", "structaxi_1_1rresp__axi.html#abf07964f86dcd08fb1f0800f06196c54", null ], + [ "bind_r", "structaxi_1_1rresp__axi.html#a959db8736246a6f9efc3baacb593d243", null ], + [ "bind_r", "structaxi_1_1rresp__axi.html#ac70ba71a449cf31b9e3d3f94672dc933", null ], + [ "bind_rresp", "structaxi_1_1rresp__axi.html#aff10c6264f0c8569c22b2ed308e32721", null ], + [ "bind_rresp", "structaxi_1_1rresp__axi.html#a8ea3e2f8f34258bd554c2cadbad33123", null ], + [ "r_data", "structaxi_1_1rresp__axi.html#ae3ca7f71c5c5209bcddeb065ee033024", null ], + [ "r_id", "structaxi_1_1rresp__axi.html#ad610c9758dd6a9109b45be34ddd61168", null ], + [ "r_last", "structaxi_1_1rresp__axi.html#a9d8caa3e7ef61382fa7b5870f897a3ef", null ], + [ "r_ready", "structaxi_1_1rresp__axi.html#ad55fd4b1b0ca0f2ef9dfc6e33b9021e1", null ], + [ "r_resp", "structaxi_1_1rresp__axi.html#a7bfdec05e564eef8c1151a6db8ff7ae9", null ], + [ "r_trace", "structaxi_1_1rresp__axi.html#a91991c339f845e41c0c634815b422d34", null ], + [ "r_user", "structaxi_1_1rresp__axi.html#a291db1a699addf66aba410b1180303ec", null ], + [ "r_valid", "structaxi_1_1rresp__axi.html#a05a123376cb6b58a5351b4a23e130bda", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1rresp__axi__inherit__graph.map b/main/structaxi_1_1rresp__axi__inherit__graph.map new file mode 100644 index 00000000..60326aca --- /dev/null +++ b/main/structaxi_1_1rresp__axi__inherit__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/main/structaxi_1_1rresp__axi__inherit__graph.md5 b/main/structaxi_1_1rresp__axi__inherit__graph.md5 new file mode 100644 index 00000000..66a06fca --- /dev/null +++ b/main/structaxi_1_1rresp__axi__inherit__graph.md5 @@ -0,0 +1 @@ +beb5d85e60787caf68b114d3ee68794b \ No newline at end of file diff --git a/main/structaxi_1_1rresp__axi__inherit__graph.png b/main/structaxi_1_1rresp__axi__inherit__graph.png new file mode 100644 index 00000000..50857b8a Binary files /dev/null and b/main/structaxi_1_1rresp__axi__inherit__graph.png differ diff --git a/main/structaxi_1_1rresp__axi__lite-members.html b/main/structaxi_1_1rresp__axi__lite-members.html new file mode 100644 index 00000000..2b02e39c --- /dev/null +++ b/main/structaxi_1_1rresp__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
+
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+
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+
+ +
+
+
+
axi::rresp_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::rresp_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_r(rresp_axi< CFG, OTYPES > &o) (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >inline
r_data (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_ready (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_resp (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
r_valid (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
rresp_axi_lite()=default (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >
rresp_axi_lite(const char *prefix) (defined in axi::rresp_axi_lite< CFG, TYPES >)axi::rresp_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1rresp__axi__lite.html b/main/structaxi_1_1rresp__axi__lite.html new file mode 100644 index 00000000..b1ab216f --- /dev/null +++ b/main/structaxi_1_1rresp__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::rresp_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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axi::rresp_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

Read data channel signals. + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ rresp_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_r (rresp_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template s2m_t< typename CFG::data_t > r_data {"r_data"}
 
+TYPES::template s2m_t< sc_dt::sc_uint< 2 > > r_resp {"r_resp"}
 
+TYPES::template s2m_t< bool > r_valid {"r_valid"}
 
+TYPES::template m2s_t< bool > r_ready {"r_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::rresp_axi_lite< CFG, TYPES >

+ +

Read data channel signals.

+ +

Definition at line 467 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1rresp__axi__lite.js b/main/structaxi_1_1rresp__axi__lite.js new file mode 100644 index 00000000..feaab3cc --- /dev/null +++ b/main/structaxi_1_1rresp__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1rresp__axi__lite = +[ + [ "rresp_axi_lite", "structaxi_1_1rresp__axi__lite.html#a10da839a4295aea9e73adf34ef0f91ec", null ], + [ "rresp_axi_lite", "structaxi_1_1rresp__axi__lite.html#a00922fcb47239b3d1037dba1b273b272", null ], + [ "bind_r", "structaxi_1_1rresp__axi__lite.html#a9f9cc0115d8c5e672cf95cb45ffc9e88", null ], + [ "r_data", "structaxi_1_1rresp__axi__lite.html#a58cc6b71cbfe007f76e8f3472d2bf9b5", null ], + [ "r_ready", "structaxi_1_1rresp__axi__lite.html#a74a2482dba10dbe33191ece8dd2c9172", null ], + [ "r_resp", "structaxi_1_1rresp__axi__lite.html#a5032ba8ce4f600aea4e3983e0c620b0a", null ], + [ "r_valid", "structaxi_1_1rresp__axi__lite.html#a260591195046ba88ca10c43a7055c7b0", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1wdata__axi-members.html b/main/structaxi_1_1wdata__axi-members.html new file mode 100644 index 00000000..44aedc7b --- /dev/null +++ b/main/structaxi_1_1wdata__axi-members.html @@ -0,0 +1,95 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
+
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+ +
+
+
+
axi::wdata_axi< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::wdata_axi< CFG, TYPES >, including all inherited members.

+ + + + + + + + + + + + + + + + +
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_w(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
bind_wdata(wdata_axi_lite< CFG, OTYPES > &o) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
w_ack (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_data (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_id (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_last (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_ready (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_strb (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_trace (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_user (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
w_valid (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi()=default (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >
wdata_axi(const char *prefix) (defined in axi::wdata_axi< CFG, TYPES >)axi::wdata_axi< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1wdata__axi.html b/main/structaxi_1_1wdata__axi.html new file mode 100644 index 00000000..4b04fb5c --- /dev/null +++ b/main/structaxi_1_1wdata__axi.html @@ -0,0 +1,156 @@ + + + + + + + +scc: axi::wdata_axi< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
+
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axi::wdata_axi< CFG, TYPES > Struct Template Reference
+
+
+
+Inheritance diagram for axi::wdata_axi< CFG, TYPES >:
+
+
Inheritance graph
+ + + + + + + +
[legend]
+ + + + + + + + + + + + + + + + +

+Public Member Functions

+ wdata_axi (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_w (wdata_axi_lite< CFG, OTYPES > &o)
 
+template<typename OTYPES >
void bind_wdata (wdata_axi_lite< CFG, OTYPES > &o)
 
+ + + + + + + + + + + + + + + + + + + +

+Public Attributes

+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::IDWIDTH > > w_id {"w_id"}
 
+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_full_t< bool > w_last {"w_last"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+TYPES::template m2s_opt_t< sc_dt::sc_uint< CFG::USERWIDTH > > w_user {"w_user"}
 
+TYPES::template m2s_full_t< bool > w_ack {"w_ack"}
 
+TYPES::template m2s_opt_t< bool > w_trace {"w_trace"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES = master_types>
+struct axi::wdata_axi< CFG, TYPES >

+ + +

Definition at line 186 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1wdata__axi.js b/main/structaxi_1_1wdata__axi.js new file mode 100644 index 00000000..2805b443 --- /dev/null +++ b/main/structaxi_1_1wdata__axi.js @@ -0,0 +1,18 @@ +var structaxi_1_1wdata__axi = +[ + [ "wdata_axi", "structaxi_1_1wdata__axi.html#ab6fea06af6a69e51d234d4f09a6e443c", null ], + [ "wdata_axi", "structaxi_1_1wdata__axi.html#a085f7dba812e5ef8dd2ca18a7a4aef11", null ], + [ "bind_w", "structaxi_1_1wdata__axi.html#a227be2f584dc22c70f677145bfe827c4", null ], + [ "bind_w", "structaxi_1_1wdata__axi.html#a7f2bea298c2fc7f3148d56e62d96c23a", null ], + [ "bind_wdata", "structaxi_1_1wdata__axi.html#aba4fd3ab0eba131bbbe96cdf9f5cb57e", null ], + [ "bind_wdata", "structaxi_1_1wdata__axi.html#a1a6c6026d3c9ae1974217b120331d8c8", null ], + [ "w_ack", "structaxi_1_1wdata__axi.html#a385664fa77192e7eca1936c24f06cce3", null ], + [ "w_data", "structaxi_1_1wdata__axi.html#a6f18ff405009842fec2a44d9bf3e8017", null ], + [ "w_id", "structaxi_1_1wdata__axi.html#a6c6f08d7b3c8d6d5ceb32721dc80b7d8", null ], + [ "w_last", "structaxi_1_1wdata__axi.html#ae501c4578e95114a8420767c8f993639", null ], + [ "w_ready", "structaxi_1_1wdata__axi.html#af47c0f2c23b5be25cd02e1a42617293b", null ], + [ "w_strb", "structaxi_1_1wdata__axi.html#a676e556d99ed9beff14fd7ade22dc464", null ], + [ "w_trace", "structaxi_1_1wdata__axi.html#aee7a79a28b2b4451011e98bba23c74b1", null ], + [ "w_user", "structaxi_1_1wdata__axi.html#ae11626386d762fe4d6f269ce6834aa5f", null ], + [ "w_valid", "structaxi_1_1wdata__axi.html#a7ea49b79cd3b4a8800b8d1bafbdb1ef2", null ] +]; \ No newline at end of file diff --git a/main/structaxi_1_1wdata__axi__inherit__graph.map b/main/structaxi_1_1wdata__axi__inherit__graph.map new file mode 100644 index 00000000..fd5364e1 --- /dev/null +++ b/main/structaxi_1_1wdata__axi__inherit__graph.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/main/structaxi_1_1wdata__axi__inherit__graph.md5 b/main/structaxi_1_1wdata__axi__inherit__graph.md5 new file mode 100644 index 00000000..159ecf7c --- /dev/null +++ b/main/structaxi_1_1wdata__axi__inherit__graph.md5 @@ -0,0 +1 @@ +8bc168fba4804279e1423fc2571fe96b \ No newline at end of file diff --git a/main/structaxi_1_1wdata__axi__inherit__graph.png b/main/structaxi_1_1wdata__axi__inherit__graph.png new file mode 100644 index 00000000..6aca046a Binary files /dev/null and b/main/structaxi_1_1wdata__axi__inherit__graph.png differ diff --git a/main/structaxi_1_1wdata__axi__lite-members.html b/main/structaxi_1_1wdata__axi__lite-members.html new file mode 100644 index 00000000..0c96b432 --- /dev/null +++ b/main/structaxi_1_1wdata__axi__lite-members.html @@ -0,0 +1,87 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
axi::wdata_axi_lite< CFG, TYPES > Member List
+
+
+ +

This is the complete list of members for axi::wdata_axi_lite< CFG, TYPES >, including all inherited members.

+ + + + + + + + +
bind_w(wdata_axi< CFG, OTYPES > &o) (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >inline
w_data (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_ready (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_strb (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
w_valid (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
wdata_axi_lite()=default (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >
wdata_axi_lite(const char *prefix) (defined in axi::wdata_axi_lite< CFG, TYPES >)axi::wdata_axi_lite< CFG, TYPES >inline
+
+ + + + diff --git a/main/structaxi_1_1wdata__axi__lite.html b/main/structaxi_1_1wdata__axi__lite.html new file mode 100644 index 00000000..c60df887 --- /dev/null +++ b/main/structaxi_1_1wdata__axi__lite.html @@ -0,0 +1,123 @@ + + + + + + + +scc: axi::wdata_axi_lite< CFG, TYPES > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+Public Member Functions | +Public Attributes | +List of all members
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axi::wdata_axi_lite< CFG, TYPES > Struct Template Reference
+
+
+ +

write data channel signals + More...

+ +

#include <signal_if.h>

+ + + + + + + +

+Public Member Functions

+ wdata_axi_lite (const char *prefix)
 
+template<typename OTYPES >
void bind_w (wdata_axi< CFG, OTYPES > &o)
 
+ + + + + + + + + +

+Public Attributes

+TYPES::template m2s_t< typename CFG::data_t > w_data {"w_data"}
 
+TYPES::template m2s_t< sc_dt::sc_uint< CFG::BUSWIDTH/8 > > w_strb {"w_strb"}
 
+TYPES::template m2s_t< bool > w_valid {"w_valid"}
 
+TYPES::template s2m_t< bool > w_ready {"w_ready"}
 
+

Detailed Description

+

template<typename CFG, typename TYPES>
+struct axi::wdata_axi_lite< CFG, TYPES >

+ +

write data channel signals

+ +

Definition at line 404 of file signal_if.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structaxi_1_1wdata__axi__lite.js b/main/structaxi_1_1wdata__axi__lite.js new file mode 100644 index 00000000..2a9f7486 --- /dev/null +++ b/main/structaxi_1_1wdata__axi__lite.js @@ -0,0 +1,10 @@ +var structaxi_1_1wdata__axi__lite = +[ + [ "wdata_axi_lite", "structaxi_1_1wdata__axi__lite.html#a3e9d650b47bd083f8eba24563aaabe42", null ], + [ "wdata_axi_lite", "structaxi_1_1wdata__axi__lite.html#a93b3a687cb6aac1f066af8873b7b3a4b", null ], + [ "bind_w", "structaxi_1_1wdata__axi__lite.html#adddf758c62f44aea560cf7d5ad179916", null ], + [ "w_data", "structaxi_1_1wdata__axi__lite.html#a65eed7c10fb70f58b1ef85dc64fd70fc", null ], + [ "w_ready", "structaxi_1_1wdata__axi__lite.html#a7dd039028cd627c1e162d70226b1369a", null ], + [ "w_strb", "structaxi_1_1wdata__axi__lite.html#a8fa80664451077881e4775f21eb3d900", null ], + [ "w_valid", "structaxi_1_1wdata__axi__lite.html#aa13809572afb4c947da11268ea5aa0b9", null ] +]; \ No newline at end of file diff --git a/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html b/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html new file mode 100644 index 00000000..59dd2ce7 --- /dev/null +++ b/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4-members.html @@ -0,0 +1,81 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
chi::enable_for_enum< rsp_resperrtype_e > Member List
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This is the complete list of members for chi::enable_for_enum< rsp_resperrtype_e >, including all inherited members.

+ + +
enable (defined in chi::enable_for_enum< rsp_resperrtype_e >)chi::enable_for_enum< rsp_resperrtype_e >static
+
+ + + + diff --git a/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html b/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html new file mode 100644 index 00000000..994b9e8f --- /dev/null +++ b/main/structchi_1_1enable__for__enum_3_01rsp__resperrtype__e_01_4.html @@ -0,0 +1,94 @@ + + + + + + + +scc: chi::enable_for_enum< rsp_resperrtype_e > Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Static Public Attributes | +List of all members
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chi::enable_for_enum< rsp_resperrtype_e > Struct Reference
+
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+ + + + +

+Static Public Attributes

+static const bool enable = true
 
+

Detailed Description

+
+

Definition at line 1087 of file chi_tlm.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__discrete__restriction-members.html b/main/structscc_1_1__discrete__restriction-members.html new file mode 100644 index 00000000..2f58c957 --- /dev/null +++ b/main/structscc_1_1__discrete__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
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+
scc::_discrete_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_discrete_restriction< T >, including all inherited members.

+ + + + +
_discrete_restriction(COLLECTION_TYPE values) (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >inline
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >inline
values (defined in scc::_discrete_restriction< T >)scc::_discrete_restriction< T >
+
+ + + + diff --git a/main/structscc_1_1__discrete__restriction.html b/main/structscc_1_1__discrete__restriction.html new file mode 100644 index 00000000..dc26c3f5 --- /dev/null +++ b/main/structscc_1_1__discrete__restriction.html @@ -0,0 +1,108 @@ + + + + + + + +scc: scc::_discrete_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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scc::_discrete_restriction< T > Struct Template Reference
+
+
+ + + + + + + +

+Public Member Functions

+template<typename COLLECTION_TYPE >
 _discrete_restriction (COLLECTION_TYPE values)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+std::unordered_set< T > const values
 
+

Detailed Description

+

template<typename T>
+struct scc::_discrete_restriction< T >

+ + +

Definition at line 75 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__discrete__restriction.js b/main/structscc_1_1__discrete__restriction.js new file mode 100644 index 00000000..3349802a --- /dev/null +++ b/main/structscc_1_1__discrete__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__discrete__restriction = +[ + [ "_discrete_restriction", "structscc_1_1__discrete__restriction.html#a5a25f5eafbd0de4b333d2ddb1459870c", null ], + [ "operator()", "structscc_1_1__discrete__restriction.html#abb01c560c44197b1a774f4c97eae9f15", null ], + [ "values", "structscc_1_1__discrete__restriction.html#ac09374f8554ab2097d1f381fa23be542", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__max__excl__restriction-members.html b/main/structscc_1_1__max__excl__restriction-members.html new file mode 100644 index 00000000..50d4a6b0 --- /dev/null +++ b/main/structscc_1_1__max__excl__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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SystemC components library
+
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+
scc::_max_excl_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_max_excl_restriction< T >, including all inherited members.

+ + + + +
_max_excl_restriction(T max) (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >inline
max (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_max_excl_restriction< T >)scc::_max_excl_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__max__excl__restriction.html b/main/structscc_1_1__max__excl__restriction.html new file mode 100644 index 00000000..a76c86fc --- /dev/null +++ b/main/structscc_1_1__max__excl__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_max_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
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+
+
+Public Member Functions | +Public Attributes | +List of all members
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scc::_max_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _max_excl_restriction (T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_max_excl_restriction< T >

+ + +

Definition at line 67 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__max__excl__restriction.js b/main/structscc_1_1__max__excl__restriction.js new file mode 100644 index 00000000..9c9c217a --- /dev/null +++ b/main/structscc_1_1__max__excl__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__max__excl__restriction = +[ + [ "_max_excl_restriction", "structscc_1_1__max__excl__restriction.html#a4d0ecc4b22a2f6cdc18b5bd01891fe5e", null ], + [ "operator()", "structscc_1_1__max__excl__restriction.html#a64366d04c3700ad0db579d069fa2bad6", null ], + [ "max", "structscc_1_1__max__excl__restriction.html#a9d6ac59482e2350361cc983e24692fc7", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__max__restriction-members.html b/main/structscc_1_1__max__restriction-members.html new file mode 100644 index 00000000..cbacc95e --- /dev/null +++ b/main/structscc_1_1__max__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+
scc::_max_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_max_restriction< T >, including all inherited members.

+ + + + +
_max_restriction(T max) (defined in scc::_max_restriction< T >)scc::_max_restriction< T >inline
max (defined in scc::_max_restriction< T >)scc::_max_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_max_restriction< T >)scc::_max_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__max__restriction.html b/main/structscc_1_1__max__restriction.html new file mode 100644 index 00000000..779fe408 --- /dev/null +++ b/main/structscc_1_1__max__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_max_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+
+Public Member Functions | +Public Attributes | +List of all members
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+
scc::_max_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _max_restriction (T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_max_restriction< T >

+ + +

Definition at line 59 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__max__restriction.js b/main/structscc_1_1__max__restriction.js new file mode 100644 index 00000000..d0434c97 --- /dev/null +++ b/main/structscc_1_1__max__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__max__restriction = +[ + [ "_max_restriction", "structscc_1_1__max__restriction.html#a9c23b9701eb894a8bc6dcc9e485fef21", null ], + [ "operator()", "structscc_1_1__max__restriction.html#a0d0c527133192d5818ae6e2a64c8d5e4", null ], + [ "max", "structscc_1_1__max__restriction.html#a02c3e3e505b01e01aa4597e293263242", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__min__excl__restriction-members.html b/main/structscc_1_1__min__excl__restriction-members.html new file mode 100644 index 00000000..1967fd8a --- /dev/null +++ b/main/structscc_1_1__min__excl__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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scc +  2022.4.0 +
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SystemC components library
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scc::_min_excl_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_excl_restriction< T >, including all inherited members.

+ + + + +
_min_excl_restriction(T min) (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >inline
min (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_excl_restriction< T >)scc::_min_excl_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__min__excl__restriction.html b/main/structscc_1_1__min__excl__restriction.html new file mode 100644 index 00000000..8cd66e3e --- /dev/null +++ b/main/structscc_1_1__min__excl__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_min_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
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+Public Member Functions | +Public Attributes | +List of all members
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scc::_min_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_excl_restriction (T min)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const min
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_excl_restriction< T >

+ + +

Definition at line 51 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__min__excl__restriction.js b/main/structscc_1_1__min__excl__restriction.js new file mode 100644 index 00000000..2e11aa9c --- /dev/null +++ b/main/structscc_1_1__min__excl__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__min__excl__restriction = +[ + [ "_min_excl_restriction", "structscc_1_1__min__excl__restriction.html#a01ab6129292a9784ee8f94518b96fd71", null ], + [ "operator()", "structscc_1_1__min__excl__restriction.html#a971103e984f937c810bff047f9cfde9f", null ], + [ "min", "structscc_1_1__min__excl__restriction.html#a78fbe1b131f778e8842939f8d10c0a99", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__min__max__excl__restriction-members.html b/main/structscc_1_1__min__max__excl__restriction-members.html new file mode 100644 index 00000000..19cceec8 --- /dev/null +++ b/main/structscc_1_1__min__max__excl__restriction-members.html @@ -0,0 +1,84 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+
scc::_min_max_excl_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_min_max_excl_restriction< T >, including all inherited members.

+ + + + + +
_min_max_excl_restriction(T min, T max) (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >inline
max (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >
min (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_max_excl_restriction< T >)scc::_min_max_excl_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__min__max__excl__restriction.html b/main/structscc_1_1__min__max__excl__restriction.html new file mode 100644 index 00000000..034a2ef0 --- /dev/null +++ b/main/structscc_1_1__min__max__excl__restriction.html @@ -0,0 +1,110 @@ + + + + + + + +scc: scc::_min_max_excl_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
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+Public Member Functions | +Public Attributes | +List of all members
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+
scc::_min_max_excl_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_max_excl_restriction (T min, T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + + + +

+Public Attributes

+T const min
 
+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_max_excl_restriction< T >

+ + +

Definition at line 33 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__min__max__excl__restriction.js b/main/structscc_1_1__min__max__excl__restriction.js new file mode 100644 index 00000000..5e1a61c0 --- /dev/null +++ b/main/structscc_1_1__min__max__excl__restriction.js @@ -0,0 +1,7 @@ +var structscc_1_1__min__max__excl__restriction = +[ + [ "_min_max_excl_restriction", "structscc_1_1__min__max__excl__restriction.html#a8d8626c7fa578acac5ab91d0b0e956b4", null ], + [ "operator()", "structscc_1_1__min__max__excl__restriction.html#a68b53f3da65b99c473259018d935fd2f", null ], + [ "max", "structscc_1_1__min__max__excl__restriction.html#a52b619df3ab17d0f8aa8b4eacddbfd3d", null ], + [ "min", "structscc_1_1__min__max__excl__restriction.html#a5ee759edf3653def287d307acbf045e4", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__min__max__restriction-members.html b/main/structscc_1_1__min__max__restriction-members.html new file mode 100644 index 00000000..7c5c2ebb --- /dev/null +++ b/main/structscc_1_1__min__max__restriction-members.html @@ -0,0 +1,84 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
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+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
scc::_min_max_restriction< T > Member List
+
+
+ +

This is the complete list of members for scc::_min_max_restriction< T >, including all inherited members.

+ + + + + +
_min_max_restriction(T min, T max) (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >inline
max (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >
min (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_max_restriction< T >)scc::_min_max_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__min__max__restriction.html b/main/structscc_1_1__min__max__restriction.html new file mode 100644 index 00000000..74087bb4 --- /dev/null +++ b/main/structscc_1_1__min__max__restriction.html @@ -0,0 +1,110 @@ + + + + + + + +scc: scc::_min_max_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
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+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_min_max_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_max_restriction (T min, T max)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + + + +

+Public Attributes

+T const min
 
+T const max
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_max_restriction< T >

+ + +

Definition at line 23 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__min__max__restriction.js b/main/structscc_1_1__min__max__restriction.js new file mode 100644 index 00000000..40afacd5 --- /dev/null +++ b/main/structscc_1_1__min__max__restriction.js @@ -0,0 +1,7 @@ +var structscc_1_1__min__max__restriction = +[ + [ "_min_max_restriction", "structscc_1_1__min__max__restriction.html#aff665e4a73dbce31a258e6b7e08ae459", null ], + [ "operator()", "structscc_1_1__min__max__restriction.html#a9a0d4d7606b62fa1e122d6e933dc663d", null ], + [ "max", "structscc_1_1__min__max__restriction.html#a965362acfd28304d0ddf19c4b4524623", null ], + [ "min", "structscc_1_1__min__max__restriction.html#aff4250c15f1523b5bda33ad9e843f7f0", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1__min__restriction-members.html b/main/structscc_1_1__min__restriction-members.html new file mode 100644 index 00000000..e27984e1 --- /dev/null +++ b/main/structscc_1_1__min__restriction-members.html @@ -0,0 +1,83 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::_min_restriction< T > Member List
+
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+ +

This is the complete list of members for scc::_min_restriction< T >, including all inherited members.

+ + + + +
_min_restriction(T min) (defined in scc::_min_restriction< T >)scc::_min_restriction< T >inline
min (defined in scc::_min_restriction< T >)scc::_min_restriction< T >
operator()(cci::cci_param_write_event< T > const &ev) const (defined in scc::_min_restriction< T >)scc::_min_restriction< T >inline
+
+ + + + diff --git a/main/structscc_1_1__min__restriction.html b/main/structscc_1_1__min__restriction.html new file mode 100644 index 00000000..38e28b87 --- /dev/null +++ b/main/structscc_1_1__min__restriction.html @@ -0,0 +1,107 @@ + + + + + + + +scc: scc::_min_restriction< T > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+Public Member Functions | +Public Attributes | +List of all members
+
+
scc::_min_restriction< T > Struct Template Reference
+
+
+ + + + + + +

+Public Member Functions

+ _min_restriction (T min)
 
+bool operator() (cci::cci_param_write_event< T > const &ev) const
 
+ + + +

+Public Attributes

+T const min
 
+

Detailed Description

+

template<typename T>
+struct scc::_min_restriction< T >

+ + +

Definition at line 43 of file cci_param_restricted.h.

+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1__min__restriction.js b/main/structscc_1_1__min__restriction.js new file mode 100644 index 00000000..66667a98 --- /dev/null +++ b/main/structscc_1_1__min__restriction.js @@ -0,0 +1,6 @@ +var structscc_1_1__min__restriction = +[ + [ "_min_restriction", "structscc_1_1__min__restriction.html#a538771b6826f30d7ed178c00b7bdace4", null ], + [ "operator()", "structscc_1_1__min__restriction.html#a6d60e43565bd944f05210c49d09b7ec1", null ], + [ "min", "structscc_1_1__min__restriction.html#aedd6ccc772278d2ba6b25d851bd6298c", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1cci__param__restricted-members.html b/main/structscc_1_1cci__param__restricted-members.html new file mode 100644 index 00000000..2d368b1f --- /dev/null +++ b/main/structscc_1_1cci__param__restricted-members.html @@ -0,0 +1,82 @@ + + + + + + + +scc: Member List + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
scc::cci_param_restricted< T, TM > Member List
+
+
+ +

This is the complete list of members for scc::cci_param_restricted< T, TM >, including all inherited members.

+ + + +
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())scc::cci_param_restricted< T, TM >inline
cci_param_restricted(const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())scc::cci_param_restricted< T, TM >inline
+
+ + + + diff --git a/main/structscc_1_1cci__param__restricted.html b/main/structscc_1_1cci__param__restricted.html new file mode 100644 index 00000000..ddd57556 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted.html @@ -0,0 +1,295 @@ + + + + + + + +scc: scc::cci_param_restricted< T, TM > Struct Template Reference + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+List of all members
+
+
scc::cci_param_restricted< T, TM > Struct Template Reference
+
+
+ +

extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter. + More...

+ +

#include <cci_param_restricted.h>

+
+Inheritance diagram for scc::cci_param_restricted< T, TM >:
+
+
Inheritance graph
+ + + + +
[legend]
+
+Collaboration diagram for scc::cci_param_restricted< T, TM >:
+
+
Collaboration graph
+ + + + +
[legend]
+ + + + + + + + + +

+Public Member Functions

Constructors
template<typename RESTR >
 cci_param_restricted (const std::string &name, const T &default_value, RESTR const &restr, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
 
template<typename RESTR >
 cci_param_restricted (const std::string &name, const T &default_value, RESTR const &restr, cci::cci_broker_handle private_broker, const std::string &desc="", cci::cci_name_type name_type=cci::CCI_RELATIVE_NAME, const cci::cci_originator &originator=cci::cci_originator())
 
+

Detailed Description

+

template<typename T, cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+struct scc::cci_param_restricted< T, TM >

+ +

extension of cci_param<T, TM> which automatically registeres a callback to restrict the valid values given to the parameter.

+
Template Parameters
+ + + +
Ttype of the parameter value
TMspecifies the parameter type lock behavior
+
+
+ +

Definition at line 180 of file cci_param_restricted.h.

+

Constructor & Destructor Documentation

+ +

◆ cci_param_restricted() [1/2]

+ +
+
+
+template<typename T , cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+
+template<typename RESTR >
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
scc::cci_param_restricted< T, TM >::cci_param_restricted (const std::string & name,
const T & default_value,
RESTR const & restr,
const std::string & desc = "",
cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
const cci::cci_originator & originator = cci::cci_originator() 
)
+ 		+inline
+
+

Constructor with (local/hierarchical) name, default value, restriction, description and originator.

+
Parameters
+ + + + + + + +
nameName of the parameter
default_valueDefault value of the parameter (Typed value)
restrRestriction to apply, will be checked befor every write
descDescription of the parameter
name_typeEither the name should be absolute or relative
originatorOriginator of the parameter
+
+
+ +

Definition at line 196 of file cci_param_restricted.h.

+ +
+
+ +

◆ cci_param_restricted() [2/2]

+ +
+
+
+template<typename T , cci::cci_param_mutable_type TM = cci::CCI_MUTABLE_PARAM>
+
+template<typename RESTR >
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
scc::cci_param_restricted< T, TM >::cci_param_restricted (const std::string & name,
const T & default_value,
RESTR const & restr,
cci::cci_broker_handle private_broker,
const std::string & desc = "",
cci::cci_name_type name_type = cci::CCI_RELATIVE_NAME,
const cci::cci_originator & originator = cci::cci_originator() 
)
+ 		+inline
+
+

Constructor with (local/hierarchical) name, default value, restriction, private broker, description, name type and originator.

+
Parameters
+ + + + + + + + +
nameName of the parameter
default_valueDefault value of the parameter (Typed value)
private_brokerAssociated private broker
restrRestriction to apply, will be checked befor every write
descDescription of the parameter
name_typeEither the name should be absolute or relative
originatorOriginator of the parameter
+
+
+ +

Definition at line 217 of file cci_param_restricted.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/main/structscc_1_1cci__param__restricted.js b/main/structscc_1_1cci__param__restricted.js new file mode 100644 index 00000000..a89b8bf3 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted.js @@ -0,0 +1,5 @@ +var structscc_1_1cci__param__restricted = +[ + [ "cci_param_restricted", "structscc_1_1cci__param__restricted.html#a6b7f0b6ac7677e10cc8ad1a0fd3e3629", null ], + [ "cci_param_restricted", "structscc_1_1cci__param__restricted.html#aeafefd5891fb058a13d6dd40f9325ac4", null ] +]; \ No newline at end of file diff --git a/main/structscc_1_1cci__param__restricted__coll__graph.map b/main/structscc_1_1cci__param__restricted__coll__graph.map new file mode 100644 index 00000000..ee591705 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/main/structscc_1_1cci__param__restricted__coll__graph.md5 b/main/structscc_1_1cci__param__restricted__coll__graph.md5 new file mode 100644 index 00000000..5d5c2843 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted__coll__graph.md5 @@ -0,0 +1 @@ +53f739e8bfb0226fcc469a28a6e12a56 \ No newline at end of file diff --git a/main/structscc_1_1cci__param__restricted__coll__graph.png b/main/structscc_1_1cci__param__restricted__coll__graph.png new file mode 100644 index 00000000..2f9b41f7 Binary files /dev/null and b/main/structscc_1_1cci__param__restricted__coll__graph.png differ diff --git a/main/structscc_1_1cci__param__restricted__inherit__graph.map b/main/structscc_1_1cci__param__restricted__inherit__graph.map new file mode 100644 index 00000000..ee591705 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted__inherit__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/main/structscc_1_1cci__param__restricted__inherit__graph.md5 b/main/structscc_1_1cci__param__restricted__inherit__graph.md5 new file mode 100644 index 00000000..5d5c2843 --- /dev/null +++ b/main/structscc_1_1cci__param__restricted__inherit__graph.md5 @@ -0,0 +1 @@ +53f739e8bfb0226fcc469a28a6e12a56 \ No newline at end of file diff --git a/main/structscc_1_1cci__param__restricted__inherit__graph.png b/main/structscc_1_1cci__param__restricted__inherit__graph.png new file mode 100644 index 00000000..2f9b41f7 Binary files /dev/null and b/main/structscc_1_1cci__param__restricted__inherit__graph.png differ diff --git a/main/target__info__if_8h_source.html b/main/target__info__if_8h_source.html new file mode 100644 index 00000000..e6fc92bf --- /dev/null +++ b/main/target__info__if_8h_source.html @@ -0,0 +1,104 @@ + + + + + + + +scc: /home/eyck/git/SystemC-Components/third_party/axi_chi/axi/pe/target_info_if.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
scc +  2022.4.0 +
+
SystemC components library
+
+
+ + + + + + +
+
+ +
+
+
+ +
+
+
+
target_info_if.h
+
+
+
1 /*
+
2  * target_info_if.h
+
3  *
+
4  * Created on: Aug 23, 2023
+
5  * Author: eyckj
+
6  */
+
7 
+
8 #ifndef _AXI_PE_TARGET_INFO_IF_H_
+
9 #define _AXI_PE_TARGET_INFO_IF_H_
+
10 
+
11 namespace axi {
+
12 namespace pe {
+
13 
+
14 class target_info_if {
+
15 public:
+
16  virtual ~target_info_if() = default;
+
17 
+
18  virtual size_t get_outstanding_tx_count() = 0;
+
19 };
+
20 
+
21 } /* namespace pe */
+
22 } /* namespace axi */
+
23 
+
24 #endif /* _AXI_PE_TARGET_INFO_IF_H_ */
+
axi::pe::target_info_if
Definition: target_info_if.h:14
+
axi
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
+
+
+ + + +