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files.qip
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/xain_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore.sv
set_global_assignment -name SDC_FILE Arcade-XSleena.sdc
set_global_assignment -name SYSTEMVERILOG_FILE Arcade-XSleena.sv
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/jtframe_resync.v
set_global_assignment -name VERILOG_FILE rtl/pause.v
set_global_assignment -name VERILOG_FILE rtl/joy_db15.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdr_req_manager_single.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdr_req_manager.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_BACK1.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_BACK2.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_CLK.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_CLK_CEN.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_cpuA_B.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_IO.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_MAP.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_OBJ.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_RGB4bitLUT.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenaCore_SoundCPU.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/XSleenacore_VideoMixer.sv
set_global_assignment -name VERILOG_FILE rtl/jtframe_frac_cen.v
set_global_assignment -name VERILOG_FILE rtl/cpu/mc6809.v
set_global_assignment -name VERILOG_FILE rtl/cpu/mc6809e.v
set_global_assignment -name VERILOG_FILE rtl/cpu/mc6809i.v
set_global_assignment -name VERILOG_FILE rtl/cpu/mc6809is.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rom.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/memory/dpram_dc.vhd
set_global_assignment -name VERILOG_FILE rtl/memory/ROM_sync.v
set_global_assignment -name VHDL_FILE rtl/memory/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/memory/SRAM_dual_sync.v
set_global_assignment -name VERILOG_FILE rtl/memory/SRAM_dual_sync_init.v
set_global_assignment -name VERILOG_FILE rtl/memory/SRAM_sync.v
set_global_assignment -name VERILOG_FILE rtl/memory/SRAM_sync_init.v
set_global_assignment -name VERILOG_FILE rtl/memory/SRAM_sync_noinit.v
set_global_assignment -name QIP_FILE rtl/pll/pll_0002.qip
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/DFF_pseudoAsyncClrPre.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/helper.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74157.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74138.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74139.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ttl_sync/n8bit_counter.sv
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74112_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74161a_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74161_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74163a_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74174_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74194_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74257_noHiZout.v
set_global_assignment -name VERILOG_FILE rtl/ttl_sync/ttl_74273_sync.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ttl_sync/ttl_74374_sync_noHiZout.sv
set_global_assignment -name QIP_FILE rtl/pll/pll_0002.qip -library pll
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_noise.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_exp.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_eg.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_div.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_cen.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49_bus.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt49.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_top.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_timers.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_sumch.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_single_acc.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_sh24.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_sh_rst.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_sh.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_reg.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pm.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pg_sum.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pg_inc.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pg_dt.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pg_comb.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_pg.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_op.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_mod.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_mmr.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_logsin.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_lfo.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_kon.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_exprom.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_step.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_pure.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_final.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_ctrl.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_comb.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg_cnt.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_eg.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_dout.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_div.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt12_csr.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt03_acc.v
set_global_assignment -name VERILOG_FILE rtl/jt12/jt03.v