ERPLAG is a strongly typed, compiled language. It is minimalist because it currently does not encompass the full capabilities of most modern programming languages like character and string handling or defining structs/classes.
- gcc >= 7.0
- nasm >= 2.14.02
The code has been tested in Ubuntu >= 16.04, and the README has been prepared accordingly. Users of other OSes will need to figure out the equivalent commands or supporting software wherever applicable.
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Clone the repository
$ git clone https://github.com/MayankJasoria/Compiler-Project.git
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Build
$ cd Compiler-Project $ make
This should create a binary file named 'compiler' in the same directory.
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Execute
Run the ERPLAG compiler in the following manner:$ ./compiler <source-code> <assembly-file>.asm $ nasm -f elf64 <assembly-file>.asm $ gcc -no-pie <assembly-file>.o -o <output>.out $ ./<output>.out
ERPLAG supports the following features:
- Primitive datatypes - integers, floating points
- Non-primitive - arrays, boolean
- Basic arithmetic operations - add, subtract, multiply, divide
- Statements:
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Comments
Examples:** single line comment ** ** Multiline comment **
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Declarative
Examples:
Declaring variables:declare index:integer; declare t:boolean; declare s:real;
Declaring a module:
declare module readArr;
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Assignment
Examples:sum := sum + 4; ** Integer assignment ** pi := 3.14; ** Floating point assignment ** bool2 := a < b ** Boolean assignment ** arr2 := arr1; ** Assigning one array into another variable **
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Input/output
Examples:
Input:get_value(var);
Output
print(var);
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Conditional
Examples:switch(c) ** switch case on boolean ** start case true: ** statements **; break; case false: ** statements **; break; end switch(int1) ** switch case on integer ** start case 1: ** statements ** break; case 2: ** statements ** case 3: ** statements ** break; default: ** statements ** end
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Iterative
Examples: While loopwhile(a >= b) start ** statements ** end
For loop
for(idx1 in 1..10) start ** statements ** end
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Module declaration and call
Examples:Driver (main) module
Note: Driver module is the entry-point of an ERPLAG program.<<<driver program>>> start ** statements ** end
Module declaration
declare module m1; ** allows module definition to be given after 'driver' ** <<module arraySum>> ** Declaration and definition may be combined this way, if it appears in the code before driver module ** takes input[list:array[1..15] of real, n:integer]; returns [sum:real]; start ** statements ** end <<module printReal>> takes input[n:real]; start print(n); end
Module call
[sum]:= use module arraySum with parameters A,k; use module printReal with parameters pi;
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A detailed language specification can be found here.
This project is no longer under active development. Any issues opened on this repository are likely to be ignored. However, well worked out pull requests are entertained.