Digital Logic Circuit (Reti Logiche) Project - 2022

Digital Logic Circuit (Reti Logiche) Project - Politecnico di Milano - Academic Year 2021/2022

Overview

This project, completed as part of a course at POLIMI, focuses on the design and implementation of a hardware component described in VHDL. The component interfaces with a memory system and processes sequences using a convolutional code (½ rate), commonly used in telecommunications to ensure reliable data transmission. The design encodes input sequences into output sequences by applying a transformation that doubles the number of words. The project involves the creation of a state machine (FSM) to manage the encoding process and interaction with memory.

Final grade: 30/30

For more details, please refer to the project report.

Authors

• Paci Emanuele (@emanuelePaci)

• Paleari Lorenzo (@LorenzoPaleari)

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All documentation and the final report have been written in Italian.