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librepcb_ko_KR.ts
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<?xml version="1.0" ?><!DOCTYPE TS><TS version="2.1" language="ko_KR" sourcelanguage="en">
<context>
<name>ArchiveOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/archiveoutputjob.cpp" line="42"/>
<source>Output Archive</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/job/archiveoutputjob.h" line="71"/>
<source>Archive</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>AttributeKey</name>
<message>
<location filename="../libs/librepcb/core/attribute/attributekey.h" line="55"/>
<source>Invalid attribute key: '%1'</source>
<translation>잘못된 속성 키: '%1'</translation>
</message>
</context>
<context>
<name>AttributeType</name>
<message>
<location filename="../libs/librepcb/core/attribute/attributetype.cpp" line="77"/>
<source>Unknown unit of attribute type "%1": "%2"</source>
<translation>알 수 없는 속성 단위 "%1": "%2"</translation>
</message>
<message>
<location filename="../libs/librepcb/core/attribute/attributetype.cpp" line="124"/>
<source>Invalid attribute type: "%1"</source>
<translation>잘못된 속성 유형: "%1"</translation>
</message>
</context>
<context>
<name>BGI_FootprintPad</name>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="164"/>
<source>Pad:</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="170"/>
<source>Signal:</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="176"/>
<source>Net:</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>BGI_Via</name>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="248"/>
<source>Through-Hole Via</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="250"/>
<source>Blind Via</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="252"/>
<source>Buried Via</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="254"/>
<source>Net: %1</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="256"/>
<source>Start Layer: %1</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="257"/>
<source>End Layer: %1</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>Board3DOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/board3doutputjob.cpp" line="39"/>
<source>STEP Model</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/job/board3doutputjob.h" line="73"/>
<source>3D Model</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>BoardDesignRuleCheckMessages</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="53"/>
<source>Depending on the capabilities of the PCB manufacturer, this could cause higher costs or even serious troubles during production, leading to a possibly non-functional PCB.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="64"/>
<source>(no net)</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>BomOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/bomoutputjob.cpp" line="40"/>
<source>Bill of Materials</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/job/bomoutputjob.h" line="79"/>
<source>Bill Of Materials</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>BoundedUnsignedRatio</name>
<message>
<location filename="../libs/librepcb/core/types/boundedunsignedratio.cpp" line="108"/>
<source>Minimum value must not be greater than maximum value.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>CircuitIdentifier</name>
<message>
<location filename="../libs/librepcb/core/types/circuitidentifier.h" line="53"/>
<source>Invalid identifier: '%1'</source>
<translation>잘못된 식별자: '%1'</translation>
</message>
</context>
<context>
<name>CmpSigPinDisplayType</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="95"/>
<source>None (no text)</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="101"/>
<source>Symbol pin name</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="107"/>
<source>Component signal name</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="113"/>
<source>Schematic net name</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>CommandLineInterface</name>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="86"/>
<source>Open a project to execute project-related tasks.</source>
<translation>프로젝트 관련 작업을 실행할 프로젝트를 엽니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="89"/>
<source>Open a library to execute library-related tasks.</source>
<translation>라이브러리 관련 작업을 실행하기 위해 라이브러리 열기.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="92"/>
<source>Open a STEP model to execute STEP-related tasks outside of a library.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="99"/>
<source>LibrePCB Command Line Interface</source>
<translation>LibrePCB 명령줄 인터페이스</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="102"/>
<source>Print this message.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="105"/>
<source>Displays version information.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="107"/>
<source>Verbose output.</source>
<translation>자세한 출력.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="110"/>
<source>The command to execute (see list below).</source>
<translation>실행 명령어 (아래 목록 참조).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="116"/>
<source>Run the electrical rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>전기 규칙 검사를 실행하고 승인되지 않은 모든 경고/오류를 인쇄하고 승인되지 않은 메시지가 있는 경우 실패(종료 코드 = 1)를 보고합니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="121"/>
<source>Run the design rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="126"/>
<source>Override DRC settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="129"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="141"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="152"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="158"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="164"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="181"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="187"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="194"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="200"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="282"/>
<source>file</source>
<translation>파일</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="132"/>
<source>Run a particular output job. Can be given multiple times to run multiple jobs.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="134"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="205"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="222"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="234"/>
<source>name</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="136"/>
<source>Run all existing output jobs.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="139"/>
<source>Override output jobs with a *.lp file containing custom jobs. If not set, the jobs from the project will be used instead.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="144"/>
<source>Override the output base directory of jobs. If not set, the standard output directory from the project is used.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="146"/>
<source>path</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="149"/>
<source>Export schematics to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>주어진 파일로 회로도를 내보냅니다. 기존 파일을 덮어씁니다. 지원되는 파일 확장자: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="155"/>
<source>Export generic BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>일반 BOM을 지정된 파일로 내보냅니다. 기존 파일을 덮어씁니다. 지원되는 파일 확장자: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="161"/>
<source>Export board-specific BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>보드사양별 BOM을 지정된 파일로 내보냅니다. 기존 파일을 덮어씁니다. 지원되는 파일 확장자: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="167"/>
<source>Comma-separated list of additional attributes to be exported to the BOM. Example: "%1"</source>
<translation>BOM으로 내보낼 쉼표로 구분된 추가 속성의 목록입니다. 예: "%1"</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="170"/>
<source>attributes</source>
<translation>속성</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="173"/>
<source>Export PCB fabrication data (Gerber/Excellon) according the fabrication output settings of boards. Existing files will be overwritten.</source>
<translation>기판의 제작 출력 설정에 따라 PCB 제작 데이터(Gerber/Excellon) 내보내기.
기존 파일을 덮어씁니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="178"/>
<source>Override PCB fabrication output settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation>사용자 지정 설정이 포함된 *.lp 파일을 제공하여 PCB 제작 출력 설정을 재정의합니다. 설정하지 않으면 보드의 설정이 대신 사용됩니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="184"/>
<source>Export pick&place file for automated assembly of the top board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>상단 보드 측면의 자동화된 조립을 위해 pick&place 파일을 내보냅니다. 기존 파일을 덮어씁니다. 지원되는 파일 확장자: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="190"/>
<source>Export pick&place file for automated assembly of the bottom board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>하단 보드 측면의 자동화된 조립을 위해 pick&place 파일을 내보냅니다. 기존 파일을 덮어씁니다. 지원되는 파일 확장자: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="197"/>
<source>Export netlist file for automated PCB testing. Existing files will be overwritten. Supported file extensions: %1</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="202"/>
<source>The name of the board(s) to export. Can be given multiple times. If not set, all boards are exported.</source>
<translation>내보낼 보드의 이름입니다. 여러 번 주어질 수 있습니다. 설정하지 않으면 모든 보드를 내보냅니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="207"/>
<source>Same as '%1', but allows to specify boards by index instead of by name.</source>
<translation>'%1'과(와) 동일하지만 이름 대신 인덱스로 보드를 지정할 수 있습니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="210"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="228"/>
<source>index</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="213"/>
<source>Remove all boards not specified with '%1' from the project before executing all the other actions. If '%1' is not passed, all boards will be removed. Pass '%2' to save the modified project to disk.</source>
<translation>다른 모든 작업을 실행하기 전에 프로젝트에서 '%1'으로 지정되지 않은 모든 보드를 제거하십시오. '%1'이(가) 통과되지 않으면 모든 보드가 제거됩니다. 수정된 프로젝트를 디스크에 저장하려면 '%2'을(를) 전달하십시오.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="220"/>
<source>The name of the assembly variant(s) to export. Can be given multiple times. If not set, all assembly variants are exported.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="225"/>
<source>Same as '%1', but allows to specify assembly variants by index instead of by name.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="231"/>
<source>Move the specified assembly variant to the top before executing all the other actions. Pass '%1' to save the modified project to disk.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="237"/>
<source>Save project before closing it (useful to upgrade file format).</source>
<translation>닫기 전에 프로젝트를 저장하십시오(파일 형식을 업그레이드하는 데 유용).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="240"/>
<source>Fail if the project files are not strictly canonical, i.e. there would be changes when saving the project. Note that this option is not available for *.lppz files.</source>
<translation>프로젝트 파일이 엄격한 표준이 아닌 경우 실패합니다. 즉, 프로젝트를 저장할 때 변경 사항이 있을 수 있습니다. *.lppz 파일에는 이 옵션을 사용할 수 없습니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="247"/>
<source>Perform the selected action(s) on all elements contained in the opened library.</source>
<translation>열려 있는 라이브러리에 포함된 모든 요소에 대해 선택한 작업을 수행합니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="251"/>
<source>Run the library element check, print all non-approved messages and report failure (exit code = 1) if there are non-approved messages.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="255"/>
<source>Minify the STEP models of all packages. Only works in conjunction with '--all'. Pass '--save' to write the minified files to disk.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="259"/>
<source>Save library (and contained elements if '--all' is given) before closing them (useful to upgrade file format).</source>
<translation>라이브러리를 닫기 전에 라이브러리를 저장하십시오 (포함 된 요소에 '-all'이 주어지면) (파일 형식을 업그레이드하는 데 유용합니다).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="263"/>
<source>Fail if the opened files are not strictly canonical, i.e. there would be changes when saving the library elements.</source>
<translation>열린 파일이 엄격하게 표준이 아닌 경우 실패, 즉 라이브러리 요소를 저장할 때 변경 사항이 있을 수 있습니다.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="269"/>
<source>Minify the STEP model before validating it. Use in conjunction with '%1' to save the output of the operation.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="274"/>
<source>Tesselate the loaded STEP model to check if LibrePCB is able to render it. Reports failure (exit code = 1) if no content is detected.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="279"/>
<source>Write the (modified) STEP file to this output location (may be equal to the opened file path). Only makes sense in conjunction with '%1'.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="286"/>
<source>Commands:</source>
<translation>명령:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="290"/>
<source>List command-specific options:</source>
<translation>명령별 옵션 목록:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="293"/>
<source>Help:</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="307"/>
<source>Path to project file (*.lpp[z]).</source>
<translation>프로젝트 파일 경로(*.lpp[z]).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="337"/>
<source>Path to library directory (*.lplib).</source>
<translation>라이브러리 디렉토리 경로(*.lplib).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="348"/>
<source>Path to the STEP file (%1).</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="354"/>
<source>Unknown command '%1'.</source>
<translation>알 수 없는 명령 '%1'.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="411"/>
<source>Missing arguments:</source>
<translation>누락된 인수:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="417"/>
<source>Unknown arguments:</source>
<translation>알 수 없는 인수:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="471"/>
<source>SUCCESS</source>
<translation>성공</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="474"/>
<source>Finished with errors!</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1221"/>
<source>Minify STEP model '%1'...</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1227"/>
<source> - Minified '%1' from %2 to %3 bytes</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1246"/>
<source>Check '%1' for non-canonical files...</source>
<translation>비표준 파일에 대해 '%1' 확인...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1264"/>
<source>Check '%1' for non-approved messages...</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1271"/>
<source>Approved messages: %1</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1273"/>
<source>Non-approved messages: %1</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1284"/>
<source>Save '%1'...</source>
<translation>저장 '%1'...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1420"/>
<source>This application version is UNSTABLE! Option '%1' is disabled to avoid breaking projects or libraries. Please use a stable release instead.</source>
<translation>이 애플리케이션 버전은 불안정합니다! 프로젝트 또는 라이브러리 중단을 방지하기 위해 '%1' 옵션을 사용할 수 없습니다. 대신 안정 버전을 사용하십시오.</translation>
</message>
</context>
<context>
<name>ComponentPrefix</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/componentprefix.h" line="56"/>
<source>Invalid component prefix: '%1'</source>
<translation>잘못된 컴포넌트 접두사: '%1'</translation>
</message>
</context>
<context>
<name>ComponentSymbolVariantItemSuffix</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/componentsymbolvariantitemsuffix.h" line="57"/>
<source>Invalid component symbol suffix: '%1'</source>
<translation>잘못된 컴포넌트 기호 접미사: '%1'</translation>
</message>
</context>
<context>
<name>CopyOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/copyoutputjob.cpp" line="39"/>
<source>Custom File</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/job/copyoutputjob.h" line="78"/>
<source>File Copy</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DesktopIntegration</name>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="135"/>
<source>To avoid troubles, only proceed if there are no other (installed) LibrePCB applications on this computer.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="148"/>
<source>Install Desktop Integration</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="149"/>
<source>This installs the following files to register the executable <i>%1</i>:</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="157"/>
<source>Uninstall Desktop Integration</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="158"/>
<source>This removes the following files:</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="181"/>
<source>Error</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="264"/>
<source>Failed to run '%1'.
Please make sure this tool is available in PATH.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DirectoryLock</name>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="79"/>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="191"/>
<source>The directory "%1" does not exist.</source>
<translation>"%1" 디렉토리가 존재하지 않습니다.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="97"/>
<source>The lock file "%1" has too few lines.</source>
<translation>%1 잠금 파일에 줄이 너무 적습니다.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="170"/>
<source>Could not lock the directory "%1" because it is already locked by "%2". Close any application accessing this directory and try again.</source>
<translation>디렉터리 "%1"은(는) 이미 "%2"에 의해 잠겨 있기 때문에 잠글 수 없습니다. 이 디렉토리에 액세스하는 모든 응용 프로그램을 닫고 다시 시도하십시오.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperBoardClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="625"/>
<source>Clearance via ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="628"/>
<source>The clearance between a via and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="632"/>
<source>Check the DRC settings and move the via away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="647"/>
<source>Clearance trace ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="650"/>
<source>The clearance between a trace and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="654"/>
<source>Check the DRC settings and move the trace away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="670"/>
<source>Clearance pad ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="673"/>
<source>The clearance between a footprint pad and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="677"/>
<source>Check the DRC settings and move the device away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="692"/>
<source>Clearance plane ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="695"/>
<source>The clearance between a plane and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="699"/>
<source>Check the DRC settings and increase the configured plane clearance if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="713"/>
<source>Clearance copper polygon ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="716"/>
<source>The clearance between a polygon and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="719"/>
<source>Check the DRC settings and move the polygon away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="736"/>
<source>Clearance copper circle ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="739"/>
<source>The clearance between a circle and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="742"/>
<source>Check the DRC settings and move the circle away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="758"/>
<source>Clearance copper text ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="761"/>
<source>The clearance between a stroke text and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="765"/>
<source>Check the DRC settings and move the stroke text away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgCopperCopperClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="503"/>
<source>trace</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="505"/>
<source>via</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="507"/>
<source>plane</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="509"/>
<source>polygon</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="511"/>
<source>circle</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="513"/>
<source>text</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="582"/>
<source>Clearance on %1: %2 ↔ %3 < %4 %5</source>
<comment>Placeholders: Layer name, object name, object name, Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="587"/>
<source>The clearance between two copper objects of different nets is smaller than the minimum copper clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="591"/>
<source>Check the DRC settings and move the objects to increase their clearance if needed.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="613"/>
<source>%1 layers</source>
<comment>Placeholder is a number > 1.</comment>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgCopperHoleClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="787"/>
<source>Clearance copper ↔ hole < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="790"/>
<source>The clearance between a non-plated hole and copper objects is smaller than the hole clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="793"/>
<source>Check the DRC settings and move the copper objects away from the hole if needed.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgCopperInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="816"/>
<source>Pad in copper keepout zone: '%1'</source>
<comment>Placeholder is pad name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="833"/>
<source>Via in copper keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="850"/>
<source>Trace in copper keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="864"/>
<source>Polygon in copper keepout zone</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="878"/>
<source>Polygon in copper keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="895"/>
<source>Circle in copper keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="918"/>
<source>There is a copper object within a copper keepout zone.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="919"/>
<source>Move the object to outside the keepout zone.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgDeviceInCourtyard</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="986"/>
<source>Device in courtyard: '%1' ↔ '%2'</source>
<comment>Placeholders: Device 1 name, device 2 name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="990"/>
<source>A device is placed within the courtyard of another device, which might cause troubles during assembly of these parts.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="993"/>
<source>Either move the devices to increase their clearance or approve this message if you're sure they can be assembled without problems.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgDeviceInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1042"/>
<source>Device in keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1063"/>
<source>There is a device within a keepout zone.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1064"/>
<source>Move the device to outside the keepout zone.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgDisabledLayer</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1521"/>
<source>Objects on disabled layer: '%1'</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1522"/>
<source>The layer contains copper objects, but it is disabled in the board setup dialog and thus will be ignored in any production data exports. Either increase the layer count to get this layer exported, or remove all objects on this layer (by temporarily enabling this layer to see them).</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgDrillBoardClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="962"/>
<source>Clearance drill ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="965"/>
<source>The clearance between a drill and the board outline is smaller than the drill clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="968"/>
<source>Check the DRC settings and move the drill away from the board outline if needed.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgDrillDrillClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="930"/>
<source>Clearance drill ↔ drill < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="933"/>
<source>The clearance between two drills is smaller than the drill clearance configured in the DRC settings.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="936"/>
<source>Check the DRC settings and move the drills to increase their distance if needed.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgEmptyNetSegment</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="276"/>
<source>Empty segment of net '%1': '%2'</source>
<comment>Placeholders: Net name, segment UUID</comment>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgExposureInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1078"/>
<source>Pad in exposure keepout zone: '%1'</source>
<comment>Placeholder is pad name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1095"/>
<source>Via in exposure keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1109"/>
<source>Polygon in exposure keepout zone</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1122"/>
<source>Polygon in exposure keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1139"/>
<source>Circle in exposure keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1163"/>
<source>There is a solder resist opening within an exposure keepout zone.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1165"/>
<source>Move the object to outside the keepout zone.</source>
<translation type="unfinished"/>
</message>
</context>
<context>
<name>DrcMsgForbiddenSlot</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1375"/>
<source>Hole is a slot with curves</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1377"/>
<source>Hole is a multi-segment slot</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1379"/>
<source>Hole is a slot</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1386"/>
<source>Either avoid them or check if your PCB manufacturer supports them.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1388"/>
<source>Choose the desired Excellon slot mode when generating the production data (G85 vs. G00..G03).</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1391"/>
<source>The drilled slot mode (G85) will not be available when generating production data.</source>
<translation type="unfinished"/>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1395"/>