Add BL5340PA

boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi

@@ -112,7 +112,7 @@
 		compatible = "zephyr,mipi-dbi-spi";
 		reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 		dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
-		spi-dev = <&spi2>;
+		spi-dev = <&spi4>;
 		write-only;
 		#address-cells = <1>;
 		#size-cells = <0>;

boards/lairdconnect/bl5340pa_dvk/CMakeLists.txt

@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA.
+# Copyright (c) 2021-2024 Laird Connectivity.
+# SPDX-License-Identifier: Apache-2.0
+
+if((CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS)
+   AND CONFIG_BOARD_ENABLE_CPUNET)
+  zephyr_library()
+  zephyr_library_sources(bl5340pa_dvk_nrf5340_cpunet_reset.c)
+
+  if(CONFIG_BUILD_WITH_TFM)
+    zephyr_library_include_directories(
+      $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/interface/include
+    )
+  endif()
+endif()

boards/lairdconnect/bl5340pa_dvk/Kconfig

@@ -0,0 +1,62 @@
+# BL5340-DVK board configuration
+
+# Copyright (c) 2019-2021 Nordic Semiconductor ASA
+# Copyright (c) 2021-2024 Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+config BOARD_ENABLE_DCDC_APP
+	bool "Application MCU DCDC converter"
+	select SOC_DCDC_NRF53X_APP
+	default y
+
+config BOARD_ENABLE_DCDC_NET
+	bool "Network MCU DCDC converter"
+	select SOC_DCDC_NRF53X_NET
+	default y
+
+config BOARD_ENABLE_DCDC_HV
+	bool "High Voltage DCDC converter"
+	select SOC_DCDC_NRF53X_HV
+	default y
+
+config BOARD_ENABLE_CPUNET
+	bool "NRF53 Network MCU"
+	select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \
+		$(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
+	help
+	  This option enables releasing the Network 'force off' signal, which
+	  as a consequence will power up the Network MCU during system boot.
+	  Additionally, the option allocates GPIO pins that will be used by UARTE
+	  of the Network MCU.
+	  Note: GPIO pin allocation can only be configured by the secure Application
+	  MCU firmware, so when this option is used with the non-secure version of
+	  the board, the application needs to take into consideration, that the
+	  secure firmware image must already have configured GPIO allocation for the
+	  Network MCU.
+	default y if (BT || NRF_802154_SER_HOST)
+
+config DOMAIN_CPUNET_BOARD
+	string
+	default "bl5340pa_dvk/nrf5340/cpunet"
+	depends on BOARD_ENABLE_CPUNET
+	help
+	  The board which will be used for CPUNET domain when creating a multi
+	  image application where one or more images should be located on
+	  another board. For example hci_ipc on the bl5340pa_dvk_cpunet for
+	  Bluetooth applications.
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUNET
+
+config DOMAIN_CPUAPP_BOARD
+	string
+	default "bl5340pa_dvk/nrf5340/cpuapp"
+	help
+	  The board which will be used for CPUAPP domain when creating a multi
+	  image application where one or more images should be located on
+	  another board.
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUNET

boards/lairdconnect/bl5340pa_dvk/Kconfig.bl5340pa_dvk

@@ -0,0 +1,9 @@
+# BL5340PA-DVK board configuration
+
+# Copyright (c) 2021-2024 Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL5340PA_DVK
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUAPP
+	select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+	select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUNET

boards/lairdconnect/bl5340pa_dvk/Kconfig.defconfig

@@ -0,0 +1,137 @@
+# BL5340-DVK board configuration
+
+# Copyright (c) 2019-2020 Nordic Semiconductor ASA
+# Copyright (c) 2021-2024 Laird Connectivity
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+config I2C
+	default GPIO || DAC
+
+# Code Partition:
+#
+# For the secure version of the board the firmware is linked at the beginning
+# of the flash, or into the code-partition defined in DT if it is intended to
+# be loaded by MCUboot. If the secure firmware is to be combined with a non-
+# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
+# be restricted to the size of its code partition.
+#
+# For the non-secure version of the board, the firmware
+# must be linked into the code-partition (non-secure) defined in DT, regardless.
+# Apply this configuration below by setting the Kconfig symbols used by
+# the linker according to the information extracted from DT partitions.
+
+# SRAM Partition:
+#
+# If the secure firmware is to be combined with a non-secure image
+# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
+# be restricted to the secure image SRAM partition (sram-secure-partition).
+# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
+# may be used by the image.
+#
+# For the non-secure version of the board, the firmware image SRAM is
+# always restricted to the allocated non-secure SRAM partition.
+#
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config SRAM_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+choice BT_HCI_BUS_TYPE
+	default BT_HCI_IPC if BT
+endchoice
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BT_HCI_IPC
+
+config BT_HCI_VS
+	default y if BT
+
+# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module
+# is mounted to the DVK using standoffs.
+# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module
+if DISPLAY
+
+config INPUT_FT5336_INTERRUPT
+	default y
+
+if LVGL
+
+config LV_Z_VDB_SIZE
+	default 64
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+config LV_COLOR_16_SWAP
+	default y
+
+config INPUT
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS
+
+config IPM_NRFX
+	default IPM
+
+config MBOX_NRFX_IPC
+	default MBOX
+
+if BOARD_BL5340PA_DVK_NRF5340_CPUNET
+
+# BT_CTLR depends on BT. When BT is enabled we should default to also
+# enabling the controller.
+config BT_CTLR
+	default y if BT
+
+config BT_ECC
+	default y if BT
+
+if MPSL_FEM
+
+config MPSL_FEM_NRF21540_TX_GAIN_DB
+	default 20
+
+config BT_CTLR_TX_PWR_ANTENNA
+	default 20
+
+choice MPSL_FEM_CHOICE
+	depends on MPSL_FEM_NRF21540_GPIO_SPI_SUPPORT
+	default MPSL_FEM_NRF21540_GPIO_SPI
+endchoice
+
+config MAIN_STACK_SIZE
+	default 2048
+
+endif # MPSL_FEM
+
+endif # BOARD_BL5340PA_DVK_NRF5340_CPUNET

boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.dts

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021-2024 Laird Connectivity
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
+#include "bl5340pa_dvk_nrf5340_cpuapp_common.dtsi"
+
+/ {
+	model = "Laird Connectivity BL5340PA (nRF5340 with nRF21540) Application";
+	compatible = "lairdconnect,bl5340pa-dvk-cpuapp";
+
+	chosen {
+		zephyr,sram = &sram0_image;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram-secure-partition = &sram0_s;
+		zephyr,sram-non-secure-partition = &sram0_ns;
+	};
+};
+
+zephyr_udc0: &usbd {
+	compatible = "nordic,nrf-usbd";
+	status = "okay";
+};
+
+&gpio_fwd {
+	nrf21540-gpio-if {
+		gpios = <&gpio0 4 0>, /* antenna select */
+				<&gpio0 31 0>, /* rx-en-gpios */
+				<&gpio0 30 0>, /* tx-en-gpios */
+				<&gpio0 29 0>; /* pdn-gpios */
+	};
+	nrf21540-spi-if {
+		gpios = <&gpio1 0 0>, /* clk */
+				<&gpio1 1 0>, /* mosi */
+				<&gpio1 5 0>, /* csn */
+				<&gpio1 4 0>; /* miso */
+	};
+};

boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.yaml

@@ -0,0 +1,22 @@
+identifier: bl5340pa_dvk/nrf5340/cpuapp
+name: BL5340PA-DVK-application-MCU
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 448
+flash: 1024
+supported:
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - qspi
+  - spi
+  - uart
+  - usb_cdc
+  - usb_device
+  - watchdog
+vendor: lairdconnect