diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi index ff29e1f176e..b10199649d0 100644 --- a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -112,7 +112,7 @@ compatible = "zephyr,mipi-dbi-spi"; reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi2>; + spi-dev = <&spi4>; write-only; #address-cells = <1>; #size-cells = <0>; diff --git a/boards/lairdconnect/bl5340pa_dvk/CMakeLists.txt b/boards/lairdconnect/bl5340pa_dvk/CMakeLists.txt new file mode 100644 index 00000000000..0dedc6b671b --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA. +# Copyright (c) 2021-2024 Laird Connectivity. +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(bl5340pa_dvk_nrf5340_cpunet_reset.c) + + if(CONFIG_BUILD_WITH_TFM) + zephyr_library_include_directories( + $/api_ns/interface/include + ) + endif() +endif() diff --git a/boards/lairdconnect/bl5340pa_dvk/Kconfig b/boards/lairdconnect/bl5340pa_dvk/Kconfig new file mode 100644 index 00000000000..26065f27ec3 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/Kconfig @@ -0,0 +1,62 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2021 Nordic Semiconductor ASA +# Copyright (c) 2021-2024 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "bl5340pa_dvk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the bl5340pa_dvk_cpunet for + Bluetooth applications. + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +if BOARD_BL5340PA_DVK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "bl5340pa_dvk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340pa_dvk/Kconfig.bl5340pa_dvk b/boards/lairdconnect/bl5340pa_dvk/Kconfig.bl5340pa_dvk new file mode 100644 index 00000000000..6f0c46be6e0 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/Kconfig.bl5340pa_dvk @@ -0,0 +1,9 @@ +# BL5340PA-DVK board configuration + +# Copyright (c) 2021-2024 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL5340PA_DVK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340PA_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340pa_dvk/Kconfig.defconfig b/boards/lairdconnect/bl5340pa_dvk/Kconfig.defconfig new file mode 100644 index 00000000000..88b8c21832b --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/Kconfig.defconfig @@ -0,0 +1,137 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# Copyright (c) 2021-2024 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +config I2C + default GPIO || DAC + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL5340PA_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HCI_VS + default y if BT + +# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module +# is mounted to the DVK using standoffs. +# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module +if DISPLAY + +config INPUT_FT5336_INTERRUPT + default y + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +config INPUT + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUAPP || BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_BL5340PA_DVK_NRF5340_CPUNET + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +config BT_ECC + default y if BT + +if MPSL_FEM + +config MPSL_FEM_NRF21540_TX_GAIN_DB + default 20 + +config BT_CTLR_TX_PWR_ANTENNA + default 20 + +choice MPSL_FEM_CHOICE + depends on MPSL_FEM_NRF21540_GPIO_SPI_SUPPORT + default MPSL_FEM_NRF21540_GPIO_SPI +endchoice + +config MAIN_STACK_SIZE + default 2048 + +endif # MPSL_FEM + +endif # BOARD_BL5340PA_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.dts b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.dts new file mode 100644 index 00000000000..f6d066d1b61 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2021-2024 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340pa_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340PA (nRF5340 with nRF21540) Application"; + compatible = "lairdconnect,bl5340pa-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +&gpio_fwd { + nrf21540-gpio-if { + gpios = <&gpio0 4 0>, /* antenna select */ + <&gpio0 31 0>, /* rx-en-gpios */ + <&gpio0 30 0>, /* tx-en-gpios */ + <&gpio0 29 0>; /* pdn-gpios */ + }; + nrf21540-spi-if { + gpios = <&gpio1 0 0>, /* clk */ + <&gpio1 1 0>, /* mosi */ + <&gpio1 5 0>, /* csn */ + <&gpio1 4 0>; /* miso */ + }; +}; diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.yaml b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000..c6657f6b055 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp.yaml @@ -0,0 +1,22 @@ +identifier: bl5340pa_dvk/nrf5340/cpuapp +name: BL5340PA-DVK-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - counter + - gpio + - i2c + - pwm + - qspi + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common-pinctrl.dtsi new file mode 100644 index 00000000000..a5d9b72b62e --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common-pinctrl.dtsi @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi4_default: spi4_default { + group1 { + psels = , + , + ; + }; + }; + + spi4_sleep: spi4_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + uart0_default: uart0_default { + group1 { + psels = , + , + , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = , + , + , + ; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + qspi_default: qspi_default { + group1 { + psels = , + , + , + , + , + ; + }; + }; + + qspi_sleep: qspi_sleep { + group1 { + psels = , + , + , + , + , + ; + low-power-enable; + }; + }; + +}; diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000..94e6792cd84 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_common.dtsi @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2019-2023 Nordic Semiconductor ASA + * Copyright (c) 2021-2024 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bl5340pa_dvk_nrf5340_cpuapp_common-pinctrl.dtsi" +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,display = &ili9340; + zephyr,bt-hci-ipc = &ipc0; + }; + + /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ + /* Note TCA9538 does not have configurable internal pull ups/ downs */ + buttons { + compatible = "gpio-keys"; + boot_button0: boot_button { + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + label = "Bootloader button (S4)"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 1 (S1)"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 2 (S2)"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 3 (S9)"; + zephyr,code = ; + }; + + button4: button_4 { + gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; + label = "Push button switch 4 (S10)"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + led2: led_2 { + gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; + label = "Blue LED 2"; + }; + led3: led_3 { + gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; + label = "Blue LED 3"; + }; + led4: led_4 { + gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; + label = "Blue LED 4"; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + swap-xy; + invert-x; + invert-y; + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "okay"; + uart { + gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + led3 = &led4; + sw0 = &button1; + sw1 = &button2; + sw2 = &button3; + sw3 = &button4; + mcuboot-button0 = &button1; + mcuboot-led0 = &led1; + sdhc0 = &sdhc0; + watchdog0 = &wdt0; + accel0 = &lis3dh; + bbram0 = &extrtc0; + spi-flash0 = &mx25r64; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi4>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + reg = <0>; + mipi-max-frequency = <32000000>; + rotation = <270>; + width = <320>; + height = <240>; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; + at24c256@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <32768>; + pagesize = <64>; + address-width = <16>; + timeout = <10>; + }; + + lis3dh: lis3dh@18 { + compatible = "st,lis2dh"; + reg = <0x18>; + irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; + + dac0: mcp4725@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + #io-channel-cells = <1>; + }; + + extrtc0: mcp7940n@6f { + compatible = "microchip,mcp7940n"; + reg = <0x6f>; + status = "okay"; + }; + + gpio_exp0: tca9538@70 { + compatible = "ti,tca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; +}; + +&spi2 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; + enc424j600@0 { + compatible = "microchip,enc424j600"; + reg = <0>; + spi-max-frequency = <8000000>; + int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + }; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + sdhc0: sdhc@0 { + reg = <0>; + compatible = "zephyr,sdhc-spi-slot"; + status = "okay"; + spi-max-frequency = <8000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + }; +}; + +&spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 64K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + /* 640K */ + slot0_partition: partition@10000 { + label = "image-0"; + }; + /* 256K */ + slot0_ns_partition: partition@b0000 { + label = "image-0-nonsecure"; + }; + + /* + * The flash starting at 0x000f8000 and ending at + * 0x000fffff is reserved for use by the application. + */ + + /* + * Storage partition will be used by FCB/NVS + * if enabled. 32K + */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +&mx25r64 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 640K */ + slot1_partition: partition@0 { + label = "image-1"; + }; + /* 256K */ + slot1_ns_partition: partition@A0000 { + label = "image-1-nonsecure"; + }; + /* 128K */ + scratch_partition: partition@e0000 { + label = "image-scratch"; + reg = <0x000e0000 0x00020000>; + }; + /* 7MB */ + lfs_partition: partition@100000 { + label = "lfs_storage"; + reg = <0x00100000 0x00700000>; + }; + }; +}; + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + }; + + sram0_ns: image_ns@20040000 { + /* Non-Secure image memory */ + }; + }; +}; + +/* Include partition configuration file */ +#include "bl5340pa_dvk_nrf5340_cpuapp_partition_conf.dtsi" diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_defconfig b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000..b584dd950ac --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_defconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Setup clocks +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y +CONFIG_SOC_LFXO_CAP_INT_7PF=y +CONFIG_SOC_HFXO_CAP_INTERNAL=y +CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 + +CONFIG_PINCTRL=y diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.dts b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.dts new file mode 100644 index 00000000000..969b573d779 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021-2024 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340pa_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340PA (nRF5340 with nRF21540) Application"; + compatible = "lairdconnect,bl5340pa-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +&qspi { + status = "disabled"; + + /* Drop the flash and partitions to avoid the config being used for DFU + * samples. + */ + /delete-node/ mx25r6435f@0; +}; diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.yaml b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.yaml new file mode 100644 index 00000000000..a79fe27f738 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns.yaml @@ -0,0 +1,21 @@ +identifier: bl5340pa_dvk/nrf5340/cpuapp/ns +name: BL5340PA-DVK-application-MCU-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 192 +supported: + - counter + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns_defconfig b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000..11ad4bacc89 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_partition_conf.dtsi new file mode 100644 index 00000000000..5c837e376da --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpuapp_partition_conf.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019-2020 Nordic Semiconductor ASA + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Default Flash planning for bl5340_dvk CPUAPP (Application MCU). + * + * Zephyr build for BL5340 with ARM TrustZone-M support + * implies building Secure and Non-Secure Zephyr images. + * + * Secure image will be placed, by default, in flash0 + * (or in slot0, if MCUboot is present). + * Secure image will use sram0 for system memory. + * + * Non-Secure image will be placed in slot0_ns, and use + * sram0_ns for system memory. + * + * Note that the Secure image only requires knowledge of + * the beginning of the Non-Secure image (not its size). + */ + +&slot0_partition { + reg = <0x00010000 0xa0000>; +}; + +&slot0_ns_partition { + reg = <0x000b0000 0x40000>; +}; + +&slot1_partition { + reg = <0x00000000 0xa0000>; +}; + +&slot1_ns_partition { + reg = <0x000a0000 0x40000>; +}; + +/* Default SRAM planning when building for nRF5340 with + * ARM TrustZone-M support + * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) + * - Middle 192 kB allocated to Non-Secure image (sram0_ns) + * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) + * (see bl5340_dvk_shared_sram_planning_conf.dtsi) + */ +&sram0_image { + reg = <0x20000000 DT_SIZE_K(448)>; +}; + +&sram0_s { + reg = <0x20000000 0x40000>; +}; + +&sram0_ns { + reg = <0x20040000 0x30000>; +}; + +/* Include shared RAM configuration file */ +#include "bl5340pa_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet-pinctrl.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet-pinctrl.dtsi new file mode 100644 index 00000000000..54dd604f82c --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet-pinctrl.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + , + , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.dts b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.dts new file mode 100644 index 00000000000..2f655889e33 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021-2024 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340pa_dvk_nrf5340_cpunet-pinctrl.dtsi" +#include "bl5340pa_dvk_nrf5340_cpunet_common.dtsi" + +/ { + model = "Laird Connectivity BL5340PA (nRF5340 with nRF21540) Network"; + compatible = "lairdconnect,bl5340pa-dvk-cpunet"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci-ipc = &ipc0; + }; + + aliases { + watchdog0 = &wdt0; + }; + + nrf_radio_fem: nrf21540_fem { + compatible = "nordic,nrf21540-fem"; + rx-en-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + tx-en-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + pdn-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + spi-if = <&nrf_radio_fem_spi>; + supply-voltage-mv = <3300>; + }; + + /* The Laird Connectivity driver that ensures regulatory compliance and + * proper GPIO control requires the Nordic Connect SDK (MPSL FEM driver). + * The default is external antenna and FCC/IC region. + * + * Add 'internal-antenna;' to use the internal antenna verison. + * Change to'power-table = <1>;' for Australia/NZ. + */ + lcz_fem: nrf21540_lcz_fem { + compatible = "lairdconnect,nrf21540-lcz-fem"; + ant-sel-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + spi-clk-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + spi-mosi-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + spi-csn-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + spi-miso-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + power-table = <0>; + }; +}; + +&radio { + fem = <&nrf_radio_fem>; +}; + +/* Can't be used with SPI0/FEM */ +&uart0 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + status = "okay"; + cs-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; + + nrf_radio_fem_spi: nrf21540_fem_spi@0 { + status = "okay"; + compatible = "nordic,nrf21540-fem-spi"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; \ No newline at end of file diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.yaml b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.yaml new file mode 100644 index 00000000000..28f7acd576b --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet.yaml @@ -0,0 +1,19 @@ +identifier: bl5340pa_dvk/nrf5340/cpunet +name: BL5340PA-DVK-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - ble + - counter + - gpio + - i2c + - spi + - uart + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_common.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_common.dtsi new file mode 100644 index 00000000000..d0f3f30a74b --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_common.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&flash1 { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 48K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + /* 88K */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x16000>; + }; + /* 88K */ + slot1_partition: partition@22000 { + label = "image-1"; + reg = <0x00022000 0x16000>; + }; + /* 32K */ + storage_partition: partition@38000 { + label = "storage"; + reg = <0x00038000 0x8000>; + }; + }; +}; + +/* Include shared RAM configuration file */ +#include "bl5340pa_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_defconfig b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000..bc698cb29cb --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +CONFIG_PINCTRL=y diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_reset.c b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_reset.c new file mode 100644 index 00000000000..cce782e4a98 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_cpunet_reset.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019-2021 Nordic Semiconductor ASA. + * Copyright (c) 2021-2024 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include + +LOG_MODULE_REGISTER(bl5340pa_dvk_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); + +#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) +#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> +#else +#define DEBUG_SETUP() +#endif + +static void remoteproc_mgr_config(void) +{ +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) + /* Route Bluetooth Controller Debug Pins */ + DEBUG_SETUP(); +#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ + +#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) + /* Retain nRF5340 Network MCU in Secure domain (bus + * accesses by Network MCU will have Secure attribute set). + */ + NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; +#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ +} + +static int remoteproc_mgr_boot(void) +{ + + /* Secure domain may configure permissions for the Network MCU. */ + remoteproc_mgr_config(); + +#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) + /* + * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies + * building also a Non-Secure image. The Non-Secure image will, in + * this case do the remainder of actions to properly configure and + * boot the Network MCU. + */ + + /* Release the Network MCU, 'Release force off signal' */ + nrf_reset_network_force_off(NRF_RESET, false); + + LOG_DBG("Network MCU released."); +#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ + + return 0; +} + +SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_shared_sram_planning_conf.dtsi b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_shared_sram_planning_conf.dtsi new file mode 100644 index 00000000000..fbb059494c3 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/bl5340pa_dvk_nrf5340_shared_sram_planning_conf.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019 Nordic Semiconductor ASA + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Default shared SRAM planning when building for BL5340 DVK. + * This file is included by both nRF5340 CPUAPP (Application MCU) + * and nRF5340 CPUNET (Network MCU). + * - 64 kB SRAM allocated as Shared memory (sram0_shared) + * - Region defined after the image SRAM of Application MCU + */ + +/ { + chosen { + /* shared memory reserved for the inter-processor communication */ + zephyr,ipc_shm = &sram0_shared; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_shared: memory@20070000 { + /* SRAM allocated to shared memory */ + reg = <0x20070000 0x10000>; + }; + }; +}; diff --git a/boards/lairdconnect/bl5340pa_dvk/board.cmake b/boards/lairdconnect/bl5340pa_dvk/board.cmake new file mode 100644 index 00000000000..5441735c28e --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340PA_DVK_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(BOARD_BL5340PA_DVK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/lairdconnect/bl5340pa_dvk/board.yml b/boards/lairdconnect/bl5340pa_dvk/board.yml new file mode 100644 index 00000000000..64bbed6b67c --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/board.yml @@ -0,0 +1,8 @@ +board: + name: bl5340pa_dvk + vendor: lairdconnect + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/lairdconnect/bl5340pa_dvk/doc/img/bl5340pa_dvk_side.png b/boards/lairdconnect/bl5340pa_dvk/doc/img/bl5340pa_dvk_side.png new file mode 100644 index 00000000000..ff81c2ef6aa Binary files /dev/null and b/boards/lairdconnect/bl5340pa_dvk/doc/img/bl5340pa_dvk_side.png differ diff --git a/boards/lairdconnect/bl5340pa_dvk/doc/index.rst b/boards/lairdconnect/bl5340pa_dvk/doc/index.rst new file mode 100644 index 00000000000..86465d024da --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/doc/index.rst @@ -0,0 +1,455 @@ +.. _bl5340pa_dvk: + +Laird Connectivity BL5340PA DVK +############################### + +Overview +******** +The BL5340PA Development Kit provides support for the Laird +Connectivity BL5340PA module which is powered by a dual-core Nordic +Semiconductor nRF5340 ARM Cortex-M33F CPU and a Nordic Semiconductor +nRF21540 FEM (Front end module) to boost the output power. The nRF5340 +inside the BL5340 module is a dual-core SoC based on the Arm® +Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``bl5340pa_dvk/nrf5340/cpuapp`` build target provides support for the application +core on the BL5340PA module. The ``bl5340pa_dvk/nrf5340/cpunet`` build target provides +support for the network core on the BL5340PA module. If ARM TrustZone is +used then the ``bl5340pa_dvk/nrf5340/cpuapp`` build target provides support for the +non-secure partition of the application core on the BL5340PA module. + +For regulatory compliance, lower power operation, and external antenna +selection the Laird Connectivity forks of the Nordic Connect SDK and branches +must be used when the radio is enabled. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4 with FEM) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bl5340pa_dvk_side.png + :align: center + :alt: BL5340PA DVK + + BL5340PA DVK (Credit: Laird Connectivity) + +More information about the module can be found on the +`BL5340 homepage`_. + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The BL5340PA DVK has two external oscillators. The frequency of +the slow clock is 32.768KHz. The frequency of the main clock +is 32MHz. + +Supported Features +================== + +The ``bl5340pa_dvk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``bl5340pa_dvk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of hardware features. + +Connections and IOs +=================== + +An eight-pin GPIO port expander is used to provide additional inputs +and outputs to the BL5340PA module. + +Refer to the `TI TCA9538 datasheet`_ for further details. + +LEDs +---- + +* LED1 (blue) = via TCA9538 port expander channel P4 (active low) +* LED2 (blue) = via TCA9538 port expander channel P5 (active low) +* LED3 (blue) = via TCA9538 port expander channel P6 (active low) +* LED4 (blue) = via TCA9538 port expander channel P7 (active low) + +Push buttons +------------ + +* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) +* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) +* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) +* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) +* BOOT = boot (active low) + +External Memory +=============== + +Several external memory sources are available for the BL5340PA DVK. +These are described as follows. + +Flash Memory +------------ + +A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is +incorporated for application image storage and large datasets. + +Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. + +EEPROM Memory +------------- + +A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for +storage of infrequently updated data and small datasets. + +Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. + +External Memory +--------------- + +An on-board micro SD card slot is available for use with micro SD cards. + +Sensors +======= + +The BL5340 DVK incorporates two sensors for user application testing. +These are described as follows. + +Temperature, Pressure, Humidity & Air Quality Sensor +---------------------------------------------------- + +A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is +available via I2C for environmental measurement applications. + +Refer to the `Bosch BME680 datasheet`_ for further details. + +3-Axis Accelerometer +-------------------- + +An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C +for vibration and motion detection applications. + +Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. + +Ethernet +======== + +Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip +ENC424J600 Ethernet controller. + +Refer to the `Microchip ENC424J600 datasheet`_ for further details. + +TFT Display & Capacitive Touch Screen Controller +================================================ + +A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch +controller is included with the BL5340 DVK for user interface +application features. + +Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the +display. + +An ILI9341 TFT controller is incorporated in the TFT module and +acts as the main controller, controlled via SPI. + +Refer to the `ILI9341 datasheet`_ for further details. + +An FT6206 Capacitive Touch Controller, controlled via I2C is +also incorporated in the TFT module. + +Refer to the `FT6206 datasheet`_ for further details. + +Real-Time Clock +=============== + +A real-time clock is available for accurate time data availability. + +Refer to the `Microchip MCP7940N datasheet`_ for further details. + +DAC +=== + +A 10-bit Digital to Analog Converter is incorporated for generation of +variable voltages. + +Refer to the `Microchip MCP4725 datasheet`_ for further details. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application + core. The IDAU is implemented with the System Protection Unit and is + used to define secure and non-secure memory maps. By default, all of + the memory space (Flash, SRAM, and peripheral address space) is + defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +The BL5340PA's application core supports the Armv8-M Security Extension. +Applications built for the ``bl5340pa_dvk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +The BL5340PA's network core does not support the Armv8-M Security +Extension. The IDAU may configure bus accesses by the network core to +have Secure attribute set; the latter allows to build and run Secure +only applications on the BL5340PA module. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the BL5340PA module may contain a Secure and a Non-Secure +firmware image for the application core. The Secure image can be built +using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure +firmware images are always built using Zephyr. The two alternatives are +described below. + +.. note:: + + By default the Secure image for BL5340PA's application core is + built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the +Non-Secure firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=bl5340pa_dvk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may + be required, to adjust the Non-Secure image Flash and SRAM starting + address and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=bl5340pa_dvk/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=bl5340pa_dvk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=bl5340pa_dvk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=bl5340pa_dvk/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the BL5340PA's +application core, the Secure application will have to set the IDAU +(SPU) configuration to allow Non-Secure access to all CPU resources +utilized by the Non-Secure application firmware. SPU configuration +shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=bl5340pa_dvk/nrf5340/cpuapp`` for +the firmware running on the BL5340's application core, and using +``-DBOARD=bl5340pa_dvk/nrf5340/cpunet`` for the firmware running +on the BL5340PA's network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The BL5340 has a flash read-back protection feature. When flash + read-back protection is active, you will need to recover the chip + before reflashing. If you are flashing with + :ref:`west `, run this command for more + details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the BL5340PA DVK requires + upgrading the nRF Command Line Tools to version 10.12.0 or newer. + Further information on how to install the nRF Command Line Tools can + be found in :ref:`nordic_segger_flashing`. + +Here is an example for the :ref:`hello_world` application running on the +BL5340PA's application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BL5340PA DVK board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl5340pa_dvk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +boards with a Segger IC. + +Testing Bluetooth on the BL5340PA DVK +************************************* +Many of the Bluetooth examples will work on the BL5340PA DVK. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +Regulatory Warning +****************** + +Note that the FEM on the BL5340PA module can boost the power of the +output signal by up to 20dBm, however this may not be compliant with +regulatory limits. The Nordic default gain for the FEM is 10 dBm. +The Laird Connectivity FEM driver defaults to 20 dBm and limits +the power at the antenna based on antenna type and region (by decreasing +the output power of the nRF5340). +Note that Laird Connectivity accepts no responsibility for regulatory issues +with end products. It is entirely the responsibility of the +device/end product manufacturer and/or designer. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 +.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf +.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf +.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf +.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf +.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf +.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf +.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf +.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf +.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf +.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/lairdconnect/bl5340pa_dvk/pre_dt_board.cmake b/boards/lairdconnect/bl5340pa_dvk/pre_dt_board.cmake new file mode 100644 index 00000000000..fb045e38545 --- /dev/null +++ b/boards/lairdconnect/bl5340pa_dvk/pre_dt_board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - flash-controller@39000 & kmu@39000 +# - power@5000 & clock@5000 +# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/samples/bluetooth/hci_ipc/prj.conf b/samples/bluetooth/hci_ipc/prj.conf index 39c20b23cab..7ed2a31a32f 100644 --- a/samples/bluetooth/hci_ipc/prj.conf +++ b/samples/bluetooth/hci_ipc/prj.conf @@ -3,7 +3,7 @@ CONFIG_MBOX=y CONFIG_HEAP_MEM_POOL_SIZE=8192 -CONFIG_MAIN_STACK_SIZE=512 +CONFIG_MAIN_STACK_SIZE=2048 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512 CONFIG_BT=y